authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 02:51:35-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 02:51:35-07:00
log280195038a8f3a364ff95adb5d3799f586e5b695
treeb80510e9735b396dd6b79cad984ee8bd50aebc46
parent9e8943736e34d28d1ea62229d6ca708303cd0eba

std.Target: add powerpcle

3 files changed, 12 insertions(+), 6 deletions(-)

lib/std/target.zig+10-6
...@@ -722,6 +722,7 @@ pub const Target = struct {...@@ -722,6 +722,7 @@ pub const Target = struct {
722 mips64el,722 mips64el,
723 msp430,723 msp430,
724 powerpc,724 powerpc,
725 powerpcle,
725 powerpc64,726 powerpc64,
726 powerpc64le,727 powerpc64le,
727 r600,728 r600,
...@@ -832,7 +833,7 @@ pub const Target = struct {...@@ -832,7 +833,7 @@ pub const Target = struct {
832 .le32 => ._NONE,833 .le32 => ._NONE,
833 .mips => ._MIPS,834 .mips => ._MIPS,
834 .mipsel => ._MIPS_RS3_LE,835 .mipsel => ._MIPS_RS3_LE,
835 .powerpc => ._PPC,836 .powerpc, .powerpcle => ._PPC,
836 .r600 => ._NONE,837 .r600 => ._NONE,
837 .riscv32 => ._RISCV,838 .riscv32 => ._RISCV,
838 .sparc => ._SPARC,839 .sparc => ._SPARC,
...@@ -892,7 +893,7 @@ pub const Target = struct {...@@ -892,7 +893,7 @@ pub const Target = struct {
892 .le32 => .Unknown,893 .le32 => .Unknown,
893 .mips => .Unknown,894 .mips => .Unknown,
894 .mipsel => .Unknown,895 .mipsel => .Unknown,
895 .powerpc => .POWERPC,896 .powerpc, .powerpcle => .POWERPC,
896 .r600 => .Unknown,897 .r600 => .Unknown,
897 .riscv32 => .RISCV32,898 .riscv32 => .RISCV32,
898 .sparc => .Unknown,899 .sparc => .Unknown,
...@@ -965,6 +966,7 @@ pub const Target = struct {...@@ -965,6 +966,7 @@ pub const Target = struct {
965 .nvptx64,966 .nvptx64,
966 .sparcel,967 .sparcel,
967 .tcele,968 .tcele,
969 .powerpcle,
968 .powerpc64le,970 .powerpc64le,
969 .r600,971 .r600,
970 .riscv32,972 .riscv32,
...@@ -1021,6 +1023,7 @@ pub const Target = struct {...@@ -1021,6 +1023,7 @@ pub const Target = struct {
1021 .mips,1023 .mips,
1022 .mipsel,1024 .mipsel,
1023 .powerpc,1025 .powerpc,
1026 .powerpcle,
1024 .r600,1027 .r600,
1025 .riscv32,1028 .riscv32,
1026 .sparc,1029 .sparc,
...@@ -1077,7 +1080,7 @@ pub const Target = struct {...@@ -1077,7 +1080,7 @@ pub const Target = struct {
1077 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",1080 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
1078 .bpfel, .bpfeb => "bpf",1081 .bpfel, .bpfeb => "bpf",
1079 .mips, .mipsel, .mips64, .mips64el => "mips",1082 .mips, .mipsel, .mips64, .mips64el => "mips",
1080 .powerpc, .powerpc64, .powerpc64le => "powerpc",1083 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1081 .amdgcn => "amdgpu",1084 .amdgcn => "amdgpu",
1082 .riscv32, .riscv64 => "riscv",1085 .riscv32, .riscv64 => "riscv",
1083 .sparc, .sparcv9, .sparcel => "sparc",1086 .sparc, .sparcv9, .sparcel => "sparc",
...@@ -1100,7 +1103,7 @@ pub const Target = struct {...@@ -1100,7 +1103,7 @@ pub const Target = struct {
1100 .hexagon => &hexagon.all_features,1103 .hexagon => &hexagon.all_features,
1101 .mips, .mipsel, .mips64, .mips64el => &mips.all_features,1104 .mips, .mipsel, .mips64, .mips64el => &mips.all_features,
1102 .msp430 => &msp430.all_features,1105 .msp430 => &msp430.all_features,
1103 .powerpc, .powerpc64, .powerpc64le => &powerpc.all_features,1106 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
1104 .amdgcn => &amdgpu.all_features,1107 .amdgcn => &amdgpu.all_features,
1105 .riscv32, .riscv64 => &riscv.all_features,1108 .riscv32, .riscv64 => &riscv.all_features,
1106 .sparc, .sparcv9, .sparcel => &sparc.all_features,1109 .sparc, .sparcv9, .sparcel => &sparc.all_features,
...@@ -1124,7 +1127,7 @@ pub const Target = struct {...@@ -1124,7 +1127,7 @@ pub const Target = struct {
1124 .hexagon => comptime allCpusFromDecls(hexagon.cpu),1127 .hexagon => comptime allCpusFromDecls(hexagon.cpu),
1125 .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),1128 .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
1126 .msp430 => comptime allCpusFromDecls(msp430.cpu),1129 .msp430 => comptime allCpusFromDecls(msp430.cpu),
1127 .powerpc, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),1130 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1128 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),1131 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
1129 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),1132 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1130 .sparc, .sparcv9, .sparcel => comptime allCpusFromDecls(sparc.cpu),1133 .sparc, .sparcv9, .sparcel => comptime allCpusFromDecls(sparc.cpu),
...@@ -1181,6 +1184,7 @@ pub const Target = struct {...@@ -1181,6 +1184,7 @@ pub const Target = struct {
1181 .mips64, .mips64el => &mips.cpu.mips64,1184 .mips64, .mips64el => &mips.cpu.mips64,
1182 .msp430 => &msp430.cpu.generic,1185 .msp430 => &msp430.cpu.generic,
1183 .powerpc => &powerpc.cpu.ppc32,1186 .powerpc => &powerpc.cpu.ppc32,
1187 .powerpcle => &powerpc.cpu.ppc32,
1184 .powerpc64 => &powerpc.cpu.ppc64,1188 .powerpc64 => &powerpc.cpu.ppc64,
1185 .powerpc64le => &powerpc.cpu.ppc64le,1189 .powerpc64le => &powerpc.cpu.ppc64le,
1186 .amdgcn => &amdgpu.cpu.generic,1190 .amdgcn => &amdgpu.cpu.generic,
...@@ -1496,7 +1500,7 @@ pub const Target = struct {...@@ -1496,7 +1500,7 @@ pub const Target = struct {
1496 return print(&result, "/lib{s}/{s}", .{ lib_suffix, loader });1500 return print(&result, "/lib{s}/{s}", .{ lib_suffix, loader });
1497 },1501 },
14981502
1499 .powerpc => return copy(&result, "/lib/ld.so.1"),1503 .powerpc, .powerpcle => return copy(&result, "/lib/ld.so.1"),
1500 .powerpc64, .powerpc64le => return copy(&result, "/lib64/ld64.so.2"),1504 .powerpc64, .powerpc64le => return copy(&result, "/lib64/ld64.so.2"),
1501 .s390x => return copy(&result, "/lib64/ld64.so.1"),1505 .s390x => return copy(&result, "/lib64/ld64.so.1"),
1502 .sparcv9 => return copy(&result, "/lib64/ld-linux.so.2"),1506 .sparcv9 => return copy(&result, "/lib64/ld-linux.so.2"),
src/codegen/llvm.zig+1
...@@ -34,6 +34,7 @@ pub fn targetTriple(allocator: *Allocator, target: std.Target) ![:0]u8 {...@@ -34,6 +34,7 @@ pub fn targetTriple(allocator: *Allocator, target: std.Target) ![:0]u8 {
34 .mips64el => "mips64el",34 .mips64el => "mips64el",
35 .msp430 => "msp430",35 .msp430 => "msp430",
36 .powerpc => "powerpc",36 .powerpc => "powerpc",
37 .powerpcle => "powerpcle",
37 .powerpc64 => "powerpc64",38 .powerpc64 => "powerpc64",
38 .powerpc64le => "powerpc64le",39 .powerpc64le => "powerpc64le",
39 .r600 => "r600",40 .r600 => "r600",
src/target.zig+1
...@@ -246,6 +246,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -246,6 +246,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
246 .mips64el => .mips64el,246 .mips64el => .mips64el,
247 .msp430 => .msp430,247 .msp430 => .msp430,
248 .powerpc => .ppc,248 .powerpc => .ppc,
249 .powerpcle => .ppcle,
249 .powerpc64 => .ppc64,250 .powerpc64 => .ppc64,
250 .powerpc64le => .ppc64le,251 .powerpc64le => .ppc64le,
251 .r600 => .r600,252 .r600 => .r600,