authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-08-13 17:42:11+02:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-09 19:17:13+02:00
log28cc3639476fae72bae3836e8776966386915142
tree4abac414a331012b87b2ac1de2bf0736e62b5e2b
parent9e070b653c89a9216f9dd9f78ed7c78c11460ac7
signaturelock-open Commit is signed but in an unrecognized format.

stage2 ARM: improve Mir representation of mov and cmp

3 files changed, 82 insertions(+), 61 deletions(-)

src/arch/arm/CodeGen.zig+32-49
...@@ -438,9 +438,8 @@ fn gen(self: *Self) !void {...@@ -438,9 +438,8 @@ fn gen(self: *Self) !void {
438 // mov fp, sp438 // mov fp, sp
439 _ = try self.addInst(.{439 _ = try self.addInst(.{
440 .tag = .mov,440 .tag = .mov,
441 .data = .{ .rr_op = .{441 .data = .{ .r_op_mov = .{
442 .rd = .fp,442 .rd = .fp,
443 .rn = .r0,
444 .op = Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none),443 .op = Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none),
445 } },444 } },
446 });445 });
...@@ -531,9 +530,8 @@ fn gen(self: *Self) !void {...@@ -531,9 +530,8 @@ fn gen(self: *Self) !void {
531 // mov sp, fp530 // mov sp, fp
532 _ = try self.addInst(.{531 _ = try self.addInst(.{
533 .tag = .mov,532 .tag = .mov,
534 .data = .{ .rr_op = .{533 .data = .{ .r_op_mov = .{
535 .rd = .sp,534 .rd = .sp,
536 .rn = .r0,
537 .op = Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none),535 .op = Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none),
538 } },536 } },
539 });537 });
...@@ -1240,9 +1238,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {...@@ -1240,9 +1238,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
12401238
1241 _ = try self.addInst(.{1239 _ = try self.addInst(.{
1242 .tag = .mvn,1240 .tag = .mvn,
1243 .data = .{ .rr_op = .{1241 .data = .{ .r_op_mov = .{
1244 .rd = dest_reg,1242 .rd = dest_reg,
1245 .rn = undefined,
1246 .op = Instruction.Operand.reg(op_reg, Instruction.Operand.Shift.none),1243 .op = Instruction.Operand.reg(op_reg, Instruction.Operand.Shift.none),
1247 } },1244 } },
1248 });1245 });
...@@ -1337,9 +1334,8 @@ fn minMax(...@@ -1337,9 +1334,8 @@ fn minMax(
1337 _ = try self.addInst(.{1334 _ = try self.addInst(.{
1338 .tag = .mov,1335 .tag = .mov,
1339 .cond = cond_choose_lhs,1336 .cond = cond_choose_lhs,
1340 .data = .{ .rr_op = .{1337 .data = .{ .r_op_mov = .{
1341 .rd = dest_reg,1338 .rd = dest_reg,
1342 .rn = .r0,
1343 .op = Instruction.Operand.reg(lhs_reg, Instruction.Operand.Shift.none),1339 .op = Instruction.Operand.reg(lhs_reg, Instruction.Operand.Shift.none),
1344 } },1340 } },
1345 });1341 });
...@@ -1348,9 +1344,8 @@ fn minMax(...@@ -1348,9 +1344,8 @@ fn minMax(
1348 _ = try self.addInst(.{1344 _ = try self.addInst(.{
1349 .tag = .mov,1345 .tag = .mov,
1350 .cond = cond_choose_rhs,1346 .cond = cond_choose_rhs,
1351 .data = .{ .rr_op = .{1347 .data = .{ .r_op_mov = .{
1352 .rd = dest_reg,1348 .rd = dest_reg,
1353 .rn = .r0,
1354 .op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),1349 .op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
1355 } },1350 } },
1356 });1351 });
...@@ -1682,9 +1677,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {...@@ -1682,9 +1677,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
1682 // mov rdlo, #01677 // mov rdlo, #0
1683 _ = try self.addInst(.{1678 _ = try self.addInst(.{
1684 .tag = .mov,1679 .tag = .mov,
1685 .data = .{ .rr_op = .{1680 .data = .{ .r_op_mov = .{
1686 .rd = rdlo,1681 .rd = rdlo,
1687 .rn = .r0,
1688 .op = Instruction.Operand.fromU32(0).?,1682 .op = Instruction.Operand.fromU32(0).?,
1689 } },1683 } },
1690 });1684 });
...@@ -1693,9 +1687,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {...@@ -1693,9 +1687,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
1693 _ = try self.addInst(.{1687 _ = try self.addInst(.{
1694 .tag = .mov,1688 .tag = .mov,
1695 .cond = .ne,1689 .cond = .ne,
1696 .data = .{ .rr_op = .{1690 .data = .{ .r_op_mov = .{
1697 .rd = rdlo,1691 .rd = rdlo,
1698 .rn = .r0,
1699 .op = Instruction.Operand.fromU32(1).?,1692 .op = Instruction.Operand.fromU32(1).?,
1700 } },1693 } },
1701 });1694 });
...@@ -1707,9 +1700,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {...@@ -1707,9 +1700,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
1707 _ = try self.addInst(.{1700 _ = try self.addInst(.{
1708 .tag = .mov,1701 .tag = .mov,
1709 .cond = .ne,1702 .cond = .ne,
1710 .data = .{ .rr_op = .{1703 .data = .{ .r_op_mov = .{
1711 .rd = rdlo,1704 .rd = rdlo,
1712 .rn = .r0,
1713 .op = Instruction.Operand.fromU32(1).?,1705 .op = Instruction.Operand.fromU32(1).?,
1714 } },1706 } },
1715 });1707 });
...@@ -2670,7 +2662,7 @@ fn binOpRegister(...@@ -2670,7 +2662,7 @@ fn binOpRegister(
2670 defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);2662 defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
26712663
2672 const dest_reg = switch (mir_tag) {2664 const dest_reg = switch (mir_tag) {
2673 .cmp => .r0, // cmp has no destination regardless2665 .cmp => undefined, // cmp has no destination regardless
2674 else => if (metadata) |md| blk: {2666 else => if (metadata) |md| blk: {
2675 if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {2667 if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
2676 break :blk lhs_reg;2668 break :blk lhs_reg;
...@@ -2690,7 +2682,6 @@ fn binOpRegister(...@@ -2690,7 +2682,6 @@ fn binOpRegister(
2690 .adds,2682 .adds,
2691 .sub,2683 .sub,
2692 .subs,2684 .subs,
2693 .cmp,
2694 .@"and",2685 .@"and",
2695 .orr,2686 .orr,
2696 .eor,2687 .eor,
...@@ -2699,6 +2690,10 @@ fn binOpRegister(...@@ -2699,6 +2690,10 @@ fn binOpRegister(
2699 .rn = lhs_reg,2690 .rn = lhs_reg,
2700 .op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),2691 .op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
2701 } },2692 } },
2693 .cmp => .{ .r_op_cmp = .{
2694 .rn = lhs_reg,
2695 .op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
2696 } },
2702 .lsl,2697 .lsl,
2703 .asr,2698 .asr,
2704 .lsr,2699 .lsr,
...@@ -2767,7 +2762,7 @@ fn binOpImmediate(...@@ -2767,7 +2762,7 @@ fn binOpImmediate(
2767 defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);2762 defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
27682763
2769 const dest_reg = switch (mir_tag) {2764 const dest_reg = switch (mir_tag) {
2770 .cmp => .r0, // cmp has no destination reg2765 .cmp => undefined, // cmp has no destination reg
2771 else => if (metadata) |md| blk: {2766 else => if (metadata) |md| blk: {
2772 if (lhs_is_register and self.reuseOperand(2767 if (lhs_is_register and self.reuseOperand(
2773 md.inst,2768 md.inst,
...@@ -2789,7 +2784,6 @@ fn binOpImmediate(...@@ -2789,7 +2784,6 @@ fn binOpImmediate(
2789 .adds,2784 .adds,
2790 .sub,2785 .sub,
2791 .subs,2786 .subs,
2792 .cmp,
2793 .@"and",2787 .@"and",
2794 .orr,2788 .orr,
2795 .eor,2789 .eor,
...@@ -2798,6 +2792,10 @@ fn binOpImmediate(...@@ -2798,6 +2792,10 @@ fn binOpImmediate(
2798 .rn = lhs_reg,2792 .rn = lhs_reg,
2799 .op = Instruction.Operand.fromU32(rhs.immediate).?,2793 .op = Instruction.Operand.fromU32(rhs.immediate).?,
2800 } },2794 } },
2795 .cmp => .{ .r_op_cmp = .{
2796 .rn = lhs_reg,
2797 .op = Instruction.Operand.fromU32(rhs.immediate).?,
2798 } },
2801 .lsl,2799 .lsl,
2802 .asr,2800 .asr,
2803 .lsr,2801 .lsr,
...@@ -3312,9 +3310,8 @@ fn genInlineMemcpy(...@@ -3312,9 +3310,8 @@ fn genInlineMemcpy(
3312 // mov count, #03310 // mov count, #0
3313 _ = try self.addInst(.{3311 _ = try self.addInst(.{
3314 .tag = .mov,3312 .tag = .mov,
3315 .data = .{ .rr_op = .{3313 .data = .{ .r_op_mov = .{
3316 .rd = count,3314 .rd = count,
3317 .rn = .r0,
3318 .op = Instruction.Operand.imm(0, 0),3315 .op = Instruction.Operand.imm(0, 0),
3319 } },3316 } },
3320 });3317 });
...@@ -3323,8 +3320,7 @@ fn genInlineMemcpy(...@@ -3323,8 +3320,7 @@ fn genInlineMemcpy(
3323 // cmp count, len3320 // cmp count, len
3324 _ = try self.addInst(.{3321 _ = try self.addInst(.{
3325 .tag = .cmp,3322 .tag = .cmp,
3326 .data = .{ .rr_op = .{3323 .data = .{ .r_op_cmp = .{
3327 .rd = .r0,
3328 .rn = count,3324 .rn = count,
3329 .op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),3325 .op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),
3330 } },3326 } },
...@@ -3418,9 +3414,8 @@ fn genInlineMemsetCode(...@@ -3418,9 +3414,8 @@ fn genInlineMemsetCode(
3418 // mov count, #03414 // mov count, #0
3419 _ = try self.addInst(.{3415 _ = try self.addInst(.{
3420 .tag = .mov,3416 .tag = .mov,
3421 .data = .{ .rr_op = .{3417 .data = .{ .r_op_mov = .{
3422 .rd = count,3418 .rd = count,
3423 .rn = .r0,
3424 .op = Instruction.Operand.imm(0, 0),3419 .op = Instruction.Operand.imm(0, 0),
3425 } },3420 } },
3426 });3421 });
...@@ -3429,8 +3424,7 @@ fn genInlineMemsetCode(...@@ -3429,8 +3424,7 @@ fn genInlineMemsetCode(
3429 // cmp count, len3424 // cmp count, len
3430 _ = try self.addInst(.{3425 _ = try self.addInst(.{
3431 .tag = .cmp,3426 .tag = .cmp,
3432 .data = .{ .rr_op = .{3427 .data = .{ .r_op_cmp = .{
3433 .rd = .r0,
3434 .rn = count,3428 .rn = count,
3435 .op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),3429 .op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),
3436 } },3430 } },
...@@ -4020,9 +4014,7 @@ fn condBr(self: *Self, condition: MCValue) !Mir.Inst.Index {...@@ -4020,9 +4014,7 @@ fn condBr(self: *Self, condition: MCValue) !Mir.Inst.Index {
4020 // bne ...4014 // bne ...
4021 _ = try self.addInst(.{4015 _ = try self.addInst(.{
4022 .tag = .cmp,4016 .tag = .cmp,
4023 .cond = .al,4017 .data = .{ .r_op_cmp = .{
4024 .data = .{ .rr_op = .{
4025 .rd = .r0,
4026 .rn = reg,4018 .rn = reg,
4027 .op = Instruction.Operand.imm(1, 0),4019 .op = Instruction.Operand.imm(1, 0),
4028 } },4020 } },
...@@ -4196,8 +4188,7 @@ fn isNull(self: *Self, ty: Type, operand: MCValue) !MCValue {...@@ -4196,8 +4188,7 @@ fn isNull(self: *Self, ty: Type, operand: MCValue) !MCValue {
41964188
4197 _ = try self.addInst(.{4189 _ = try self.addInst(.{
4198 .tag = .cmp,4190 .tag = .cmp,
4199 .data = .{ .rr_op = .{4191 .data = .{ .r_op_cmp = .{
4200 .rd = undefined,
4201 .rn = reg_mcv.register,4192 .rn = reg_mcv.register,
4202 .op = Instruction.Operand.fromU32(0).?,4193 .op = Instruction.Operand.fromU32(0).?,
4203 } },4194 } },
...@@ -4832,9 +4823,8 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -4832,9 +4823,8 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
4832 .register_v_flag => .vs,4823 .register_v_flag => .vs,
4833 else => unreachable,4824 else => unreachable,
4834 },4825 },
4835 .data = .{ .rr_op = .{4826 .data = .{ .r_op_mov = .{
4836 .rd = cond_reg,4827 .rd = cond_reg,
4837 .rn = .r0,
4838 .op = Instruction.Operand.fromU32(1).?,4828 .op = Instruction.Operand.fromU32(1).?,
4839 } },4829 } },
4840 });4830 });
...@@ -4935,9 +4925,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -4935,9 +4925,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
4935 // mov reg, 04925 // mov reg, 0
4936 _ = try self.addInst(.{4926 _ = try self.addInst(.{
4937 .tag = .mov,4927 .tag = .mov,
4938 .data = .{ .rr_op = .{4928 .data = .{ .r_op_mov = .{
4939 .rd = reg,4929 .rd = reg,
4940 .rn = .r0,
4941 .op = zero,4930 .op = zero,
4942 } },4931 } },
4943 });4932 });
...@@ -4946,9 +4935,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -4946,9 +4935,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
4946 _ = try self.addInst(.{4935 _ = try self.addInst(.{
4947 .tag = .mov,4936 .tag = .mov,
4948 .cond = condition,4937 .cond = condition,
4949 .data = .{ .rr_op = .{4938 .data = .{ .r_op_mov = .{
4950 .rd = reg,4939 .rd = reg,
4951 .rn = .r0,
4952 .op = one,4940 .op = one,
4953 } },4941 } },
4954 });4942 });
...@@ -4957,18 +4945,16 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -4957,18 +4945,16 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
4957 if (Instruction.Operand.fromU32(x)) |op| {4945 if (Instruction.Operand.fromU32(x)) |op| {
4958 _ = try self.addInst(.{4946 _ = try self.addInst(.{
4959 .tag = .mov,4947 .tag = .mov,
4960 .data = .{ .rr_op = .{4948 .data = .{ .r_op_mov = .{
4961 .rd = reg,4949 .rd = reg,
4962 .rn = .r0,
4963 .op = op,4950 .op = op,
4964 } },4951 } },
4965 });4952 });
4966 } else if (Instruction.Operand.fromU32(~x)) |op| {4953 } else if (Instruction.Operand.fromU32(~x)) |op| {
4967 _ = try self.addInst(.{4954 _ = try self.addInst(.{
4968 .tag = .mvn,4955 .tag = .mvn,
4969 .data = .{ .rr_op = .{4956 .data = .{ .r_op_mov = .{
4970 .rd = reg,4957 .rd = reg,
4971 .rn = .r0,
4972 .op = op,4958 .op = op,
4973 } },4959 } },
4974 });4960 });
...@@ -4984,9 +4970,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -4984,9 +4970,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
4984 } else {4970 } else {
4985 _ = try self.addInst(.{4971 _ = try self.addInst(.{
4986 .tag = .mov,4972 .tag = .mov,
4987 .data = .{ .rr_op = .{4973 .data = .{ .r_op_mov = .{
4988 .rd = reg,4974 .rd = reg,
4989 .rn = .r0,
4990 .op = Instruction.Operand.imm(@truncate(u8, x), 0),4975 .op = Instruction.Operand.imm(@truncate(u8, x), 0),
4991 } },4976 } },
4992 });4977 });
...@@ -5028,9 +5013,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5028,9 +5013,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5028 // orr reg, reg, #0xdd, 85013 // orr reg, reg, #0xdd, 8
5029 _ = try self.addInst(.{5014 _ = try self.addInst(.{
5030 .tag = .mov,5015 .tag = .mov,
5031 .data = .{ .rr_op = .{5016 .data = .{ .r_op_mov = .{
5032 .rd = reg,5017 .rd = reg,
5033 .rn = .r0,
5034 .op = Instruction.Operand.imm(@truncate(u8, x), 0),5018 .op = Instruction.Operand.imm(@truncate(u8, x), 0),
5035 } },5019 } },
5036 });5020 });
...@@ -5069,9 +5053,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5069,9 +5053,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5069 // mov reg, src_reg5053 // mov reg, src_reg
5070 _ = try self.addInst(.{5054 _ = try self.addInst(.{
5071 .tag = .mov,5055 .tag = .mov,
5072 .data = .{ .rr_op = .{5056 .data = .{ .r_op_mov = .{
5073 .rd = reg,5057 .rd = reg,
5074 .rn = .r0,
5075 .op = Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none),5058 .op = Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none),
5076 } },5059 } },
5077 });5060 });
src/arch/arm/Emit.zig+36-12
...@@ -385,20 +385,44 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {...@@ -385,20 +385,44 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
385fn mirDataProcessing(emit: *Emit, inst: Mir.Inst.Index) !void {385fn mirDataProcessing(emit: *Emit, inst: Mir.Inst.Index) !void {
386 const tag = emit.mir.instructions.items(.tag)[inst];386 const tag = emit.mir.instructions.items(.tag)[inst];
387 const cond = emit.mir.instructions.items(.cond)[inst];387 const cond = emit.mir.instructions.items(.cond)[inst];
388 const rr_op = emit.mir.instructions.items(.data)[inst].rr_op;
389388
390 switch (tag) {389 switch (tag) {
391 .add => try emit.writeInstruction(Instruction.add(cond, rr_op.rd, rr_op.rn, rr_op.op)),390 .add,
392 .adds => try emit.writeInstruction(Instruction.adds(cond, rr_op.rd, rr_op.rn, rr_op.op)),391 .adds,
393 .@"and" => try emit.writeInstruction(Instruction.@"and"(cond, rr_op.rd, rr_op.rn, rr_op.op)),392 .@"and",
394 .cmp => try emit.writeInstruction(Instruction.cmp(cond, rr_op.rn, rr_op.op)),393 .eor,
395 .eor => try emit.writeInstruction(Instruction.eor(cond, rr_op.rd, rr_op.rn, rr_op.op)),394 .orr,
396 .mov => try emit.writeInstruction(Instruction.mov(cond, rr_op.rd, rr_op.op)),395 .rsb,
397 .mvn => try emit.writeInstruction(Instruction.mvn(cond, rr_op.rd, rr_op.op)),396 .sub,
398 .orr => try emit.writeInstruction(Instruction.orr(cond, rr_op.rd, rr_op.rn, rr_op.op)),397 .subs,
399 .rsb => try emit.writeInstruction(Instruction.rsb(cond, rr_op.rd, rr_op.rn, rr_op.op)),398 => {
400 .sub => try emit.writeInstruction(Instruction.sub(cond, rr_op.rd, rr_op.rn, rr_op.op)),399 const rr_op = emit.mir.instructions.items(.data)[inst].rr_op;
401 .subs => try emit.writeInstruction(Instruction.subs(cond, rr_op.rd, rr_op.rn, rr_op.op)),400 switch (tag) {
401 .add => try emit.writeInstruction(Instruction.add(cond, rr_op.rd, rr_op.rn, rr_op.op)),
402 .adds => try emit.writeInstruction(Instruction.adds(cond, rr_op.rd, rr_op.rn, rr_op.op)),
403 .@"and" => try emit.writeInstruction(Instruction.@"and"(cond, rr_op.rd, rr_op.rn, rr_op.op)),
404 .eor => try emit.writeInstruction(Instruction.eor(cond, rr_op.rd, rr_op.rn, rr_op.op)),
405 .orr => try emit.writeInstruction(Instruction.orr(cond, rr_op.rd, rr_op.rn, rr_op.op)),
406 .rsb => try emit.writeInstruction(Instruction.rsb(cond, rr_op.rd, rr_op.rn, rr_op.op)),
407 .sub => try emit.writeInstruction(Instruction.sub(cond, rr_op.rd, rr_op.rn, rr_op.op)),
408 .subs => try emit.writeInstruction(Instruction.subs(cond, rr_op.rd, rr_op.rn, rr_op.op)),
409 else => unreachable,
410 }
411 },
412 .cmp => {
413 const r_op_cmp = emit.mir.instructions.items(.data)[inst].r_op_cmp;
414 try emit.writeInstruction(Instruction.cmp(cond, r_op_cmp.rn, r_op_cmp.op));
415 },
416 .mov,
417 .mvn,
418 => {
419 const r_op_mov = emit.mir.instructions.items(.data)[inst].r_op_mov;
420 switch (tag) {
421 .mov => try emit.writeInstruction(Instruction.mov(cond, r_op_mov.rd, r_op_mov.op)),
422 .mvn => try emit.writeInstruction(Instruction.mvn(cond, r_op_mov.rd, r_op_mov.op)),
423 else => unreachable,
424 }
425 },
402 else => unreachable,426 else => unreachable,
403 }427 }
404}428}
src/arch/arm/Mir.zig+14
...@@ -166,6 +166,20 @@ pub const Inst = struct {...@@ -166,6 +166,20 @@ pub const Inst = struct {
166 rd: Register,166 rd: Register,
167 imm16: u16,167 imm16: u16,
168 },168 },
169 /// A register and an operand
170 ///
171 /// Used by mov and mvn
172 r_op_mov: struct {
173 rd: Register,
174 op: bits.Instruction.Operand,
175 },
176 /// A register and an operand
177 ///
178 /// Used by cmp
179 r_op_cmp: struct {
180 rn: Register,
181 op: bits.Instruction.Operand,
182 },
169 /// Two registers and a shift amount183 /// Two registers and a shift amount
170 ///184 ///
171 /// Used by e.g. lsl185 /// Used by e.g. lsl