authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-06 11:10:02+02:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2025-10-06 11:10:02+02:00
log2962db333f43c8bb10a1e2ad4cdd19dfab26515b
tree1077791d5785d2276053fc3163b5fb6dde21f645
parentea9fb3ccfa1caef7f234a791da18fa33b9c292c7
parenta5ff376b8ff6caa857ec2e4da27e5debb716d920
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #25480 from alexrp/std-debug-hexagon

`std.debug`: add unwind support for `hexagon-linux`

4 files changed, 109 insertions(+), 2 deletions(-)

lib/std/debug/Dwarf.zig+3
......@@ -1431,6 +1431,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
14311431 return switch (arch) {
14321432 .aarch64, .aarch64_be => 32,
14331433 .arm, .armeb, .thumb, .thumbeb => 15,
1434 .hexagon => 76,
14341435 .loongarch32, .loongarch64 => 32,
14351436 .riscv32, .riscv32be, .riscv64, .riscv64be => 32,
14361437 .s390x => 65,
......@@ -1444,6 +1445,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
14441445 return switch (arch) {
14451446 .aarch64, .aarch64_be => 29,
14461447 .arm, .armeb, .thumb, .thumbeb => 11,
1448 .hexagon => 30,
14471449 .loongarch32, .loongarch64 => 22,
14481450 .riscv32, .riscv32be, .riscv64, .riscv64be => 8,
14491451 .s390x => 11,
......@@ -1457,6 +1459,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
14571459 return switch (arch) {
14581460 .aarch64, .aarch64_be => 31,
14591461 .arm, .armeb, .thumb, .thumbeb => 13,
1462 .hexagon => 29,
14601463 .loongarch32, .loongarch64 => 3,
14611464 .riscv32, .riscv32be, .riscv64, .riscv64be => 2,
14621465 .s390x => 15,
lib/std/debug/SelfInfo/Elf.zig+1
......@@ -97,6 +97,7 @@ pub const can_unwind: bool = s: {
9797 .linux => &.{
9898 .aarch64,
9999 .aarch64_be,
100 .hexagon,
100101 .loongarch64,
101102 .riscv32,
102103 .riscv64,
lib/std/debug/cpu_context.zig+76
......@@ -6,6 +6,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
66else switch (native_arch) {
77 .aarch64, .aarch64_be => Aarch64,
88 .arm, .armeb, .thumb, .thumbeb => Arm,
9 .hexagon => Hexagon,
910 .loongarch32, .loongarch64 => LoongArch,
1011 .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
1112 .s390x => S390x,
......@@ -181,6 +182,13 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
181182 },
182183 else => null,
183184 },
185 .hexagon => switch (builtin.os.tag) {
186 .linux => .{
187 .r = uc.mcontext.gregs,
188 .pc = uc.mcontext.pc,
189 },
190 else => null,
191 },
184192 .loongarch64 => switch (builtin.os.tag) {
185193 .linux => .{
186194 .r = uc.mcontext.regs, // includes r0 (hardwired zero)
......@@ -502,6 +510,74 @@ pub const Aarch64 = extern struct {
502510 }
503511};
504512
513/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
514pub const Hexagon = extern struct {
515 /// The numbered general-purpose registers r0 - r31.
516 r: [32]u32,
517 pc: u32,
518
519 pub inline fn current() Hexagon {
520 var ctx: Hexagon = undefined;
521 asm volatile (
522 \\ memw(r0 + #0) = r0
523 \\ memw(r0 + #4) = r1
524 \\ memw(r0 + #8) = r2
525 \\ memw(r0 + #12) = r3
526 \\ memw(r0 + #16) = r4
527 \\ memw(r0 + #20) = r5
528 \\ memw(r0 + #24) = r6
529 \\ memw(r0 + #28) = r7
530 \\ memw(r0 + #32) = r8
531 \\ memw(r0 + #36) = r9
532 \\ memw(r0 + #40) = r10
533 \\ memw(r0 + #44) = r11
534 \\ memw(r0 + #48) = r12
535 \\ memw(r0 + #52) = r13
536 \\ memw(r0 + #56) = r14
537 \\ memw(r0 + #60) = r15
538 \\ memw(r0 + #64) = r16
539 \\ memw(r0 + #68) = r17
540 \\ memw(r0 + #72) = r18
541 \\ memw(r0 + #76) = r19
542 \\ memw(r0 + #80) = r20
543 \\ memw(r0 + #84) = r21
544 \\ memw(r0 + #88) = r22
545 \\ memw(r0 + #92) = r23
546 \\ memw(r0 + #96) = r24
547 \\ memw(r0 + #100) = r25
548 \\ memw(r0 + #104) = r26
549 \\ memw(r0 + #108) = r27
550 \\ memw(r0 + #112) = r28
551 \\ memw(r0 + #116) = r29
552 \\ memw(r0 + #120) = r30
553 \\ memw(r0 + #124) = r31
554 \\ r1 = pc
555 \\ memw(r0 + #128) = r1
556 \\ r1 = memw(r0 + #4)
557 :
558 : [gprs] "{r0}" (&ctx),
559 : .{ .memory = true });
560 return ctx;
561 }
562
563 pub fn dwarfRegisterBytes(ctx: *Hexagon, register_num: u16) DwarfRegisterError![]u8 {
564 // Sourced from LLVM's HexagonRegisterInfo.td, which disagrees with LLDB...
565 switch (register_num) {
566 0...31 => return @ptrCast(&ctx.r[register_num]),
567 76 => return @ptrCast(&ctx.pc),
568
569 // This is probably covering some numbers that aren't actually mapped, but seriously,
570 // look at that file. I really can't be bothered to make it more precise.
571 32...75 => return error.UnsupportedRegister,
572 77...259 => return error.UnsupportedRegister,
573 // 999999...1000030 => return error.UnsupportedRegister,
574 // 9999999...10000030 => return error.UnsupportedRegister,
575
576 else => return error.InvalidRegister,
577 }
578 }
579};
580
505581/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
506582pub const LoongArch = extern struct {
507583 /// The numbered general-purpose registers r0 - r31. r0 must be zero.
lib/std/os/linux/hexagon.zig+29-2
......@@ -9,6 +9,8 @@ const gid_t = std.os.linux.gid_t;
99const pid_t = std.os.linux.pid_t;
1010const sockaddr = linux.sockaddr;
1111const socklen_t = linux.socklen_t;
12const stack_t = linux.stack_t;
13const sigset_t = linux.sigset_t;
1214const timespec = std.os.linux.timespec;
1315
1416pub fn syscall0(number: SYS) usize {
......@@ -235,5 +237,30 @@ pub const Elf_Symndx = u32;
235237
236238pub const VDSO = void;
237239
238/// TODO
239pub const ucontext_t = void;
240pub const mcontext_t = extern struct {
241 gregs: [32]u32 align(8),
242 sa0: u32,
243 lc0: u32,
244 sa1: u32,
245 lc1: u32,
246 m0: u32,
247 m1: u32,
248 usr: u32,
249 p3_0: u32,
250 gp: u32,
251 ugp: u32,
252 pc: u32,
253 cause: u32,
254 badva: u32,
255 cs0: u32,
256 cs1: u32,
257 _pad2: u32,
258};
259
260pub const ucontext_t = extern struct {
261 flags: usize,
262 link: ?*ucontext_t,
263 stack: stack_t,
264 mcontext: mcontext_t,
265 sigmask: [2]u32,
266};