authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-11-10 06:52:12+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-11-10 08:20:21+01:00
log2c470d24b3c3c939a0ec20292b5d28d92c16b431
treece332a6d8d2e529cb187faae5d848c7791fa8ba2
parent5358af7ba4cf16bef1734729646b99842e439916
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: add Arch tag and info for kvx

8 files changed, 139 insertions(+), 1 deletions(-)

lib/compiler/aro/aro/target.zig+4-1
...@@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
477 .ve,477 .ve,
478 .bpfel,478 .bpfel,
479 .bpfeb,479 .bpfeb,
480 .kvx,
480 .s390x,481 .s390x,
481 => return null,482 => return null,
482483
...@@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
551 .nvptx64,552 .nvptx64,
552 .wasm64,553 .wasm64,
553 .spirv64,554 .spirv64,
555 .kvx,
554 .loongarch64,556 .loongarch64,
555 .mips64,557 .mips64,
556 .mips64el,558 .mips64el,
...@@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
636 .wasm32 => "wasm32",638 .wasm32 => "wasm32",
637 .wasm64 => "wasm64",639 .wasm64 => "wasm64",
638 .ve => "ve",640 .ve => "ve",
639 // Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name641 // Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name
640 .kalimba => "kalimba",642 .kalimba => "kalimba",
643 .kvx => "kvx",
641 .propeller => "propeller",644 .propeller => "propeller",
642 .or1k => "or1k",645 .or1k => "or1k",
643 };646 };
lib/std/Target.zig+22
...@@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");...@@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");
710pub const hexagon = @import("Target/hexagon.zig");710pub const hexagon = @import("Target/hexagon.zig");
711pub const hppa = @import("Target/generic.zig");711pub const hppa = @import("Target/generic.zig");
712pub const kalimba = @import("Target/generic.zig");712pub const kalimba = @import("Target/generic.zig");
713pub const kvx = @import("Target/kvx.zig");
713pub const lanai = @import("Target/lanai.zig");714pub const lanai = @import("Target/lanai.zig");
714pub const loongarch = @import("Target/loongarch.zig");715pub const loongarch = @import("Target/loongarch.zig");
715pub const m68k = @import("Target/m68k.zig");716pub const m68k = @import("Target/m68k.zig");
...@@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {...@@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1043 .hexagon => .QDSP6,1044 .hexagon => .QDSP6,
1044 .hppa, .hppa64 => .PARISC,1045 .hppa, .hppa64 => .PARISC,
1045 .kalimba => .CSR_KALIMBA,1046 .kalimba => .CSR_KALIMBA,
1047 .kvx => .KVX,
1046 .lanai => .LANAI,1048 .lanai => .LANAI,
1047 .loongarch32, .loongarch64 => .LOONGARCH,1049 .loongarch32, .loongarch64 => .LOONGARCH,
1048 .m68k => .@"68K",1050 .m68k => .@"68K",
...@@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {...@@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1105 .hppa,1107 .hppa,
1106 .hppa64,1108 .hppa64,
1107 .kalimba,1109 .kalimba,
1110 .kvx,
1108 .lanai,1111 .lanai,
1109 .m68k,1112 .m68k,
1110 .microblaze,1113 .microblaze,
...@@ -1310,6 +1313,7 @@ pub const Cpu = struct {...@@ -1310,6 +1313,7 @@ pub const Cpu = struct {
1310 hppa,1313 hppa,
1311 hppa64,1314 hppa64,
1312 kalimba,1315 kalimba,
1316 kvx,
1313 lanai,1317 lanai,
1314 loongarch32,1318 loongarch32,
1315 loongarch64,1319 loongarch64,
...@@ -1385,6 +1389,7 @@ pub const Cpu = struct {...@@ -1385,6 +1389,7 @@ pub const Cpu = struct {
1385 hexagon,1389 hexagon,
1386 hppa,1390 hppa,
1387 kalimba,1391 kalimba,
1392 kvx,
1388 lanai,1393 lanai,
1389 loongarch,1394 loongarch,
1390 m68k,1395 m68k,
...@@ -1420,6 +1425,7 @@ pub const Cpu = struct {...@@ -1420,6 +1425,7 @@ pub const Cpu = struct {
1420 .hexagon => .hexagon,1425 .hexagon => .hexagon,
1421 .hppa, .hppa64 => .hppa,1426 .hppa, .hppa64 => .hppa,
1422 .kalimba => .kalimba,1427 .kalimba => .kalimba,
1428 .kvx => .kvx,
1423 .lanai => .lanai,1429 .lanai => .lanai,
1424 .loongarch32, .loongarch64 => .loongarch,1430 .loongarch32, .loongarch64 => .loongarch,
1425 .m68k => .m68k,1431 .m68k => .m68k,
...@@ -1623,6 +1629,7 @@ pub const Cpu = struct {...@@ -1623,6 +1629,7 @@ pub const Cpu = struct {
1623 .csky,1629 .csky,
1624 .hexagon,1630 .hexagon,
1625 .kalimba,1631 .kalimba,
1632 .kvx,
1626 .loongarch32,1633 .loongarch32,
1627 .loongarch64,1634 .loongarch64,
1628 .microblazeel,1635 .microblazeel,
...@@ -1847,6 +1854,10 @@ pub const Cpu = struct {...@@ -1847,6 +1854,10 @@ pub const Cpu = struct {
1847 .hppa64_elf,1854 .hppa64_elf,
1848 => &.{.hppa64},1855 => &.{.hppa64},
18491856
1857 .kvx_lp64,
1858 .kvx_ilp32,
1859 => &.{.kvx},
1860
1850 .lanai_sysv,1861 .lanai_sysv,
1851 => &.{.lanai},1862 => &.{.lanai},
18521863
...@@ -1936,6 +1947,7 @@ pub const Cpu = struct {...@@ -1936,6 +1947,7 @@ pub const Cpu = struct {
1936 return switch (arch) {1947 return switch (arch) {
1937 .amdgcn => &amdgcn.cpu.gfx600,1948 .amdgcn => &amdgcn.cpu.gfx600,
1938 .avr => &avr.cpu.avr1,1949 .avr => &avr.cpu.avr1,
1950 .kvx => &kvx.cpu.coolidge_v1,
1939 .loongarch32 => &loongarch.cpu.generic_la32,1951 .loongarch32 => &loongarch.cpu.generic_la32,
1940 .loongarch64 => &loongarch.cpu.generic_la64,1952 .loongarch64 => &loongarch.cpu.generic_la64,
1941 .mips, .mipsel => &mips.cpu.mips32,1953 .mips, .mipsel => &mips.cpu.mips32,
...@@ -1987,6 +1999,7 @@ pub const Cpu = struct {...@@ -1987,6 +1999,7 @@ pub const Cpu = struct {
1987 .bpfel, .bpfeb => &bpf.cpu.v3,1999 .bpfel, .bpfeb => &bpf.cpu.v3,
1988 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.2000 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
1989 .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.2001 .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
2002 .kvx => &kvx.cpu.coolidge_v2,
1990 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.2003 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
1991 .loongarch64 => &loongarch.cpu.la64v1_0,2004 .loongarch64 => &loongarch.cpu.la64v1_0,
1992 .m68k => &m68k.cpu.M68000,2005 .m68k => &m68k.cpu.M68000,
...@@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {...@@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {
2440 .aarch64,2453 .aarch64,
2441 .aarch64_be,2454 .aarch64_be,
2442 .hexagon,2455 .hexagon,
2456 .kvx,
2443 .m68k,2457 .m68k,
2444 .microblaze,2458 .microblaze,
2445 .microblazeel,2459 .microblazeel,
...@@ -2817,6 +2831,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {...@@ -2817,6 +2831,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2817 .bpfeb,2831 .bpfeb,
2818 .bpfel,2832 .bpfel,
2819 .hppa64,2833 .hppa64,
2834 .kvx,
2820 .loongarch64,2835 .loongarch64,
2821 .mips64,2836 .mips64,
2822 .mips64el,2837 .mips64el,
...@@ -3375,6 +3390,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {...@@ -3375,6 +3390,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3375 .aarch64_be,3390 .aarch64_be,
3376 .alpha,3391 .alpha,
3377 .hppa64,3392 .hppa64,
3393 .kvx,
3378 .loongarch32,3394 .loongarch32,
3379 .loongarch64,3395 .loongarch64,
3380 .mips64,3396 .mips64,
...@@ -3482,6 +3498,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {...@@ -3482,6 +3498,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3482 .aarch64_be,3498 .aarch64_be,
3483 .alpha,3499 .alpha,
3484 .hppa64,3500 .hppa64,
3501 .kvx,
3485 .loongarch32,3502 .loongarch32,
3486 .loongarch64,3503 .loongarch64,
3487 .mips64,3504 .mips64,
...@@ -3557,6 +3574,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {...@@ -3557,6 +3574,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3557 .bpfel,3574 .bpfel,
3558 .bpfeb,3575 .bpfeb,
3559 .hppa64,3576 .hppa64,
3577 .kvx,
3560 .loongarch64,3578 .loongarch64,
3561 .mips64,3579 .mips64,
3562 .mips64el,3580 .mips64el,
...@@ -3626,6 +3644,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention...@@ -3626,6 +3644,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3626 .hppa => .{ .hppa_elf = .{} },3644 .hppa => .{ .hppa_elf = .{} },
3627 .hppa64 => .{ .hppa64_elf = .{} },3645 .hppa64 => .{ .hppa64_elf = .{} },
3628 .kalimba => null,3646 .kalimba => null,
3647 .kvx => switch (target.abi) {
3648 .ilp32 => .{ .kvx_ilp32 = .{} },
3649 else => .{ .kvx_lp64 = .{} },
3650 },
3629 .lanai => .{ .lanai_sysv = .{} },3651 .lanai => .{ .lanai_sysv = .{} },
3630 .loongarch64 => .{ .loongarch64_lp64 = .{} },3652 .loongarch64 => .{ .loongarch64_lp64 = .{} },
3631 .loongarch32 => .{ .loongarch32_ilp32 = .{} },3653 .loongarch32 => .{ .loongarch32_ilp32 = .{} },
lib/std/Target/kvx.zig created+64
...@@ -0,0 +1,64 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 v3_1,
9 v3_2,
10 v4_1,
11};
12
13pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
14pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
15pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
16pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
17
18pub const all_features = blk: {
19 const len = @typeInfo(Feature).@"enum".fields.len;
20 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
21 var result: [len]CpuFeature = undefined;
22 result[@intFromEnum(Feature.v3_1)] = .{
23 .llvm_name = null,
24 .description = "Enable ISA v3.1",
25 .dependencies = featureSet(&[_]Feature{}),
26 };
27 result[@intFromEnum(Feature.v3_2)] = .{
28 .llvm_name = null,
29 .description = "Enable ISA v3.2",
30 .dependencies = featureSet(&[_]Feature{
31 .v3_1,
32 }),
33 };
34 result[@intFromEnum(Feature.v4_1)] = .{
35 .llvm_name = null,
36 .description = "Enable ISA v4.1",
37 .dependencies = featureSet(&[_]Feature{
38 .v3_2,
39 }),
40 };
41 const ti = @typeInfo(Feature);
42 for (&result, 0..) |*elem, i| {
43 elem.index = i;
44 elem.name = ti.@"enum".fields[i].name;
45 }
46 break :blk result;
47};
48
49pub const cpu = struct {
50 pub const coolidge_v1: CpuModel = .{
51 .name = "coolidge_v1",
52 .llvm_name = null,
53 .features = featureSet(&[_]Feature{
54 .v3_1,
55 }),
56 };
57 pub const coolidge_v2: CpuModel = .{
58 .name = "coolidge_v2",
59 .llvm_name = null,
60 .features = featureSet(&[_]Feature{
61 .v3_2,
62 }),
63 };
64};
lib/std/builtin.zig+4
...@@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {...@@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {
274 /// The standard `hppa64` calling convention.274 /// The standard `hppa64` calling convention.
275 hppa64_elf: CommonOptions,275 hppa64_elf: CommonOptions,
276276
277 kvx_lp64: CommonOptions,
278 kvx_ilp32: CommonOptions,
279
277 /// The standard `lanai` calling convention.280 /// The standard `lanai` calling convention.
278 lanai_sysv: CommonOptions,281 lanai_sysv: CommonOptions,
279282
...@@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {...@@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {
959 .csky,962 .csky,
960 .hppa,963 .hppa,
961 .hppa64,964 .hppa64,
965 .kvx,
962 .lanai,966 .lanai,
963 .loongarch32,967 .loongarch32,
964 .loongarch64,968 .loongarch64,
src/Sema.zig+2
...@@ -9074,6 +9074,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention...@@ -9074,6 +9074,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9074 .hexagon_sysv_hvx,9074 .hexagon_sysv_hvx,
9075 .hppa_elf,9075 .hppa_elf,
9076 .hppa64_elf,9076 .hppa64_elf,
9077 .kvx_lp64,
9078 .kvx_ilp32,
9077 .lanai_sysv,9079 .lanai_sysv,
9078 .loongarch64_lp64,9080 .loongarch64_lp64,
9079 .loongarch32_ilp32,9081 .loongarch32_ilp32,
src/codegen/llvm.zig+5
...@@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8...@@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
111 .hppa,111 .hppa,
112 .hppa64,112 .hppa64,
113 .kalimba,113 .kalimba,
114 .kvx,
114 .microblaze,115 .microblaze,
115 .microblazeel,116 .microblazeel,
116 .or1k,117 .or1k,
...@@ -476,6 +477,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {...@@ -476,6 +477,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
476 .hppa,477 .hppa,
477 .hppa64,478 .hppa64,
478 .kalimba,479 .kalimba,
480 .kvx,
479 .microblaze,481 .microblaze,
480 .microblazeel,482 .microblazeel,
481 .or1k,483 .or1k,
...@@ -11930,6 +11932,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s...@@ -11930,6 +11932,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11930 .hexagon_sysv_hvx,11932 .hexagon_sysv_hvx,
11931 .hppa_elf,11933 .hppa_elf,
11932 .hppa64_elf,11934 .hppa64_elf,
11935 .kvx_lp64,
11936 .kvx_ilp32,
11933 .lanai_sysv,11937 .lanai_sysv,
11934 .loongarch64_lp64,11938 .loongarch64_lp64,
11935 .loongarch32_ilp32,11939 .loongarch32_ilp32,
...@@ -13113,6 +13117,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -13113,6 +13117,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13113 .hppa,13117 .hppa,
13114 .hppa64,13118 .hppa64,
13115 .kalimba,13119 .kalimba,
13120 .kvx,
13116 .microblaze,13121 .microblaze,
13117 .microblazeel,13122 .microblazeel,
13118 .or1k,13123 .or1k,
src/target.zig+1
...@@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)...@@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
219 .hppa,219 .hppa,
220 .hppa64,220 .hppa64,
221 .kalimba,221 .kalimba,
222 .kvx,
222 .microblaze,223 .microblaze,
223 .microblazeel,224 .microblazeel,
224 .or1k,225 .or1k,
tools/update_cpu_features.zig+37
...@@ -973,6 +973,43 @@ const targets = [_]ArchTarget{...@@ -973,6 +973,43 @@ const targets = [_]ArchTarget{
973 .td_name = "Hexagon",973 .td_name = "Hexagon",
974 },974 },
975 },975 },
976 .{
977 .zig_name = "kvx",
978 .llvm = null,
979 .extra_features = &.{
980 .{
981 .zig_name = "v3_1",
982 .desc = "Enable ISA v3.1",
983 .deps = &.{},
984 },
985 .{
986 .zig_name = "v3_2",
987 .desc = "Enable ISA v3.2",
988 .deps = &.{"v3_1"},
989 },
990 .{
991 .zig_name = "v4_1",
992 .desc = "Enable ISA v4.1",
993 .deps = &.{"v3_2"},
994 },
995 },
996 .extra_cpus = &.{
997 .{
998 .llvm_name = null,
999 .zig_name = "coolidge_v1",
1000 .features = &.{
1001 "v3_1",
1002 },
1003 },
1004 .{
1005 .llvm_name = null,
1006 .zig_name = "coolidge_v2",
1007 .features = &.{
1008 "v3_2",
1009 },
1010 },
1011 },
1012 },
976 .{1013 .{
977 .zig_name = "lanai",1014 .zig_name = "lanai",
978 .llvm = .{1015 .llvm = .{