| ... | ... | @@ -899,6 +899,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 899 | 899 | .load => return self.genLoad(inst.castTag(.load).?), |
| 900 | 900 | .loop => return self.genLoop(inst.castTag(.loop).?), |
| 901 | 901 | .not => return self.genNot(inst.castTag(.not).?), |
| 902 | .mul => return self.genMul(inst.castTag(.mul).?), |
| 902 | 903 | .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?), |
| 903 | 904 | .ref => return self.genRef(inst.castTag(.ref).?), |
| 904 | 905 | .ret => return self.genRet(inst.castTag(.ret).?), |
| ... | ... | @@ -1128,6 +1129,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 1128 | 1129 | } |
| 1129 | 1130 | } |
| 1130 | 1131 | |
| 1132 | fn genMul(self: *Self, inst: *ir.Inst.BinOp) !MCValue { |
| 1133 | // No side effects, so if it's unreferenced, do nothing. |
| 1134 | if (inst.base.isUnused()) |
| 1135 | return MCValue.dead; |
| 1136 | switch (arch) { |
| 1137 | .arm, .armeb => return try self.genArmMul(&inst.base, inst.lhs, inst.rhs), |
| 1138 | else => return self.fail(inst.base.src, "TODO implement mul for {}", .{self.target.cpu.arch}), |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1131 | 1142 | fn genBitAnd(self: *Self, inst: *ir.Inst.BinOp) !MCValue { |
| 1132 | 1143 | // No side effects, so if it's unreferenced, do nothing. |
| 1133 | 1144 | if (inst.base.isUnused()) |
| ... | ... | @@ -1478,6 +1489,38 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 1478 | 1489 | } |
| 1479 | 1490 | } |
| 1480 | 1491 | |
| 1492 | fn genArmMul(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst) !MCValue { |
| 1493 | const lhs = try self.resolveInst(op_lhs); |
| 1494 | const rhs = try self.resolveInst(op_rhs); |
| 1495 | |
| 1496 | // Destination must be a register |
| 1497 | // LHS must be a register |
| 1498 | // RHS must be a register |
| 1499 | var dst_mcv: MCValue = undefined; |
| 1500 | var lhs_mcv: MCValue = undefined; |
| 1501 | var rhs_mcv: MCValue = undefined; |
| 1502 | if (self.reuseOperand(inst, 0, lhs)) { |
| 1503 | // LHS is the destination |
| 1504 | lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs; |
| 1505 | rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs; |
| 1506 | dst_mcv = lhs_mcv; |
| 1507 | } else if (self.reuseOperand(inst, 1, rhs)) { |
| 1508 | // RHS is the destination |
| 1509 | lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs; |
| 1510 | rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs; |
| 1511 | dst_mcv = rhs_mcv; |
| 1512 | } else { |
| 1513 | // TODO save 1 copy instruction by directly allocating the destination register |
| 1514 | // LHS is the destination |
| 1515 | lhs_mcv = try self.copyToNewRegister(inst, lhs); |
| 1516 | rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs; |
| 1517 | dst_mcv = lhs_mcv; |
| 1518 | } |
| 1519 | |
| 1520 | writeInt(u32, try self.code.addManyAsArray(4), Instruction.mul(.al, dst_mcv.register, lhs_mcv.register, rhs_mcv.register).toU32()); |
| 1521 | return dst_mcv; |
| 1522 | } |
| 1523 | |
| 1481 | 1524 | /// ADD, SUB, XOR, OR, AND |
| 1482 | 1525 | fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue { |
| 1483 | 1526 | try self.code.ensureCapacity(self.code.items.len + 8); |
Joachim Schmidt <joachim.schmidt557@outlook.com> 2021-03-01 22:43:42+01:00