authorgravatar for miguel.p.paradinha@gmail.commparadinha <miguel.p.paradinha@gmail.com> 2022-03-18 19:38:06+00:00
committergravatar for miguel.p.paradinha@gmail.commparadinha <miguel.p.paradinha@gmail.com> 2022-03-21 19:32:46+00:00
log35eaaed7c4fa5ca16c3a593e2bb479163e4c56d8
tree89ec0349fcc0382b6d93ce1eff19f19facf839e6
parent6d7808e647e6d244e53a18139c22bce8cd38a3ca

stage2: x86_64: use correct register size when loading things from memory

1 files changed, 3 insertions(+), 2 deletions(-)

src/arch/x86_64/CodeGen.zig+3-2
......@@ -953,7 +953,8 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
953953/// This can have a side effect of spilling instructions to the stack to free up a register.
954954fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
955955 const reg = try self.register_manager.allocReg(null);
956 try self.genSetReg(ty, reg, mcv);
956 const sized_reg = registerAlias(reg, @intCast(u32, ty.abiSize(self.target.*)));
957 try self.genSetReg(ty, sized_reg, mcv);
957958 return reg;
958959}
959960
......@@ -5337,7 +5338,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
53375338 _ = try self.addInst(.{
53385339 .tag = .mov,
53395340 .ops = (Mir.Ops{
5340 .reg1 = reg.to64(),
5341 .reg1 = reg,
53415342 .reg2 = reg.to64(),
53425343 .flags = 0b01,
53435344 }).encode(),