| ... | @@ -3740,22 +3740,9 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void | ... | @@ -3740,22 +3740,9 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void |
| 3740 | .data = .{ .payload = payload }, | 3740 | .data = .{ .payload = payload }, |
| 3741 | }); | 3741 | }); |
| 3742 | } else { | 3742 | } else { |
| 3743 | // This requires two instructions; a move imm as used above, followed by an indirect load using the register | | |
| 3744 | // as the address and the register as the destination. | | |
| 3745 | // | | |
| 3746 | // This cannot be used if the lower three bits of the id are equal to four or five, as there | | |
| 3747 | // is no way to possibly encode it. This means that RSP, RBP, R12, and R13 cannot be used with | | |
| 3748 | // this instruction. | | |
| 3749 | const id3 = @truncate(u3, reg.id()); | | |
| 3750 | assert(id3 != 4 and id3 != 5); | | |
| 3751 | | | |
| 3752 | // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue. | 3743 | // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue. |
| 3753 | try self.genSetReg(ty, reg, MCValue{ .immediate = x }); | 3744 | try self.genSetReg(ty, reg, MCValue{ .immediate = x }); |
| 3754 | | 3745 | |
| 3755 | // Now, the register contains the address of the value to load into it | | |
| 3756 | // Currently, we're only allowing 64-bit registers, so we need the `REX.W 8B /r` variant. | | |
| 3757 | // TODO: determine whether to allow other sized registers, and if so, handle them properly. | | |
| 3758 | | | |
| 3759 | // mov reg, [reg + 0x0] | 3746 | // mov reg, [reg + 0x0] |
| 3760 | _ = try self.addInst(.{ | 3747 | _ = try self.addInst(.{ |
| 3761 | .tag = .mov, | 3748 | .tag = .mov, |
Jakub Konka <kubkon@jakubkonka.com> 2022-01-23 00:31:37+01:00
src