| ... | ... | @@ -23,6 +23,16 @@ const FeatureOverride = struct { |
| 23 | 23 | extra_deps: []const []const u8 = &.{}, |
| 24 | 24 | }; |
| 25 | 25 | |
| 26 | const CpuOverride = struct { |
| 27 | llvm_name: []const u8, |
| 28 | /// If true, completely omit the CPU; as if it does not exist. |
| 29 | omit: bool = false, |
| 30 | zig_name: ?[]const u8 = null, |
| 31 | desc: ?[]const u8 = null, |
| 32 | omit_deps: []const []const u8 = &.{}, |
| 33 | extra_deps: []const []const u8 = &.{}, |
| 34 | }; |
| 35 | |
| 26 | 36 | const Cpu = struct { |
| 27 | 37 | llvm_name: ?[]const u8, |
| 28 | 38 | zig_name: []const u8, |
| ... | ... | @@ -44,9 +54,9 @@ const ArchTarget = struct { |
| 44 | 54 | td_name: []const u8, |
| 45 | 55 | }, |
| 46 | 56 | feature_overrides: []const FeatureOverride = &.{}, |
| 47 | | extra_cpus: []const Cpu = &.{}, |
| 48 | 57 | extra_features: []const Feature = &.{}, |
| 49 | | omit_cpus: []const []const u8 = &.{}, |
| 58 | cpu_overrides: []const CpuOverride = &.{}, |
| 59 | extra_cpus: []const Cpu = &.{}, |
| 50 | 60 | branch_quota: ?usize = null, |
| 51 | 61 | }; |
| 52 | 62 | |
| ... | ... | @@ -432,6 +442,14 @@ const targets = [_]ArchTarget{ |
| 432 | 442 | .flatten = true, |
| 433 | 443 | }, |
| 434 | 444 | }, |
| 445 | .cpu_overrides = &.{ |
| 446 | .{ |
| 447 | // Who thought this alias was a good idea? Upgrade your compiler and suddenly your |
| 448 | // programs SIGILL because this changed meaning. Brilliant. |
| 449 | .llvm_name = "apple-latest", |
| 450 | .omit = true, |
| 451 | }, |
| 452 | }, |
| 435 | 453 | .extra_cpus = &.{ |
| 436 | 454 | .{ |
| 437 | 455 | .llvm_name = null, |
| ... | ... | @@ -485,11 +503,6 @@ const targets = [_]ArchTarget{ |
| 485 | 503 | }, |
| 486 | 504 | }, |
| 487 | 505 | }, |
| 488 | | .omit_cpus = &.{ |
| 489 | | // Who thought this alias was a good idea? Upgrade your compiler and suddenly your |
| 490 | | // programs SIGILL because this changed meaning. Brilliant. |
| 491 | | "apple-latest", |
| 492 | | }, |
| 493 | 506 | }, |
| 494 | 507 | .{ |
| 495 | 508 | .zig_name = "alpha", |
| ... | ... | @@ -754,63 +767,6 @@ const targets = [_]ArchTarget{ |
| 754 | 767 | .flatten = true, |
| 755 | 768 | }, |
| 756 | 769 | |
| 757 | | .{ |
| 758 | | .llvm_name = "cortex-m4", |
| 759 | | .omit_deps = &.{"vfp4d16sp"}, |
| 760 | | }, |
| 761 | | .{ |
| 762 | | .llvm_name = "cortex-m7", |
| 763 | | .omit_deps = &.{"fp_armv8d16"}, |
| 764 | | }, |
| 765 | | .{ |
| 766 | | .llvm_name = "cortex-m33", |
| 767 | | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 768 | | }, |
| 769 | | .{ |
| 770 | | .llvm_name = "cortex-m35p", |
| 771 | | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 772 | | }, |
| 773 | | .{ |
| 774 | | .llvm_name = "cortex-m52", |
| 775 | | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 776 | | }, |
| 777 | | .{ |
| 778 | | .llvm_name = "cortex-m55", |
| 779 | | .omit_deps = &.{ "fp_armv8d16", "mve_fp" }, |
| 780 | | }, |
| 781 | | .{ |
| 782 | | .llvm_name = "cortex-m85", |
| 783 | | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 784 | | }, |
| 785 | | .{ |
| 786 | | .llvm_name = "cortex-r5", |
| 787 | | .omit_deps = &.{"vfp3d16"}, |
| 788 | | }, |
| 789 | | .{ |
| 790 | | .llvm_name = "cortex-r7", |
| 791 | | .omit_deps = &.{ "fp16", "vfp3d16" }, |
| 792 | | }, |
| 793 | | .{ |
| 794 | | .llvm_name = "cortex-r8", |
| 795 | | .omit_deps = &.{ "fp16", "vfp3d16" }, |
| 796 | | }, |
| 797 | | .{ |
| 798 | | .llvm_name = "cortex-r52", |
| 799 | | .omit_deps = &.{ "fp_armv8", "neon" }, |
| 800 | | }, |
| 801 | | .{ |
| 802 | | .llvm_name = "cortex-r52plus", |
| 803 | | .omit_deps = &.{ "fp_armv8", "neon" }, |
| 804 | | }, |
| 805 | | .{ |
| 806 | | .llvm_name = "star-mc1", |
| 807 | | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 808 | | }, |
| 809 | | .{ |
| 810 | | .llvm_name = "star-mc3", |
| 811 | | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 812 | | }, |
| 813 | | |
| 814 | 770 | .{ |
| 815 | 771 | .llvm_name = "armv2", |
| 816 | 772 | .zig_name = "v2", |
| ... | ... | @@ -1121,23 +1077,6 @@ const targets = [_]ArchTarget{ |
| 1121 | 1077 | .zig_name = "has_v9_7a", |
| 1122 | 1078 | }, |
| 1123 | 1079 | }, |
| 1124 | | .extra_cpus = &.{ |
| 1125 | | .{ |
| 1126 | | .llvm_name = "generic", |
| 1127 | | .zig_name = "baseline", |
| 1128 | | .features = &.{"v7a"}, |
| 1129 | | }, |
| 1130 | | .{ |
| 1131 | | .llvm_name = null, |
| 1132 | | .zig_name = "exynos_m1", |
| 1133 | | .features = &.{ "v8a", "exynos" }, |
| 1134 | | }, |
| 1135 | | .{ |
| 1136 | | .llvm_name = null, |
| 1137 | | .zig_name = "exynos_m2", |
| 1138 | | .features = &.{ "v8a", "exynos" }, |
| 1139 | | }, |
| 1140 | | }, |
| 1141 | 1080 | .extra_features = &.{ |
| 1142 | 1081 | // LLVM removed support for v2 and v3 but zig wants to support targeting old hardware |
| 1143 | 1082 | .{ |
| ... | ... | @@ -1161,6 +1100,81 @@ const targets = [_]ArchTarget{ |
| 1161 | 1100 | .deps = &.{"strict_align"}, |
| 1162 | 1101 | }, |
| 1163 | 1102 | }, |
| 1103 | .cpu_overrides = &.{ |
| 1104 | .{ |
| 1105 | .llvm_name = "cortex-m4", |
| 1106 | .omit_deps = &.{"vfp4d16sp"}, |
| 1107 | }, |
| 1108 | .{ |
| 1109 | .llvm_name = "cortex-m7", |
| 1110 | .omit_deps = &.{"fp_armv8d16"}, |
| 1111 | }, |
| 1112 | .{ |
| 1113 | .llvm_name = "cortex-m33", |
| 1114 | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 1115 | }, |
| 1116 | .{ |
| 1117 | .llvm_name = "cortex-m35p", |
| 1118 | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 1119 | }, |
| 1120 | .{ |
| 1121 | .llvm_name = "cortex-m52", |
| 1122 | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 1123 | }, |
| 1124 | .{ |
| 1125 | .llvm_name = "cortex-m55", |
| 1126 | .omit_deps = &.{ "fp_armv8d16", "mve_fp" }, |
| 1127 | }, |
| 1128 | .{ |
| 1129 | .llvm_name = "cortex-m85", |
| 1130 | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 1131 | }, |
| 1132 | .{ |
| 1133 | .llvm_name = "cortex-r5", |
| 1134 | .omit_deps = &.{"vfp3d16"}, |
| 1135 | }, |
| 1136 | .{ |
| 1137 | .llvm_name = "cortex-r7", |
| 1138 | .omit_deps = &.{ "fp16", "vfp3d16" }, |
| 1139 | }, |
| 1140 | .{ |
| 1141 | .llvm_name = "cortex-r8", |
| 1142 | .omit_deps = &.{ "fp16", "vfp3d16" }, |
| 1143 | }, |
| 1144 | .{ |
| 1145 | .llvm_name = "cortex-r52", |
| 1146 | .omit_deps = &.{ "fp_armv8", "neon" }, |
| 1147 | }, |
| 1148 | .{ |
| 1149 | .llvm_name = "cortex-r52plus", |
| 1150 | .omit_deps = &.{ "fp_armv8", "neon" }, |
| 1151 | }, |
| 1152 | .{ |
| 1153 | .llvm_name = "star-mc1", |
| 1154 | .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, |
| 1155 | }, |
| 1156 | .{ |
| 1157 | .llvm_name = "star-mc3", |
| 1158 | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 1159 | }, |
| 1160 | }, |
| 1161 | .extra_cpus = &.{ |
| 1162 | .{ |
| 1163 | .llvm_name = "generic", |
| 1164 | .zig_name = "baseline", |
| 1165 | .features = &.{"v7a"}, |
| 1166 | }, |
| 1167 | .{ |
| 1168 | .llvm_name = null, |
| 1169 | .zig_name = "exynos_m1", |
| 1170 | .features = &.{ "v8a", "exynos" }, |
| 1171 | }, |
| 1172 | .{ |
| 1173 | .llvm_name = null, |
| 1174 | .zig_name = "exynos_m2", |
| 1175 | .features = &.{ "v8a", "exynos" }, |
| 1176 | }, |
| 1177 | }, |
| 1164 | 1178 | }, |
| 1165 | 1179 | .{ |
| 1166 | 1180 | .zig_name = "avr", |
| ... | ... | @@ -1470,6 +1484,24 @@ const targets = [_]ArchTarget{ |
| 1470 | 1484 | .name = "LoongArch", |
| 1471 | 1485 | .td_name = "LoongArch", |
| 1472 | 1486 | }, |
| 1487 | .cpu_overrides = &.{ |
| 1488 | .{ |
| 1489 | .llvm_name = "generic", |
| 1490 | .omit = true, |
| 1491 | }, |
| 1492 | .{ |
| 1493 | .llvm_name = "generic-la64", |
| 1494 | .omit = true, |
| 1495 | }, |
| 1496 | .{ |
| 1497 | .llvm_name = "loongarch32", |
| 1498 | .omit = true, |
| 1499 | }, |
| 1500 | .{ |
| 1501 | .llvm_name = "loongarch64", |
| 1502 | .omit = true, |
| 1503 | }, |
| 1504 | }, |
| 1473 | 1505 | .extra_cpus = &.{ |
| 1474 | 1506 | .{ |
| 1475 | 1507 | .llvm_name = null, |
| ... | ... | @@ -1521,12 +1553,6 @@ const targets = [_]ArchTarget{ |
| 1521 | 1553 | }, |
| 1522 | 1554 | }, |
| 1523 | 1555 | }, |
| 1524 | | .omit_cpus = &.{ |
| 1525 | | "generic", |
| 1526 | | "generic-la64", |
| 1527 | | "loongarch32", |
| 1528 | | "loongarch64", |
| 1529 | | }, |
| 1530 | 1556 | }, |
| 1531 | 1557 | .{ |
| 1532 | 1558 | .zig_name = "m68k", |
| ... | ... | @@ -1607,6 +1633,12 @@ const targets = [_]ArchTarget{ |
| 1607 | 1633 | .omit = true, |
| 1608 | 1634 | }, |
| 1609 | 1635 | }, |
| 1636 | .cpu_overrides = &.{ |
| 1637 | .{ |
| 1638 | .llvm_name = "ppc32", |
| 1639 | .omit = true, |
| 1640 | }, |
| 1641 | }, |
| 1610 | 1642 | .extra_cpus = &.{ |
| 1611 | 1643 | .{ |
| 1612 | 1644 | .llvm_name = null, |
| ... | ... | @@ -1643,9 +1675,6 @@ const targets = [_]ArchTarget{ |
| 1643 | 1675 | }, |
| 1644 | 1676 | }, |
| 1645 | 1677 | }, |
| 1646 | | .omit_cpus = &.{ |
| 1647 | | "ppc32", |
| 1648 | | }, |
| 1649 | 1678 | }, |
| 1650 | 1679 | .{ |
| 1651 | 1680 | .zig_name = "propeller", |
| ... | ... | @@ -1744,6 +1773,12 @@ const targets = [_]ArchTarget{ |
| 1744 | 1773 | .deps = &.{}, |
| 1745 | 1774 | }, |
| 1746 | 1775 | }, |
| 1776 | .cpu_overrides = &.{ |
| 1777 | .{ |
| 1778 | .llvm_name = "generic", |
| 1779 | .omit = true, |
| 1780 | }, |
| 1781 | }, |
| 1747 | 1782 | .extra_cpus = &.{ |
| 1748 | 1783 | .{ |
| 1749 | 1784 | .llvm_name = null, |
| ... | ... | @@ -1761,9 +1796,6 @@ const targets = [_]ArchTarget{ |
| 1761 | 1796 | .features = &.{ "ve3", "vpu" }, |
| 1762 | 1797 | }, |
| 1763 | 1798 | }, |
| 1764 | | .omit_cpus = &.{ |
| 1765 | | "generic", |
| 1766 | | }, |
| 1767 | 1799 | }, |
| 1768 | 1800 | .{ |
| 1769 | 1801 | .zig_name = "wasm", |
| ... | ... | @@ -1798,6 +1830,16 @@ const targets = [_]ArchTarget{ |
| 1798 | 1830 | .deps = &.{"bulk_memory_opt"}, |
| 1799 | 1831 | }, |
| 1800 | 1832 | }, |
| 1833 | .cpu_overrides = &.{ |
| 1834 | .{ |
| 1835 | .llvm_name = "bleeding-edge", |
| 1836 | .omit = true, |
| 1837 | }, |
| 1838 | .{ |
| 1839 | .llvm_name = "generic", |
| 1840 | .omit = true, |
| 1841 | }, |
| 1842 | }, |
| 1801 | 1843 | .extra_cpus = &.{ |
| 1802 | 1844 | .{ |
| 1803 | 1845 | .llvm_name = null, |
| ... | ... | @@ -1836,10 +1878,6 @@ const targets = [_]ArchTarget{ |
| 1836 | 1878 | }, |
| 1837 | 1879 | }, |
| 1838 | 1880 | }, |
| 1839 | | .omit_cpus = &.{ |
| 1840 | | "bleeding-edge", |
| 1841 | | "generic", |
| 1842 | | }, |
| 1843 | 1881 | }, |
| 1844 | 1882 | .{ |
| 1845 | 1883 | .zig_name = "x86", |
| ... | ... | @@ -1865,20 +1903,58 @@ const targets = [_]ArchTarget{ |
| 1865 | 1903 | .omit = true, |
| 1866 | 1904 | }, |
| 1867 | 1905 | .{ |
| 1868 | | .llvm_name = "alderlake", |
| 1869 | | .extra_deps = &.{ "smap", "smep" }, |
| 1906 | .llvm_name = "sse4.2", |
| 1907 | .extra_deps = &.{"crc32"}, |
| 1870 | 1908 | }, |
| 1909 | }, |
| 1910 | .extra_features = &.{ |
| 1911 | // Features removed from LLVM |
| 1871 | 1912 | .{ |
| 1872 | | .llvm_name = "amdfam10", |
| 1873 | | .extra_deps = &.{"3dnowa"}, |
| 1913 | .zig_name = "3dnow", |
| 1914 | .desc = "Enable 3DNow! instructions", |
| 1915 | .deps = &.{"mmx"}, |
| 1874 | 1916 | }, |
| 1875 | 1917 | .{ |
| 1876 | | .llvm_name = "arrowlake", |
| 1877 | | .extra_deps = &.{ "smap", "smep" }, |
| 1918 | .zig_name = "3dnowa", |
| 1919 | .desc = "Enable 3DNow! Athlon instructions", |
| 1920 | .deps = &.{"3dnow"}, |
| 1878 | 1921 | }, |
| 1879 | 1922 | .{ |
| 1880 | | .llvm_name = "arrowlake-s", |
| 1881 | | .extra_deps = &.{ "smap", "smep" }, |
| 1923 | .zig_name = "avx512er", |
| 1924 | .desc = "Enable AVX-512 Exponential and Reciprocal Instructions", |
| 1925 | .deps = &.{"avx512f"}, |
| 1926 | }, |
| 1927 | .{ |
| 1928 | .zig_name = "avx512pf", |
| 1929 | .desc = "Enable AVX-512 PreFetch Instructions", |
| 1930 | .deps = &.{"avx512f"}, |
| 1931 | }, |
| 1932 | .{ |
| 1933 | .zig_name = "prefetchwt1", |
| 1934 | .desc = "Prefetch with Intent to Write and T1 Hint", |
| 1935 | .deps = &.{}, |
| 1936 | }, |
| 1937 | // Custom Zig features |
| 1938 | .{ |
| 1939 | .zig_name = "bsf_bsr_0_clobbers_result", |
| 1940 | .desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero", |
| 1941 | .deps = &.{}, |
| 1942 | }, |
| 1943 | .{ |
| 1944 | .zig_name = "smap", |
| 1945 | .desc = "Enable Supervisor Mode Access Prevention", |
| 1946 | .deps = &.{}, |
| 1947 | }, |
| 1948 | .{ |
| 1949 | .zig_name = "smep", |
| 1950 | .desc = "Enable Supervisor Mode Execution Prevention", |
| 1951 | .deps = &.{}, |
| 1952 | }, |
| 1953 | }, |
| 1954 | .cpu_overrides = &.{ |
| 1955 | .{ |
| 1956 | .llvm_name = "amdfam10", |
| 1957 | .extra_deps = &.{"3dnowa"}, |
| 1882 | 1958 | }, |
| 1883 | 1959 | .{ |
| 1884 | 1960 | .llvm_name = "athlon", |
| ... | ... | @@ -2057,8 +2133,16 @@ const targets = [_]ArchTarget{ |
| 2057 | 2133 | .extra_deps = &.{"3dnow"}, |
| 2058 | 2134 | }, |
| 2059 | 2135 | .{ |
| 2060 | | .llvm_name = "sse4.2", |
| 2061 | | .extra_deps = &.{"crc32"}, |
| 2136 | .llvm_name = "alderlake", |
| 2137 | .extra_deps = &.{ "smap", "smep" }, |
| 2138 | }, |
| 2139 | .{ |
| 2140 | .llvm_name = "arrowlake", |
| 2141 | .extra_deps = &.{ "smap", "smep" }, |
| 2142 | }, |
| 2143 | .{ |
| 2144 | .llvm_name = "arrowlake-s", |
| 2145 | .extra_deps = &.{ "smap", "smep" }, |
| 2062 | 2146 | }, |
| 2063 | 2147 | .{ |
| 2064 | 2148 | .llvm_name = "znver1", |
| ... | ... | @@ -2080,49 +2164,131 @@ const targets = [_]ArchTarget{ |
| 2080 | 2164 | .llvm_name = "znver5", |
| 2081 | 2165 | .extra_deps = &.{ "smap", "smep" }, |
| 2082 | 2166 | }, |
| 2083 | | }, |
| 2084 | | .extra_features = &.{ |
| 2085 | | // Features removed from LLVM |
| 2167 | |
| 2168 | // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. |
| 2086 | 2169 | .{ |
| 2087 | | .zig_name = "3dnow", |
| 2088 | | .desc = "Enable 3DNow! instructions", |
| 2089 | | .deps = &.{"mmx"}, |
| 2170 | .llvm_name = "pentium_mmx", |
| 2171 | .omit = true, |
| 2090 | 2172 | }, |
| 2091 | 2173 | .{ |
| 2092 | | .zig_name = "3dnowa", |
| 2093 | | .desc = "Enable 3DNow! Athlon instructions", |
| 2094 | | .deps = &.{"3dnow"}, |
| 2174 | .llvm_name = "pentium_pro", |
| 2175 | .omit = true, |
| 2095 | 2176 | }, |
| 2096 | 2177 | .{ |
| 2097 | | .zig_name = "avx512er", |
| 2098 | | .desc = "Enable AVX-512 Exponential and Reciprocal Instructions", |
| 2099 | | .deps = &.{"avx512f"}, |
| 2178 | .llvm_name = "pentium_ii", |
| 2179 | .omit = true, |
| 2100 | 2180 | }, |
| 2101 | 2181 | .{ |
| 2102 | | .zig_name = "avx512pf", |
| 2103 | | .desc = "Enable AVX-512 PreFetch Instructions", |
| 2104 | | .deps = &.{"avx512f"}, |
| 2182 | .llvm_name = "pentium_3m", |
| 2183 | .omit = true, |
| 2105 | 2184 | }, |
| 2106 | 2185 | .{ |
| 2107 | | .zig_name = "prefetchwt1", |
| 2108 | | .desc = "Prefetch with Intent to Write and T1 Hint", |
| 2109 | | .deps = &.{}, |
| 2186 | .llvm_name = "pentium_iii", |
| 2187 | .omit = true, |
| 2110 | 2188 | }, |
| 2111 | | // Custom Zig features |
| 2112 | 2189 | .{ |
| 2113 | | .zig_name = "bsf_bsr_0_clobbers_result", |
| 2114 | | .desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero", |
| 2115 | | .deps = &.{}, |
| 2190 | .llvm_name = "pentium_iii_no_xmm_regs", |
| 2191 | .omit = true, |
| 2116 | 2192 | }, |
| 2117 | 2193 | .{ |
| 2118 | | .zig_name = "smap", |
| 2119 | | .desc = "Enable Supervisor Mode Access Prevention", |
| 2120 | | .deps = &.{}, |
| 2194 | .llvm_name = "pentium_m", |
| 2195 | .omit = true, |
| 2121 | 2196 | }, |
| 2122 | 2197 | .{ |
| 2123 | | .zig_name = "smep", |
| 2124 | | .desc = "Enable Supervisor Mode Execution Prevention", |
| 2125 | | .deps = &.{}, |
| 2198 | .llvm_name = "pentium4m", |
| 2199 | .omit = true, |
| 2200 | }, |
| 2201 | .{ |
| 2202 | .llvm_name = "pentium_4", |
| 2203 | .omit = true, |
| 2204 | }, |
| 2205 | .{ |
| 2206 | .llvm_name = "pentium_4_sse3", |
| 2207 | .omit = true, |
| 2208 | }, |
| 2209 | .{ |
| 2210 | .llvm_name = "core_2_duo_ssse3", |
| 2211 | .omit = true, |
| 2212 | }, |
| 2213 | .{ |
| 2214 | .llvm_name = "core_2_duo_sse4_1", |
| 2215 | .omit = true, |
| 2216 | }, |
| 2217 | .{ |
| 2218 | .llvm_name = "atom_sse4_2", |
| 2219 | .omit = true, |
| 2220 | }, |
| 2221 | .{ |
| 2222 | .llvm_name = "goldmont-plus", |
| 2223 | .omit = true, |
| 2224 | }, |
| 2225 | .{ |
| 2226 | .llvm_name = "core_i7_sse4_2", |
| 2227 | .omit = true, |
| 2228 | }, |
| 2229 | .{ |
| 2230 | .llvm_name = "core_aes_pclmulqdq", |
| 2231 | .omit = true, |
| 2232 | }, |
| 2233 | .{ |
| 2234 | .llvm_name = "corei7-avx", |
| 2235 | .omit = true, |
| 2236 | }, |
| 2237 | .{ |
| 2238 | .llvm_name = "core_2nd_gen_avx", |
| 2239 | .omit = true, |
| 2240 | }, |
| 2241 | .{ |
| 2242 | .llvm_name = "core-avx-i", |
| 2243 | .omit = true, |
| 2244 | }, |
| 2245 | .{ |
| 2246 | .llvm_name = "core_3rd_gen_avx", |
| 2247 | .omit = true, |
| 2248 | }, |
| 2249 | .{ |
| 2250 | .llvm_name = "core-avx2", |
| 2251 | .omit = true, |
| 2252 | }, |
| 2253 | .{ |
| 2254 | .llvm_name = "core_4th_gen_avx", |
| 2255 | .omit = true, |
| 2256 | }, |
| 2257 | .{ |
| 2258 | .llvm_name = "core_4th_gen_avx_tsx", |
| 2259 | .omit = true, |
| 2260 | }, |
| 2261 | .{ |
| 2262 | .llvm_name = "core_5th_gen_avx", |
| 2263 | .omit = true, |
| 2264 | }, |
| 2265 | .{ |
| 2266 | .llvm_name = "core_5th_gen_avx_tsx", |
| 2267 | .omit = true, |
| 2268 | }, |
| 2269 | .{ |
| 2270 | .llvm_name = "mic_avx512", |
| 2271 | .omit = true, |
| 2272 | }, |
| 2273 | .{ |
| 2274 | .llvm_name = "skylake-avx512", |
| 2275 | .omit = true, |
| 2276 | }, |
| 2277 | .{ |
| 2278 | .llvm_name = "icelake-client", |
| 2279 | .omit = true, |
| 2280 | }, |
| 2281 | .{ |
| 2282 | .llvm_name = "icelake-server", |
| 2283 | .omit = true, |
| 2284 | }, |
| 2285 | .{ |
| 2286 | .llvm_name = "graniterapids_d", |
| 2287 | .omit = true, |
| 2288 | }, |
| 2289 | .{ |
| 2290 | .llvm_name = "arrowlake_s", |
| 2291 | .omit = true, |
| 2126 | 2292 | }, |
| 2127 | 2293 | }, |
| 2128 | 2294 | .extra_cpus = &.{ |
| ... | ... | @@ -2132,40 +2298,6 @@ const targets = [_]ArchTarget{ |
| 2132 | 2298 | .features = &.{"16bit_mode"}, |
| 2133 | 2299 | }, |
| 2134 | 2300 | }, |
| 2135 | | .omit_cpus = &.{ |
| 2136 | | // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. |
| 2137 | | "pentium_mmx", |
| 2138 | | "pentium_pro", |
| 2139 | | "pentium_ii", |
| 2140 | | "pentium_3m", |
| 2141 | | "pentium_iii_no_xmm_regs", |
| 2142 | | "pentium_iii", |
| 2143 | | "pentium_m", |
| 2144 | | "pentium4m", |
| 2145 | | "pentium_4", |
| 2146 | | "pentium_4_sse3", |
| 2147 | | "core_2_duo_ssse3", |
| 2148 | | "core_2_duo_sse4_1", |
| 2149 | | "atom_sse4_2", |
| 2150 | | "goldmont_plus", |
| 2151 | | "core_i7_sse4_2", |
| 2152 | | "core_aes_pclmulqdq", |
| 2153 | | "corei7-avx", |
| 2154 | | "core_2nd_gen_avx", |
| 2155 | | "core-avx-i", |
| 2156 | | "core_3rd_gen_avx", |
| 2157 | | "core-avx2", |
| 2158 | | "core_4th_gen_avx", |
| 2159 | | "core_4th_gen_avx_tsx", |
| 2160 | | "core_5th_gen_avx", |
| 2161 | | "core_5th_gen_avx_tsx", |
| 2162 | | "mic_avx512", |
| 2163 | | "skylake_avx512", |
| 2164 | | "icelake_client", |
| 2165 | | "icelake_server", |
| 2166 | | "graniterapids_d", |
| 2167 | | "arrowlake_s", |
| 2168 | | }, |
| 2169 | 2301 | }, |
| 2170 | 2302 | .{ |
| 2171 | 2303 | .zig_name = "xcore", |
| ... | ... | @@ -2195,6 +2327,16 @@ const targets = [_]ArchTarget{ |
| 2195 | 2327 | .deps = &.{"xs3"}, |
| 2196 | 2328 | }, |
| 2197 | 2329 | }, |
| 2330 | .cpu_overrides = &.{ |
| 2331 | .{ |
| 2332 | .llvm_name = "generic", |
| 2333 | .omit = true, |
| 2334 | }, |
| 2335 | .{ |
| 2336 | .llvm_name = "xs1b-generic", |
| 2337 | .omit = true, |
| 2338 | }, |
| 2339 | }, |
| 2198 | 2340 | .extra_cpus = &.{ |
| 2199 | 2341 | .{ |
| 2200 | 2342 | .llvm_name = null, |
| ... | ... | @@ -2212,10 +2354,6 @@ const targets = [_]ArchTarget{ |
| 2212 | 2354 | .features = &.{ "fpu", "vpu" }, |
| 2213 | 2355 | }, |
| 2214 | 2356 | }, |
| 2215 | | .omit_cpus = &.{ |
| 2216 | | "generic", |
| 2217 | | "xs1b-generic", |
| 2218 | | }, |
| 2219 | 2357 | }, |
| 2220 | 2358 | .{ |
| 2221 | 2359 | .zig_name = "xtensa", |
| ... | ... | @@ -2491,28 +2629,25 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2491 | 2629 | if (hasSuperclass(&kv.value_ptr.object, "Processor")) { |
| 2492 | 2630 | const llvm_name = kv.value_ptr.object.get("Name").?.string; |
| 2493 | 2631 | if (llvm_name.len == 0) continue; |
| 2494 | | const omitted = for (target.omit_cpus) |omit_cpu_name| { |
| 2495 | | if (mem.eql(u8, omit_cpu_name, llvm_name)) break true; |
| 2496 | | } else false; |
| 2497 | | if (omitted) continue; |
| 2498 | 2632 | |
| 2499 | 2633 | var zig_name = try llvmNameToZigName(arena, llvm_name); |
| 2500 | 2634 | var deps = std.array_list.Managed([]const u8).init(arena); |
| 2501 | 2635 | var omit_deps: []const []const u8 = &.{}; |
| 2502 | 2636 | var extra_deps: []const []const u8 = &.{}; |
| 2503 | | for (target.feature_overrides) |feature_override| { |
| 2504 | | if (mem.eql(u8, llvm_name, feature_override.llvm_name)) { |
| 2505 | | if (feature_override.omit) { |
| 2506 | | continue; |
| 2637 | const omitted = for (target.cpu_overrides) |cpu_override| { |
| 2638 | if (mem.eql(u8, llvm_name, cpu_override.llvm_name)) { |
| 2639 | if (cpu_override.omit) { |
| 2640 | break true; |
| 2507 | 2641 | } |
| 2508 | | if (feature_override.zig_name) |override_name| { |
| 2642 | if (cpu_override.zig_name) |override_name| { |
| 2509 | 2643 | zig_name = override_name; |
| 2510 | 2644 | } |
| 2511 | | omit_deps = feature_override.omit_deps; |
| 2512 | | extra_deps = feature_override.extra_deps; |
| 2513 | | break; |
| 2645 | omit_deps = cpu_override.omit_deps; |
| 2646 | extra_deps = cpu_override.extra_deps; |
| 2647 | break false; |
| 2514 | 2648 | } |
| 2515 | | } |
| 2649 | } else false; |
| 2650 | if (omitted) continue; |
| 2516 | 2651 | const features = kv.value_ptr.object.get("Features").?.array; |
| 2517 | 2652 | for (features.items) |feature| { |
| 2518 | 2653 | const feature_key = feature.object.get("def").?.string; |
| ... | ... | @@ -2554,8 +2689,8 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2554 | 2689 | |
| 2555 | 2690 | if (cpu_aliases.get(zig_name)) |aliases| { |
| 2556 | 2691 | alias_it: for (aliases.items) |alias| { |
| 2557 | | for (target.omit_cpus) |omit_cpu_name| { |
| 2558 | | if (mem.eql(u8, omit_cpu_name, alias.llvm)) continue :alias_it; |
| 2692 | for (target.cpu_overrides) |cpu_override| { |
| 2693 | if (mem.eql(u8, alias.llvm, cpu_override.llvm_name) and cpu_override.omit) continue :alias_it; |
| 2559 | 2694 | } |
| 2560 | 2695 | |
| 2561 | 2696 | try all_cpus.append(.{ |
Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 04:26:44+02:00