| author |  Jakub Konka <kubkon@jakubkonka.com> 2022-09-01 16:35:09+02:00 |
| committer | Jakub Konka <kubkon@jakubkonka.com> 2022-09-07 22:42:56+02:00 |
| log | 38573fed0ba796f642e7b4eebdf3f9eafc572f25 |
| tree | dea2afd6f3f70ca36213c4572308e650ad13d066 |
| parent | 49b1716064cb87b5e8ca13dcb1c9e4fc701737bc |
coff: fix runtime traps
3 files changed, 8 insertions(+), 3 deletions(-)
src- arch
- x86_64
- link
src/arch/x86_64/CodeGen.zig+6-1
| ... | @@ -4204,6 +4204,7 @@ fn airRet(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4204,6 +4204,7 @@ fn airRet(self: *Self, inst: Air.Inst.Index) !void { |
| 4204 | }, | 4204 | }, |
| 4205 | .stack_offset => { | 4205 | .stack_offset => { |
| 4206 | const reg = try self.copyToTmpRegister(Type.usize, self.ret_mcv); | 4206 | const reg = try self.copyToTmpRegister(Type.usize, self.ret_mcv); |
| 4207 | log.warn("REG = {}", .{reg}); | ||
| 4207 | const reg_lock = self.register_manager.lockRegAssumeUnused(reg); | 4208 | const reg_lock = self.register_manager.lockRegAssumeUnused(reg); |
| 4208 | defer self.register_manager.unlockReg(reg_lock); | 4209 | defer self.register_manager.unlockReg(reg_lock); |
| 4209 | 4210 | ||
| ... | @@ -5854,7 +5855,11 @@ fn genInlineMemcpy( | ... | @@ -5854,7 +5855,11 @@ fn genInlineMemcpy( |
| 5854 | len: MCValue, | 5855 | len: MCValue, |
| 5855 | opts: InlineMemcpyOpts, | 5856 | opts: InlineMemcpyOpts, |
| 5856 | ) InnerError!void { | 5857 | ) InnerError!void { |
| 5857 | // TODO preserve contents of .rax and .rcx if not free, and then restore | 5858 | // TODO: Preserve contents of .rax and .rcx if not free and locked, and then restore |
| 5859 | // How can we do this without context if the value inside .rax or .rcx we preserve contains | ||
| 5860 | // value needed to perform the memcpy in the first place? | ||
| 5861 | // I think we should have an accumulator-based context that we pass with each subsequent helper | ||
| 5862 | // call until we resolve the entire instruction. | ||
| 5858 | try self.register_manager.getReg(.rax, null); | 5863 | try self.register_manager.getReg(.rax, null); |
| 5859 | try self.register_manager.getReg(.rcx, null); | 5864 | try self.register_manager.getReg(.rcx, null); |
| 5860 | 5865 |
src/arch/x86_64/abi.zig+1-1
| ... | @@ -447,7 +447,7 @@ pub fn getCAbiIntReturnRegs(target: Target) []const Register { | ... | @@ -447,7 +447,7 @@ pub fn getCAbiIntReturnRegs(target: Target) []const Register { |
| 447 | } | 447 | } |
| 448 | 448 | ||
| 449 | const gp_regs = [_]Register{ | 449 | const gp_regs = [_]Register{ |
| 450 | .rax, .rbx, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11, .r12, .r13, .r14, .r15, | 450 | .rbx, .r12, .r13, .r14, .r15, .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11, |
| 451 | }; | 451 | }; |
| 452 | const sse_avx_regs = [_]Register{ | 452 | const sse_avx_regs = [_]Register{ |
| 453 | .ymm0, .ymm1, .ymm2, .ymm3, .ymm4, .ymm5, .ymm6, .ymm7, | 453 | .ymm0, .ymm1, .ymm2, .ymm3, .ymm4, .ymm5, .ymm6, .ymm7, |
src/link/Coff.zig+1-1
| ... | @@ -1053,7 +1053,7 @@ pub fn updateDecl(self: *Coff, module: *Module, decl_index: Module.Decl.Index) ! | ... | @@ -1053,7 +1053,7 @@ pub fn updateDecl(self: *Coff, module: *Module, decl_index: Module.Decl.Index) ! |
| 1053 | .ty = decl.ty, | 1053 | .ty = decl.ty, |
| 1054 | .val = decl_val, | 1054 | .val = decl_val, |
| 1055 | }, &code_buffer, .none, .{ | 1055 | }, &code_buffer, .none, .{ |
| 1056 | .parent_atom_index = 0, | 1056 | .parent_atom_index = decl.link.coff.sym_index, |
| 1057 | }); | 1057 | }); |
| 1058 | const code = switch (res) { | 1058 | const code = switch (res) { |
| 1059 | .externally_managed => |x| x, | 1059 | .externally_managed => |x| x, |