authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-07-23 20:04:26-07:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-07-23 20:04:26-07:00
log399f4fe7d69723eb94db7e13d2e8ffdc0ce4345b
tree69334f0de7a410fbc2445489bbf9825f3ce13ee5
parent7aaebd17746dc97111585563c64e166e27b334af
parent2d4fc1bb7a0c8b7ac42ace3e2bc05cc72c0efba9
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #20719 from alexrp/misc-porting

`std.os.linux`: A handful of random porting fixes, mostly for `armeb` and `thumbeb`

2 files changed, 94 insertions(+), 15 deletions(-)

lib/std/os/linux.zig+72-9
......@@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) {
3838 .x86 => @import("linux/x86.zig"),
3939 .x86_64 => @import("linux/x86_64.zig"),
4040 .aarch64, .aarch64_be => @import("linux/arm64.zig"),
41 .arm, .thumb => @import("linux/arm-eabi.zig"),
41 .arm, .armeb, .thumb, .thumbeb => @import("linux/arm-eabi.zig"),
4242 .riscv64 => @import("linux/riscv64.zig"),
4343 .sparc64 => @import("linux/sparc64.zig"),
4444 .mips, .mipsel => @import("linux/mips.zig"),
......@@ -103,7 +103,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) {
103103 .x86 => syscalls.X86,
104104 .x86_64 => syscalls.X64,
105105 .aarch64, .aarch64_be => syscalls.Arm64,
106 .arm, .thumb => syscalls.Arm,
106 .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
107107 .riscv64 => syscalls.RiscV64,
108108 .sparc64 => syscalls.Sparc64,
109109 .mips, .mipsel => syscalls.Mips,
......@@ -142,7 +142,7 @@ pub const MAP = switch (native_arch) {
142142 UNINITIALIZED: bool = false,
143143 _: u5 = 0,
144144 },
145 .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
145 .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
146146 TYPE: MAP_TYPE,
147147 FIXED: bool = false,
148148 ANONYMOUS: bool = false,
......@@ -290,7 +290,7 @@ pub const O = switch (native_arch) {
290290 TMPFILE: bool = false,
291291 _: u9 = 0,
292292 },
293 .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
293 .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
294294 ACCMODE: ACCMODE = .RDONLY,
295295 _2: u4 = 0,
296296 CREAT: bool = false,
......@@ -4787,13 +4787,72 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
47874787}
47884788
47894789pub const MINSIGSTKSZ = switch (native_arch) {
4790 .x86, .x86_64, .arm, .mipsel => 2048,
4791 .aarch64 => 5120,
4790 .arc,
4791 .arm,
4792 .armeb,
4793 .csky,
4794 .hexagon,
4795 .m68k,
4796 .mips,
4797 .mipsel,
4798 .mips64,
4799 .mips64el,
4800 .powerpc,
4801 .powerpcle,
4802 .riscv32,
4803 .riscv64,
4804 .s390x,
4805 .thumb,
4806 .thumbeb,
4807 .x86,
4808 .x86_64,
4809 .xtensa,
4810 => 2048,
4811 .loongarch64,
4812 .sparc,
4813 .sparcel,
4814 .sparc64,
4815 => 4096,
4816 .aarch64,
4817 .aarch64_be,
4818 => 5120,
4819 .powerpc64,
4820 .powerpc64le,
4821 => 8192,
47924822 else => @compileError("MINSIGSTKSZ not defined for this architecture"),
47934823};
47944824pub const SIGSTKSZ = switch (native_arch) {
4795 .x86, .x86_64, .arm, .mipsel => 8192,
4796 .aarch64 => 16384,
4825 .arc,
4826 .arm,
4827 .armeb,
4828 .csky,
4829 .hexagon,
4830 .m68k,
4831 .mips,
4832 .mipsel,
4833 .mips64,
4834 .mips64el,
4835 .powerpc,
4836 .powerpcle,
4837 .riscv32,
4838 .riscv64,
4839 .s390x,
4840 .thumb,
4841 .thumbeb,
4842 .x86,
4843 .x86_64,
4844 .xtensa,
4845 => 8192,
4846 .aarch64,
4847 .aarch64_be,
4848 .loongarch64,
4849 .sparc,
4850 .sparcel,
4851 .sparc64,
4852 => 16384,
4853 .powerpc64,
4854 .powerpc64le,
4855 => 32768,
47974856 else => @compileError("SIGSTKSZ not defined for this architecture"),
47984857};
47994858
......@@ -7294,7 +7353,7 @@ pub const AUDIT = struct {
72947353 ARMEB = toAudit(.armeb),
72957354 CSKY = toAudit(.csky),
72967355 HEXAGON = @intFromEnum(std.elf.EM.HEXAGON),
7297 X86 = toAudit(.x86),
7356 LOONGARCH64 = toAudit(.loongarch64),
72987357 M68K = toAudit(.m68k),
72997358 MIPS = toAudit(.mips),
73007359 MIPSEL = toAudit(.mips) | LE,
......@@ -7308,18 +7367,22 @@ pub const AUDIT = struct {
73087367 S390X = toAudit(.s390x),
73097368 SPARC = toAudit(.sparc),
73107369 SPARC64 = toAudit(.sparc64),
7370 X86 = toAudit(.x86),
73117371 X86_64 = toAudit(.x86_64),
7372 XTENSA = toAudit(.xtensa),
73127373
73137374 fn toAudit(arch: std.Target.Cpu.Arch) u32 {
73147375 var res: u32 = @intFromEnum(arch.toElfMachine());
73157376 if (arch.endian() == .little) res |= LE;
73167377 switch (arch) {
73177378 .aarch64,
7379 .loongarch64,
73187380 .mips64,
73197381 .mips64el,
73207382 .powerpc64,
73217383 .powerpc64le,
73227384 .riscv64,
7385 .s390x,
73237386 .sparc64,
73247387 .x86_64,
73257388 => res |= @"64BIT",
lib/std/os/linux/tls.zig+22-6
......@@ -49,7 +49,23 @@ const TLSVariant = enum {
4949};
5050
5151const tls_variant = switch (native_arch) {
52 .arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => TLSVariant.VariantI,
52 .arm,
53 .armeb,
54 .thumb,
55 .thumbeb,
56 .aarch64,
57 .aarch64_be,
58 .riscv32,
59 .riscv64,
60 .mips,
61 .mipsel,
62 .mips64,
63 .mips64el,
64 .powerpc,
65 .powerpcle,
66 .powerpc64,
67 .powerpc64le,
68 => TLSVariant.VariantI,
5369 .x86_64, .x86, .sparc64 => TLSVariant.VariantII,
5470 else => @compileError("undefined tls_variant for this architecture"),
5571};
......@@ -58,14 +74,14 @@ const tls_variant = switch (native_arch) {
5874const tls_tcb_size = switch (native_arch) {
5975 // ARM EABI mandates enough space for two pointers: the first one points to
6076 // the DTV while the second one is unspecified but reserved
61 .arm, .armeb, .thumb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
77 .arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
6278 // One pointer-sized word that points either to the DTV or the TCB itself
6379 else => @sizeOf(usize),
6480};
6581
6682// Controls if the TP points to the end of the TCB instead of its beginning
6783const tls_tp_points_past_tcb = switch (native_arch) {
68 .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => true,
84 .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => true,
6985 else => false,
7086};
7187
......@@ -73,12 +89,12 @@ const tls_tp_points_past_tcb = switch (native_arch) {
7389// make the generated code more efficient
7490
7591const tls_tp_offset = switch (native_arch) {
76 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x7000,
92 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x7000,
7793 else => 0,
7894};
7995
8096const tls_dtv_offset = switch (native_arch) {
81 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x8000,
97 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x8000,
8298 .riscv32, .riscv64 => 0x800,
8399 else => 0,
84100};
......@@ -150,7 +166,7 @@ pub fn setThreadPointer(addr: usize) void {
150166 : [addr] "r" (addr),
151167 );
152168 },
153 .arm, .thumb => {
169 .arm, .armeb, .thumb, .thumbeb => {
154170 const rc = @call(.always_inline, linux.syscall1, .{ .set_tls, addr });
155171 assert(rc == 0);
156172 },