| author | |
| committer | |
| log | 3bf9a8feb50c3ff20da80593a735ec3244cb5d89 |
| tree | ee53ac71cb9fbed67b0daa5487030d430b8dd842 |
| parent | 9fc9235ac815f8b0ad88445216407a0a9f747d5f |
2 files changed, 18 insertions(+), 1 deletions(-)
src/arch/x86_64/CodeGen.zig+17| ... | ... | @@ -7177,6 +7177,23 @@ fn genBinOp( |
| 7177 | 7177 | dst_reg, |
| 7178 | 7178 | tmp_reg, |
| 7179 | 7179 | ); |
| 7180 | switch (air_tag) { | |
| 7181 | .div_trunc, .div_floor => try self.asmRegisterRegisterRegisterImmediate( | |
| 7182 | .{ .v_ss, .round }, | |
| 7183 | dst_reg, | |
| 7184 | dst_reg, | |
| 7185 | dst_reg, | |
| 7186 | Immediate.u(@as(u5, @bitCast(RoundMode{ | |
| 7187 | .mode = switch (air_tag) { | |
| 7188 | .div_trunc => .zero, | |
| 7189 | .div_floor => .down, | |
| 7190 | else => unreachable, | |
| 7191 | }, | |
| 7192 | .precision = .inexact, | |
| 7193 | }))), | |
| 7194 | ), | |
| 7195 | else => {}, | |
| 7196 | } | |
| 7180 | 7197 | try self.asmRegisterRegisterImmediate( |
| 7181 | 7198 | .{ .v_, .cvtps2ph }, |
| 7182 | 7199 | dst_reg, |
test/behavior/math.zig+1-1| ... | ... | @@ -495,11 +495,11 @@ fn testDivision() !void { |
| 495 | 495 | } |
| 496 | 496 | |
| 497 | 497 | test "division half-precision floats" { |
| 498 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO | |
| 499 | 498 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO |
| 500 | 499 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO |
| 501 | 500 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO |
| 502 | 501 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
| 502 | if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest; | |
| 503 | 503 | |
| 504 | 504 | try testDivisionFP16(); |
| 505 | 505 | try comptime testDivisionFP16(); |