authorgravatar for jacoblevgw@gmail.comJacob G-W <jacoblevgw@gmail.com> 2021-01-08 17:08:45-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-01-18 19:29:18-07:00
log3c2a9220edd59c2d7b50aca65e4cd0748cf2306f
treed5a15a892c9d0befc08bdeca0778718a2f1bcce4
parent6c7e66613d57aec2f2949c065ea6431ff6c31f88

stage2: fix orelse at comptime

There was just some untested code that did not work. .isnull -> .isnonnull and I had to add a .ref resultloc to make types match up.

2 files changed, 49 insertions(+), 2 deletions(-)

src/astgen.zig+2-2
......@@ -1127,7 +1127,7 @@ fn catchExpr(mod: *Module, scope: *Scope, rl: ResultLoc, node: *ast.Node.Catch)
11271127}
11281128
11291129fn orelseExpr(mod: *Module, scope: *Scope, rl: ResultLoc, node: *ast.Node.SimpleInfixOp) InnerError!*zir.Inst {
1130 return orelseCatchExpr(mod, scope, rl, node.lhs, node.op_token, .isnull, .unwrap_optional_unsafe, node.rhs, null);
1130 return orelseCatchExpr(mod, scope, rl, node.lhs, node.op_token, .isnonnull, .unwrap_optional_unsafe, node.rhs, null);
11311131}
11321132
11331133fn orelseCatchExpr(
......@@ -1205,7 +1205,7 @@ fn orelseCatchExpr(
12051205
12061206 _ = try addZIRInst(mod, &then_scope.base, src, zir.Inst.Break, .{
12071207 .block = block,
1208 .operand = try expr(mod, then_sub_scope, branch_rl, rhs),
1208 .operand = try rlWrap(mod, then_sub_scope, .{ .ref = {} }, try expr(mod, then_sub_scope, branch_rl, rhs)),
12091209 }, .{});
12101210
12111211 var else_scope: Scope.GenZIR = .{
test/stage2/test.zig+47
......@@ -1462,4 +1462,51 @@ pub fn addCases(ctx: *TestContext) !void {
14621462 "",
14631463 );
14641464 }
1465 {
1466 var case = ctx.exe("orelse at comptime", linux_x64);
1467 case.addCompareOutput(
1468 \\export fn _start() noreturn {
1469 \\ const i: ?u64 = 0;
1470 \\ const orelsed = i orelse 5;
1471 \\ assert(orelsed == 0);
1472 \\ exit();
1473 \\}
1474 \\fn assert(b: bool) void {
1475 \\ if (!b) unreachable;
1476 \\}
1477 \\fn exit() noreturn {
1478 \\ asm volatile ("syscall"
1479 \\ :
1480 \\ : [number] "{rax}" (231),
1481 \\ [arg1] "{rdi}" (0)
1482 \\ : "rcx", "r11", "memory"
1483 \\ );
1484 \\ unreachable;
1485 \\}
1486 ,
1487 "",
1488 );
1489 case.addCompareOutput(
1490 \\export fn _start() noreturn {
1491 \\ const i: ?u64 = null;
1492 \\ const orelsed = i orelse 5;
1493 \\ assert(orelsed == 5);
1494 \\ exit();
1495 \\}
1496 \\fn assert(b: bool) void {
1497 \\ if (!b) unreachable;
1498 \\}
1499 \\fn exit() noreturn {
1500 \\ asm volatile ("syscall"
1501 \\ :
1502 \\ : [number] "{rax}" (231),
1503 \\ [arg1] "{rdi}" (0)
1504 \\ : "rcx", "r11", "memory"
1505 \\ );
1506 \\ unreachable;
1507 \\}
1508 ,
1509 "",
1510 );
1511 }
14651512}