| ... | ... | @@ -32,44 +32,46 @@ const aarch64 = struct { |
| 32 | 32 | clidr: u64, |
| 33 | 33 | ctr: u64, |
| 34 | 34 | }; |
| 35 | |
| 36 | fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { |
| 37 | var value: aarch64.sysctl_cpu_id = undefined; |
| 38 | var len: usize = @sizeOf(@TypeOf(value)); |
| 39 | switch (std.posix.errno(std.c.sysctlbyname("machdep.cpu0.cpu_id", &value, &len, null, 0))) { |
| 40 | .SUCCESS => {}, |
| 41 | .FAULT => unreachable, |
| 42 | .INVAL => unreachable, |
| 43 | .ISDIR => unreachable, |
| 44 | .NOENT => unreachable, // 👻 |
| 45 | .NOMEM => {}, // `aarch64.sysctl_cpu_id` has grown upstream, harmless |
| 46 | .NOTDIR => unreachable, |
| 47 | .NOTEMPTY => unreachable, |
| 48 | .OPNOTSUPP => unreachable, |
| 49 | .PERM => unreachable, |
| 50 | else => return null, |
| 51 | } |
| 52 | |
| 53 | const registers = [12]u64{ |
| 54 | value.midr, |
| 55 | value.aa64pfr0, |
| 56 | value.aa64pfr1, |
| 57 | value.aa64dfr0, |
| 58 | value.aa64dfr1, |
| 59 | 0, // ID_AA64AFR0_EL1 |
| 60 | 0, // ID_AA64AFR1_EL1 |
| 61 | value.aa64isar0, |
| 62 | value.aa64isar1, |
| 63 | value.aa64mmfr0, |
| 64 | value.aa64mmfr1, |
| 65 | value.aa64mmfr2, |
| 66 | }; |
| 67 | |
| 68 | return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers); |
| 69 | } |
| 35 | 70 | }; |
| 36 | 71 | |
| 37 | 72 | pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu { |
| 38 | 73 | return switch (native_arch) { |
| 39 | | .aarch64, .aarch64_be => b: { |
| 40 | | var value: aarch64.sysctl_cpu_id = undefined; |
| 41 | | var len: usize = @sizeOf(@TypeOf(value)); |
| 42 | | switch (std.posix.errno(std.c.sysctlbyname("machdep.cpu0.cpu_id", &value, &len, null, 0))) { |
| 43 | | .SUCCESS => {}, |
| 44 | | .FAULT => unreachable, |
| 45 | | .INVAL => unreachable, |
| 46 | | .ISDIR => unreachable, |
| 47 | | .NOENT => unreachable, // 👻 |
| 48 | | .NOMEM => {}, // `aarch64.sysctl_cpu_id` has grown upstream, harmless |
| 49 | | .NOTDIR => unreachable, |
| 50 | | .NOTEMPTY => unreachable, |
| 51 | | .OPNOTSUPP => unreachable, |
| 52 | | .PERM => unreachable, |
| 53 | | else => return null, |
| 54 | | } |
| 55 | | |
| 56 | | const registers = [12]u64{ |
| 57 | | value.midr, |
| 58 | | value.aa64pfr0, |
| 59 | | value.aa64pfr1, |
| 60 | | value.aa64dfr0, |
| 61 | | value.aa64dfr1, |
| 62 | | 0, // ID_AA64AFR0_EL1 |
| 63 | | 0, // ID_AA64AFR1_EL1 |
| 64 | | value.aa64isar0, |
| 65 | | value.aa64isar1, |
| 66 | | value.aa64mmfr0, |
| 67 | | value.aa64mmfr1, |
| 68 | | value.aa64mmfr2, |
| 69 | | }; |
| 70 | | |
| 71 | | break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers); |
| 72 | | }, |
| 74 | .aarch64, .aarch64_be => aarch64.detectNativeCpuAndFeatures(native_arch), |
| 73 | 75 | else => null, |
| 74 | 76 | }; |
| 75 | 77 | } |