authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-06-30 06:59:06+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-07-01 23:03:15+02:00
log3d7fb4f204940875e7cd9e4dd82f28c464f688e8
treed6693f6cf517798cc8c36bed35a4ab5811d84771
parentfd2d4507c86057bf43ae2198edeb3ebddfa6caca
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.linux: Add detection for some extra RISC-V CPUs

1 files changed, 2 insertions(+), 0 deletions(-)

lib/std/zig/system/linux.zig+2
...@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {...@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
7676
77 const cpu_names = .{77 const cpu_names = .{
78 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },78 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
79 .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
79 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },80 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
80 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },81 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
81 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },82 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
83 .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
82 };84 };
8385
84 fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {86 fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {