authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2025-07-28 13:03:16-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-07-28 22:23:19-07:00
log3fbdd58a874c6b4dae84bed2ed31c945ff4adb54
treecff600f1e759d5f47fec41948eb77afba88ac959
parentecd3ea9bd2f543f44813da21fd6b77d53dd72d7c

aarch64: implement scalar `@mod`

3 files changed, 5048 insertions(+), 1309 deletions(-)

src/codegen/aarch64/Select.zig+246-28
......@@ -1919,8 +1919,8 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
19191919 switch (bits) {
19201920 else => unreachable,
19211921 1...32 => {
1922 try isel.emit(.sub(res_ra.w(), div_ra.w(), .{ .register = rem_ra.w() }));
1923 try isel.emit(.csinc(rem_ra.w(), .wzr, .wzr, .ge));
1922 try isel.emit(.csel(res_ra.w(), div_ra.w(), rem_ra.w(), .pl));
1923 try isel.emit(.sub(rem_ra.w(), div_ra.w(), .{ .immediate = 1 }));
19241924 try isel.emit(.ccmp(
19251925 rem_ra.w(),
19261926 .{ .immediate = 0 },
......@@ -1932,8 +1932,8 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
19321932 try isel.emit(.msub(rem_ra.w(), div_ra.w(), rhs_mat.ra.w(), lhs_mat.ra.w()));
19331933 },
19341934 33...64 => {
1935 try isel.emit(.sub(res_ra.x(), div_ra.x(), .{ .register = rem_ra.x() }));
1936 try isel.emit(.csinc(rem_ra.x(), .xzr, .xzr, .ge));
1935 try isel.emit(.csel(res_ra.x(), div_ra.x(), rem_ra.x(), .pl));
1936 try isel.emit(.sub(rem_ra.x(), div_ra.x(), .{ .immediate = 1 }));
19371937 try isel.emit(.ccmp(
19381938 rem_ra.x(),
19391939 .{ .immediate = 0 },
......@@ -2162,7 +2162,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
21622162 }
21632163 if (air.next()) |next_air_tag| continue :air_tag next_air_tag;
21642164 },
2165 .rem => |air_tag| {
2165 .rem, .rem_optimized, .mod, .mod_optimized => |air_tag| {
21662166 if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: {
21672167 defer res_vi.value.deref(isel);
21682168
......@@ -2180,17 +2180,57 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
21802180 const rhs_mat = try rhs_vi.matReg(isel);
21812181 const div_ra = try isel.allocIntReg();
21822182 defer isel.freeReg(div_ra);
2183 const rem_ra = rem_ra: switch (air_tag) {
2184 else => unreachable,
2185 .rem => res_ra,
2186 .mod => switch (int_info.signedness) {
2187 .signed => {
2188 const rem_ra = try isel.allocIntReg();
2189 errdefer isel.freeReg(rem_ra);
2190 switch (int_info.bits) {
2191 else => unreachable,
2192 1...32 => {
2193 try isel.emit(.csel(res_ra.w(), rem_ra.w(), div_ra.w(), .pl));
2194 try isel.emit(.add(div_ra.w(), rem_ra.w(), .{ .register = rhs_mat.ra.w() }));
2195 try isel.emit(.ccmp(
2196 div_ra.w(),
2197 .{ .immediate = 0 },
2198 .{ .n = false, .z = false, .c = false, .v = false },
2199 .ne,
2200 ));
2201 try isel.emit(.eor(div_ra.w(), rem_ra.w(), .{ .register = rhs_mat.ra.w() }));
2202 try isel.emit(.subs(.wzr, rem_ra.w(), .{ .immediate = 0 }));
2203 },
2204 33...64 => {
2205 try isel.emit(.csel(res_ra.x(), rem_ra.x(), div_ra.x(), .pl));
2206 try isel.emit(.add(div_ra.x(), rem_ra.x(), .{ .register = rhs_mat.ra.x() }));
2207 try isel.emit(.ccmp(
2208 div_ra.x(),
2209 .{ .immediate = 0 },
2210 .{ .n = false, .z = false, .c = false, .v = false },
2211 .ne,
2212 ));
2213 try isel.emit(.eor(div_ra.x(), rem_ra.x(), .{ .register = rhs_mat.ra.x() }));
2214 try isel.emit(.subs(.xzr, rem_ra.x(), .{ .immediate = 0 }));
2215 },
2216 }
2217 break :rem_ra rem_ra;
2218 },
2219 .unsigned => res_ra,
2220 },
2221 };
2222 defer if (rem_ra != res_ra) isel.freeReg(rem_ra);
21832223 switch (int_info.bits) {
21842224 else => unreachable,
21852225 1...32 => {
2186 try isel.emit(.msub(res_ra.w(), div_ra.w(), rhs_mat.ra.w(), lhs_mat.ra.w()));
2226 try isel.emit(.msub(rem_ra.w(), div_ra.w(), rhs_mat.ra.w(), lhs_mat.ra.w()));
21872227 try isel.emit(switch (int_info.signedness) {
21882228 .signed => .sdiv(div_ra.w(), lhs_mat.ra.w(), rhs_mat.ra.w()),
21892229 .unsigned => .udiv(div_ra.w(), lhs_mat.ra.w(), rhs_mat.ra.w()),
21902230 });
21912231 },
21922232 33...64 => {
2193 try isel.emit(.msub(res_ra.x(), div_ra.x(), rhs_mat.ra.x(), lhs_mat.ra.x()));
2233 try isel.emit(.msub(rem_ra.x(), div_ra.x(), rhs_mat.ra.x(), lhs_mat.ra.x()));
21942234 try isel.emit(switch (int_info.signedness) {
21952235 .signed => .sdiv(div_ra.x(), lhs_mat.ra.x(), rhs_mat.ra.x()),
21962236 .unsigned => .udiv(div_ra.x(), lhs_mat.ra.x(), rhs_mat.ra.x()),
......@@ -2201,21 +2241,184 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
22012241 try lhs_mat.finish(isel);
22022242 } else {
22032243 const bits = ty.floatBits(isel.target);
2204
2205 try call.prepareReturn(isel);
2206 switch (bits) {
2244 switch (air_tag) {
22072245 else => unreachable,
2208 16, 32, 64, 128 => try call.returnLiveIn(isel, res_vi.value, .v0),
2209 80 => {
2210 var res_hi16_it = res_vi.value.field(ty, 8, 8);
2211 const res_hi16_vi = try res_hi16_it.only(isel);
2212 try call.returnLiveIn(isel, res_hi16_vi.?, .r1);
2213 var res_lo64_it = res_vi.value.field(ty, 0, 8);
2214 const res_lo64_vi = try res_lo64_it.only(isel);
2215 try call.returnLiveIn(isel, res_lo64_vi.?, .r0);
2246 .rem, .rem_optimized => {
2247 if (!res_vi.value.isUsed(isel)) break :unused;
2248 try call.prepareReturn(isel);
2249 switch (bits) {
2250 else => unreachable,
2251 16, 32, 64, 128 => try call.returnLiveIn(isel, res_vi.value, .v0),
2252 80 => {
2253 var res_hi16_it = res_vi.value.field(ty, 8, 8);
2254 const res_hi16_vi = try res_hi16_it.only(isel);
2255 try call.returnLiveIn(isel, res_hi16_vi.?, .r1);
2256 var res_lo64_it = res_vi.value.field(ty, 0, 8);
2257 const res_lo64_vi = try res_lo64_it.only(isel);
2258 try call.returnLiveIn(isel, res_lo64_vi.?, .r0);
2259 },
2260 }
2261 try call.finishReturn(isel);
2262 },
2263 .mod, .mod_optimized => switch (bits) {
2264 else => unreachable,
2265 16, 32, 64 => {
2266 const res_ra = try res_vi.value.defReg(isel) orelse break :unused;
2267 try call.prepareReturn(isel);
2268 const rem_ra: Register.Alias = .v0;
2269 const temp1_ra: Register.Alias = .v1;
2270 const temp2_ra: Register.Alias = switch (res_ra) {
2271 rem_ra, temp1_ra => .v2,
2272 else => res_ra,
2273 };
2274 const need_fcvt = switch (bits) {
2275 else => unreachable,
2276 16 => !isel.target.cpu.has(.aarch64, .fullfp16),
2277 32, 64 => false,
2278 };
2279 if (need_fcvt) try isel.emit(.fcvt(res_ra.h(), res_ra.s()));
2280 try isel.emit(switch (res_ra) {
2281 rem_ra => .bif(res_ra.@"8b"(), temp2_ra.@"8b"(), temp1_ra.@"8b"()),
2282 temp1_ra => .bsl(res_ra.@"8b"(), rem_ra.@"8b"(), temp2_ra.@"8b"()),
2283 else => .bit(res_ra.@"8b"(), rem_ra.@"8b"(), temp1_ra.@"8b"()),
2284 });
2285 const rhs_vi = try isel.use(bin_op.rhs);
2286 const rhs_mat = try rhs_vi.matReg(isel);
2287 try isel.emit(bits: switch (bits) {
2288 else => unreachable,
2289 16 => if (need_fcvt)
2290 continue :bits 32
2291 else
2292 .fadd(temp2_ra.h(), rem_ra.h(), rhs_mat.ra.h()),
2293 32 => .fadd(temp2_ra.s(), rem_ra.s(), rhs_mat.ra.s()),
2294 64 => .fadd(temp2_ra.d(), rem_ra.d(), rhs_mat.ra.d()),
2295 });
2296 if (need_fcvt) {
2297 try isel.emit(.fcvt(rhs_mat.ra.s(), rhs_mat.ra.h()));
2298 try isel.emit(.fcvt(rem_ra.s(), rem_ra.h()));
2299 }
2300 try isel.emit(.orr(temp1_ra.@"8b"(), temp1_ra.@"8b"(), .{
2301 .register = temp2_ra.@"8b"(),
2302 }));
2303 try isel.emit(switch (bits) {
2304 else => unreachable,
2305 16 => .cmge(temp1_ra.@"4h"(), temp1_ra.@"4h"(), .zero),
2306 32 => .cmge(temp1_ra.@"2s"(), temp1_ra.@"2s"(), .zero),
2307 64 => .cmge(temp1_ra.d(), temp1_ra.d(), .zero),
2308 });
2309 try isel.emit(switch (bits) {
2310 else => unreachable,
2311 16 => .fcmeq(temp2_ra.h(), rem_ra.h(), .zero),
2312 32 => .fcmeq(temp2_ra.s(), rem_ra.s(), .zero),
2313 64 => .fcmeq(temp2_ra.d(), rem_ra.d(), .zero),
2314 });
2315 try isel.emit(.eor(temp1_ra.@"8b"(), rem_ra.@"8b"(), .{
2316 .register = rhs_mat.ra.@"8b"(),
2317 }));
2318 try rhs_mat.finish(isel);
2319 try call.finishReturn(isel);
2320 },
2321 80, 128 => {
2322 if (!res_vi.value.isUsed(isel)) break :unused;
2323 try call.prepareReturn(isel);
2324 switch (bits) {
2325 else => unreachable,
2326 16, 32, 64, 128 => try call.returnLiveIn(isel, res_vi.value, .v0),
2327 80 => {
2328 var res_hi16_it = res_vi.value.field(ty, 8, 8);
2329 const res_hi16_vi = try res_hi16_it.only(isel);
2330 try call.returnLiveIn(isel, res_hi16_vi.?, .r1);
2331 var res_lo64_it = res_vi.value.field(ty, 0, 8);
2332 const res_lo64_vi = try res_lo64_it.only(isel);
2333 try call.returnLiveIn(isel, res_lo64_vi.?, .r0);
2334 },
2335 }
2336 const skip_label = isel.instructions.items.len;
2337 try isel.global_relocs.append(gpa, .{
2338 .name = switch (bits) {
2339 else => unreachable,
2340 16 => "__addhf3",
2341 32 => "__addsf3",
2342 64 => "__adddf3",
2343 80 => "__addxf3",
2344 128 => "__addtf3",
2345 },
2346 .reloc = .{ .label = @intCast(isel.instructions.items.len) },
2347 });
2348 try isel.emit(.bl(0));
2349 const rhs_vi = try isel.use(bin_op.rhs);
2350 switch (bits) {
2351 else => unreachable,
2352 80 => {
2353 const lhs_lo64_ra: Register.Alias = .r0;
2354 const lhs_hi16_ra: Register.Alias = .r1;
2355 const rhs_lo64_ra: Register.Alias = .r2;
2356 const rhs_hi16_ra: Register.Alias = .r3;
2357 const temp_ra: Register.Alias = .r4;
2358 var rhs_hi16_it = rhs_vi.field(ty, 8, 8);
2359 const rhs_hi16_vi = try rhs_hi16_it.only(isel);
2360 try call.paramLiveOut(isel, rhs_hi16_vi.?, rhs_hi16_ra);
2361 var rhs_lo64_it = rhs_vi.field(ty, 0, 8);
2362 const rhs_lo64_vi = try rhs_lo64_it.only(isel);
2363 try call.paramLiveOut(isel, rhs_lo64_vi.?, rhs_lo64_ra);
2364 try isel.emit(.cbz(
2365 temp_ra.x(),
2366 @intCast((isel.instructions.items.len + 1 - skip_label) << 2),
2367 ));
2368 try isel.emit(.orr(temp_ra.x(), lhs_lo64_ra.x(), .{ .shifted_register = .{
2369 .register = lhs_hi16_ra.x(),
2370 .shift = .{ .lsl = 64 - 15 },
2371 } }));
2372 try isel.emit(.tbz(
2373 temp_ra.w(),
2374 15,
2375 @intCast((isel.instructions.items.len + 1 - skip_label) << 2),
2376 ));
2377 try isel.emit(.eor(temp_ra.w(), lhs_hi16_ra.w(), .{
2378 .register = rhs_hi16_ra.w(),
2379 }));
2380 },
2381 128 => {
2382 const lhs_ra: Register.Alias = .v0;
2383 const rhs_ra: Register.Alias = .v1;
2384 const temp1_ra: Register.Alias = .r0;
2385 const temp2_ra: Register.Alias = .r1;
2386 try call.paramLiveOut(isel, rhs_vi, rhs_ra);
2387 try isel.emit(.@"b."(
2388 .pl,
2389 @intCast((isel.instructions.items.len + 1 - skip_label) << 2),
2390 ));
2391 try isel.emit(.cbz(
2392 temp1_ra.x(),
2393 @intCast((isel.instructions.items.len + 1 - skip_label) << 2),
2394 ));
2395 try isel.emit(.orr(temp1_ra.x(), temp1_ra.x(), .{ .shifted_register = .{
2396 .register = temp2_ra.x(),
2397 .shift = .{ .lsl = 1 },
2398 } }));
2399 try isel.emit(.fmov(temp1_ra.x(), .{
2400 .register = rhs_ra.d(),
2401 }));
2402 try isel.emit(.tbz(
2403 temp1_ra.x(),
2404 63,
2405 @intCast((isel.instructions.items.len + 1 - skip_label) << 2),
2406 ));
2407 try isel.emit(.eor(temp1_ra.x(), temp1_ra.x(), .{
2408 .register = temp2_ra.x(),
2409 }));
2410 try isel.emit(.fmov(temp2_ra.x(), .{
2411 .register = rhs_ra.@"d[]"(1),
2412 }));
2413 try isel.emit(.fmov(temp1_ra.x(), .{
2414 .register = lhs_ra.@"d[]"(1),
2415 }));
2416 },
2417 }
2418 try call.finishReturn(isel);
2419 },
22162420 },
22172421 }
2218 try call.finishReturn(isel);
22192422
22202423 try call.prepareCallee(isel);
22212424 try isel.global_relocs.append(gpa, .{
......@@ -9517,12 +9720,12 @@ pub const Value = struct {
95179720 const part_mat = try part_vi.matReg(isel);
95189721 try isel.emit(if (part_vi.isVector(isel)) emit: {
95199722 assert(part_offset == 0 and part_size == vi_size);
9520 break :emit size: switch (vi_size) {
9723 break :emit switch (vi_size) {
95219724 else => unreachable,
95229725 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
95239726 .fmov(ra.h(), .{ .register = part_mat.ra.h() })
95249727 else
9525 continue :size 4,
9728 .dup(ra.h(), part_mat.ra.@"h[]"(0)),
95269729 4 => .fmov(ra.s(), .{ .register = part_mat.ra.s() }),
95279730 8 => .fmov(ra.d(), .{ .register = part_mat.ra.d() }),
95289731 16 => .orr(ra.@"16b"(), part_mat.ra.@"16b"(), .{ .register = part_mat.ra.@"16b"() }),
......@@ -9642,21 +9845,30 @@ pub const Value = struct {
96429845 },
96439846 true => switch (vi.size(isel)) {
96449847 else => unreachable,
9645 2 => .fmov(dst_ra.w(), .{ .register = src_ra.h() }),
9848 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
9849 .fmov(dst_ra.w(), .{ .register = src_ra.h() })
9850 else
9851 .umov(dst_ra.w(), src_ra.@"h[]"(0)),
96469852 4 => .fmov(dst_ra.w(), .{ .register = src_ra.s() }),
96479853 8 => .fmov(dst_ra.x(), .{ .register = src_ra.d() }),
96489854 },
96499855 },
96509856 true => switch (src_ra.isVector()) {
9651 false => switch (vi.size(isel)) {
9857 false => size: switch (vi.size(isel)) {
96529858 else => unreachable,
9653 2 => .fmov(dst_ra.h(), .{ .register = src_ra.w() }),
9859 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
9860 .fmov(dst_ra.h(), .{ .register = src_ra.w() })
9861 else
9862 continue :size 4,
96549863 4 => .fmov(dst_ra.s(), .{ .register = src_ra.w() }),
96559864 8 => .fmov(dst_ra.d(), .{ .register = src_ra.x() }),
96569865 },
96579866 true => switch (vi.size(isel)) {
96589867 else => unreachable,
9659 2 => .fmov(dst_ra.h(), .{ .register = src_ra.h() }),
9868 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
9869 .fmov(dst_ra.h(), .{ .register = src_ra.h() })
9870 else
9871 .dup(dst_ra.h(), src_ra.@"h[]"(0)),
96609872 4 => .fmov(dst_ra.s(), .{ .register = src_ra.s() }),
96619873 8 => .fmov(dst_ra.d(), .{ .register = src_ra.d() }),
96629874 16 => .orr(dst_ra.@"16b"(), src_ra.@"16b"(), .{ .register = src_ra.@"16b"() }),
......@@ -9713,9 +9925,12 @@ pub const Value = struct {
97139925 const part_size = part_vi.size(isel);
97149926 const part_ra = if (part_vi.isVector(isel)) try isel.allocIntReg() else dst_ra;
97159927 defer if (part_ra != dst_ra) isel.freeReg(part_ra);
9716 if (part_ra != dst_ra) try isel.emit(switch (part_size) {
9928 if (part_ra != dst_ra) try isel.emit(part_size: switch (part_size) {
97179929 else => unreachable,
9718 2 => .fmov(dst_ra.h(), .{ .register = part_ra.w() }),
9930 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
9931 .fmov(dst_ra.h(), .{ .register = part_ra.w() })
9932 else
9933 continue :part_size 4,
97199934 4 => .fmov(dst_ra.s(), .{ .register = part_ra.w() }),
97209935 8 => .fmov(dst_ra.d(), .{ .register = part_ra.x() }),
97219936 });
......@@ -10360,7 +10575,10 @@ pub const Value = struct {
1036010575 if (vi.register(isel)) |ra| {
1036110576 if (ra != mat.ra) break :free try isel.emit(if (vi == mat.vi) if (mat.ra.isVector()) switch (size) {
1036210577 else => unreachable,
10363 2 => .fmov(mat.ra.h(), .{ .register = ra.h() }),
10578 2 => if (isel.target.cpu.has(.aarch64, .fullfp16))
10579 .fmov(mat.ra.h(), .{ .register = ra.h() })
10580 else
10581 .dup(mat.ra.h(), ra.@"h[]"(0)),
1036410582 4 => .fmov(mat.ra.s(), .{ .register = ra.s() }),
1036510583 8 => .fmov(mat.ra.d(), .{ .register = ra.d() }),
1036610584 16 => .orr(mat.ra.@"16b"(), ra.@"16b"(), .{ .register = ra.@"16b"() }),
src/codegen/aarch64/encoding.zig+4802-1278
......@@ -81,6 +81,14 @@ pub const Register = struct {
8181 .@"16b", .@"8b" => .byte,
8282 };
8383 }
84
85 pub fn elemSz(arrangement: Arrangement) Instruction.DataProcessingVector.Sz {
86 return switch (arrangement) {
87 else => unreachable,
88 .@"2d", .@"1d" => .double,
89 .@"4s", .@"2s" => .single,
90 };
91 }
8492 };
8593
8694 pub const x0: Register = .{ .alias = .r0, .format = .{ .integer = .doubleword } };
......@@ -6817,7 +6825,7 @@ pub const Instruction = packed union {
68176825 o0: AddSubtractOp = .add,
68186826 Rm: Register.Encoded,
68196827 op21: u2 = 0b01,
6820 U: bool = false,
6828 U: std.builtin.Signedness = .signed,
68216829 decoded24: u5 = 0b11011,
68226830 op54: u2 = 0b00,
68236831 sf: Register.IntegerSize = .doubleword,
......@@ -6831,7 +6839,7 @@ pub const Instruction = packed union {
68316839 o0: AddSubtractOp = .sub,
68326840 Rm: Register.Encoded,
68336841 op21: u2 = 0b01,
6834 U: bool = false,
6842 U: std.builtin.Signedness = .signed,
68356843 decoded24: u5 = 0b11011,
68366844 op54: u2 = 0b00,
68376845 sf: Register.IntegerSize = .doubleword,
......@@ -6845,7 +6853,7 @@ pub const Instruction = packed union {
68456853 o0: AddSubtractOp = .add,
68466854 Rm: Register.Encoded,
68476855 op21: u2 = 0b10,
6848 U: bool = false,
6856 U: std.builtin.Signedness = .signed,
68496857 decoded24: u5 = 0b11011,
68506858 op54: u2 = 0b00,
68516859 sf: Register.IntegerSize = .doubleword,
......@@ -6859,7 +6867,7 @@ pub const Instruction = packed union {
68596867 o0: AddSubtractOp = .add,
68606868 Rm: Register.Encoded,
68616869 op21: u2 = 0b01,
6862 U: bool = true,
6870 U: std.builtin.Signedness = .unsigned,
68636871 decoded24: u5 = 0b11011,
68646872 op54: u2 = 0b00,
68656873 sf: Register.IntegerSize = .doubleword,
......@@ -6873,7 +6881,7 @@ pub const Instruction = packed union {
68736881 o0: AddSubtractOp = .sub,
68746882 Rm: Register.Encoded,
68756883 op21: u2 = 0b01,
6876 U: bool = true,
6884 U: std.builtin.Signedness = .unsigned,
68776885 decoded24: u5 = 0b11011,
68786886 op54: u2 = 0b00,
68796887 sf: Register.IntegerSize = .doubleword,
......@@ -6887,7 +6895,7 @@ pub const Instruction = packed union {
68876895 o0: AddSubtractOp = .add,
68886896 Rm: Register.Encoded,
68896897 op21: u2 = 0b10,
6890 U: bool = true,
6898 U: std.builtin.Signedness = .unsigned,
68916899 decoded24: u5 = 0b11011,
68926900 op54: u2 = 0b00,
68936901 sf: Register.IntegerSize = .doubleword,
......@@ -7009,8 +7017,12 @@ pub const Instruction = packed union {
70097017 /// C4.1.90 Data Processing -- Scalar Floating-Point and Advanced SIMD
70107018 pub const DataProcessingVector = packed union {
70117019 group: @This().Group,
7020 simd_scalar_copy: SimdScalarCopy,
7021 simd_scalar_two_register_miscellaneous_fp16: SimdScalarTwoRegisterMiscellaneousFp16,
7022 simd_scalar_two_register_miscellaneous: SimdScalarTwoRegisterMiscellaneous,
70127023 simd_scalar_pairwise: SimdScalarPairwise,
70137024 simd_copy: SimdCopy,
7025 simd_two_register_miscellaneous_fp16: SimdTwoRegisterMiscellaneousFp16,
70147026 simd_two_register_miscellaneous: SimdTwoRegisterMiscellaneous,
70157027 simd_across_lanes: SimdAcrossLanes,
70167028 simd_three_same: SimdThreeSame,
......@@ -7020,6 +7032,7 @@ pub const Instruction = packed union {
70207032 float_compare: FloatCompare,
70217033 float_immediate: FloatImmediate,
70227034 float_data_processing_two_source: FloatDataProcessingTwoSource,
7035 float_conditional_select: FloatConditionalSelect,
70237036 float_data_processing_three_source: FloatDataProcessingThreeSource,
70247037
70257038 /// Table C4-91 Encoding table for the Data Processing -- Scalar Floating-Point and Advanced SIMD group
......@@ -7032,42 +7045,10 @@ pub const Instruction = packed union {
70327045 op0: u4,
70337046 };
70347047
7035 /// Advanced SIMD scalar pairwise
7036 pub const SimdScalarPairwise = packed union {
7037 group: @This().Group,
7038 addp: Addp,
7039
7040 pub const Group = packed struct {
7041 Rd: Register.Encoded,
7042 Rn: Register.Encoded,
7043 decoded10: u2 = 0b10,
7044 opcode: u5,
7045 decoded17: u5 = 0b11000,
7046 size: Size,
7047 decoded24: u5 = 0b11110,
7048 U: u1,
7049 decoded30: u2 = 0b01,
7050 };
7051
7052 /// C7.2.4 ADDP (scalar)
7053 pub const Addp = packed struct {
7054 Rd: Register.Encoded,
7055 Rn: Register.Encoded,
7056 decoded10: u2 = 0b10,
7057 opcode: u5 = 0b11011,
7058 decoded17: u5 = 0b11000,
7059 size: Size,
7060 decoded24: u5 = 0b11110,
7061 U: u1 = 0b0,
7062 decoded30: u2 = 0b01,
7063 };
7064 };
7065
7066 /// Advanced SIMD copy
7067 pub const SimdCopy = packed union {
7048 /// Advanced SIMD scalar copy
7049 pub const SimdScalarCopy = packed union {
70687050 group: @This().Group,
7069 smov: Smov,
7070 umov: Umov,
7051 dup: Dup,
70717052
70727053 pub const Group = packed struct {
70737054 Rd: Register.Encoded,
......@@ -7076,1127 +7057,3375 @@ pub const Instruction = packed union {
70767057 imm4: u4,
70777058 decoded15: u1 = 0b0,
70787059 imm5: u5,
7079 decoded21: u8 = 0b01110000,
7060 decoded21: u8 = 0b11110000,
70807061 op: u1,
7081 Q: Register.IntegerSize,
7082 decoded31: u1 = 0b0,
7062 decoded30: u2 = 0b01,
70837063 };
70847064
7085 /// C7.2.279 SMOV
7086 pub const Smov = packed struct {
7065 /// C7.2.39 DUP (element)
7066 pub const Dup = packed struct {
70877067 Rd: Register.Encoded,
70887068 Rn: Register.Encoded,
70897069 decoded10: u1 = 0b1,
7090 decoded11: u1 = 0b1,
7091 decoded12: u1 = 0b0,
7092 decoded13: u2 = 0b01,
7070 imm4: u4 = 0b0000,
70937071 decoded15: u1 = 0b0,
70947072 imm5: u5,
7095 decoded21: u8 = 0b01110000,
7096 decoded29: u1 = 0b0,
7097 Q: Register.IntegerSize,
7098 decoded31: u1 = 0b0,
7073 decoded21: u8 = 0b11110000,
7074 op: u1 = 0b0,
7075 decoded30: u2 = 0b01,
70997076 };
71007077
7101 /// C7.2.371 UMOV
7102 pub const Umov = packed struct {
7103 Rd: Register.Encoded,
7104 Rn: Register.Encoded,
7105 decoded10: u1 = 0b1,
7106 decoded11: u1 = 0b1,
7107 decoded12: u1 = 0b1,
7108 decoded13: u2 = 0b01,
7109 decoded15: u1 = 0b0,
7110 imm5: u5,
7111 decoded21: u8 = 0b01110000,
7112 decoded29: u1 = 0b0,
7113 Q: Register.IntegerSize,
7114 decoded31: u1 = 0b0,
7078 pub const Decoded = union(enum) {
7079 unallocated,
7080 dup: Dup,
71157081 };
7082 pub fn decode(inst: @This()) @This().Decoded {
7083 return switch (inst.group.op) {
7084 0b0 => switch (inst.group.imm4) {
7085 else => .unallocated,
7086 0b0000 => .{ .dup = inst.dup },
7087 },
7088 0b1 => .unallocated,
7089 };
7090 }
71167091 };
71177092
7118 /// Advanced SIMD two-register miscellaneous
7119 pub const SimdTwoRegisterMiscellaneous = packed union {
7093 /// Advanced SIMD scalar two-register miscellaneous FP16
7094 pub const SimdScalarTwoRegisterMiscellaneousFp16 = packed union {
71207095 group: @This().Group,
7121 cnt: Cnt,
7096 fcvtns: Fcvtns,
7097 fcvtms: Fcvtms,
7098 fcvtas: Fcvtas,
7099 scvtf: Scvtf,
7100 fcmgt: Fcmgt,
7101 fcmeq: Fcmeq,
7102 fcmlt: Fcmlt,
7103 fcvtps: Fcvtps,
7104 fcvtzs: Fcvtzs,
7105 frecpe: Frecpe,
7106 frecpx: Frecpx,
7107 fcvtnu: Fcvtnu,
7108 fcvtmu: Fcvtmu,
7109 fcvtau: Fcvtau,
7110 ucvtf: Ucvtf,
7111 fcmge: Fcmge,
7112 fcmle: Fcmle,
7113 fcvtpu: Fcvtpu,
7114 fcvtzu: Fcvtzu,
7115 frsqrte: Frsqrte,
71227116
71237117 pub const Group = packed struct {
71247118 Rd: Register.Encoded,
71257119 Rn: Register.Encoded,
71267120 decoded10: u2 = 0b10,
71277121 opcode: u5,
7128 decoded17: u5 = 0b10000,
7129 size: Size,
7130 decoded24: u5 = 0b01110,
7131 U: u1,
7132 Q: Q,
7133 decoded31: u1 = 0b0,
7122 decoded17: u6 = 0b111100,
7123 a: u1,
7124 decoded24: u5 = 0b11110,
7125 U: std.builtin.Signedness,
7126 decoded30: u2 = 0b01,
71347127 };
71357128
7136 /// C7.2.38 CNT
7137 pub const Cnt = packed struct {
7129 /// C7.2.80 FCVTNS (vector)
7130 pub const Fcvtns = packed struct {
71387131 Rd: Register.Encoded,
71397132 Rn: Register.Encoded,
71407133 decoded10: u2 = 0b10,
7141 opcode: u5 = 0b00101,
7142 decoded17: u5 = 0b10000,
7143 size: Size,
7144 decoded24: u5 = 0b01110,
7145 U: u1 = 0b0,
7146 Q: Q,
7147 decoded31: u1 = 0b0,
7134 opcode: u5 = 0b11010,
7135 decoded17: u6 = 0b111100,
7136 o2: u1 = 0b0,
7137 decoded24: u5 = 0b11110,
7138 U: std.builtin.Signedness = .signed,
7139 decoded30: u2 = 0b01,
71487140 };
7149 };
7150
7151 /// Advanced SIMD across lanes
7152 pub const SimdAcrossLanes = packed union {
7153 group: @This().Group,
7154 addv: Addv,
71557141
7156 pub const Group = packed struct {
7142 /// C7.2.75 FCVTMS (vector)
7143 pub const Fcvtms = packed struct {
71577144 Rd: Register.Encoded,
71587145 Rn: Register.Encoded,
71597146 decoded10: u2 = 0b10,
7160 opcode: u5,
7161 decoded17: u5 = 0b11000,
7162 size: Size,
7163 decoded24: u5 = 0b01110,
7164 U: u1,
7165 Q: Q,
7166 decoded31: u1 = 0b0,
7147 opcode: u5 = 0b11011,
7148 decoded17: u6 = 0b111100,
7149 o2: u1 = 0b0,
7150 decoded24: u5 = 0b11110,
7151 U: std.builtin.Signedness = .signed,
7152 decoded30: u2 = 0b01,
71677153 };
71687154
7169 /// C7.2.6 ADDV
7170 pub const Addv = packed struct {
7155 /// C7.2.70 FCVTAS (vector)
7156 pub const Fcvtas = packed struct {
71717157 Rd: Register.Encoded,
71727158 Rn: Register.Encoded,
71737159 decoded10: u2 = 0b10,
7174 opcode: u5 = 0b11011,
7175 decoded17: u5 = 0b11000,
7176 size: Size,
7177 decoded24: u5 = 0b01110,
7178 U: u1 = 0b0,
7179 Q: Q,
7180 decoded31: u1 = 0b0,
7160 opcode: u5 = 0b11100,
7161 decoded17: u6 = 0b111100,
7162 o2: u1 = 0b0,
7163 decoded24: u5 = 0b11110,
7164 U: std.builtin.Signedness = .signed,
7165 decoded30: u2 = 0b01,
71817166 };
7182 };
71837167
7184 /// Advanced SIMD three same
7185 pub const SimdThreeSame = packed union {
7186 group: @This().Group,
7187 addp: Addp,
7188 @"and": And,
7189 bic: Bic,
7190 orr: Orr,
7191 orn: Orn,
7192 eor: Eor,
7168 /// C7.2.234 SCVTF (vector, integer)
7169 pub const Scvtf = packed struct {
7170 Rd: Register.Encoded,
7171 Rn: Register.Encoded,
7172 decoded10: u2 = 0b10,
7173 opcode: u5 = 0b11101,
7174 decoded17: u6 = 0b111100,
7175 o2: u1 = 0b0,
7176 decoded24: u5 = 0b11110,
7177 U: std.builtin.Signedness = .signed,
7178 decoded30: u2 = 0b01,
7179 };
71937180
7194 pub const Group = packed struct {
7181 /// C7.2.61 FCMGT (zero)
7182 pub const Fcmgt = packed struct {
71957183 Rd: Register.Encoded,
71967184 Rn: Register.Encoded,
7197 decoded10: u1 = 0b1,
7198 opcode: u5,
7199 Rm: Register.Encoded,
7200 decoded21: u1 = 0b1,
7201 size: Size,
7202 decoded24: u5 = 0b01110,
7203 U: u1,
7204 Q: Q,
7205 decoded31: u1 = 0b0,
7185 decoded10: u2 = 0b10,
7186 opcode: u5 = 0b01100,
7187 decoded17: u6 = 0b111100,
7188 o2: u1 = 0b1,
7189 decoded24: u5 = 0b11110,
7190 U: std.builtin.Signedness = .signed,
7191 decoded30: u2 = 0b01,
72067192 };
72077193
7208 /// C7.2.5 ADDP (vector)
7209 pub const Addp = packed struct {
7194 /// C7.2.57 FCMEQ (zero)
7195 pub const Fcmeq = packed struct {
72107196 Rd: Register.Encoded,
72117197 Rn: Register.Encoded,
7212 decoded10: u1 = 0b1,
7213 opcode: u5 = 0b10111,
7214 Rm: Register.Encoded,
7215 decoded21: u1 = 0b1,
7216 size: Size,
7217 decoded24: u5 = 0b01110,
7218 U: u1 = 0b0,
7219 Q: Q,
7220 decoded31: u1 = 0b0,
7198 decoded10: u2 = 0b10,
7199 opcode: u5 = 0b01101,
7200 decoded17: u6 = 0b111100,
7201 o2: u1 = 0b1,
7202 decoded24: u5 = 0b11110,
7203 U: std.builtin.Signedness = .signed,
7204 decoded30: u2 = 0b01,
72217205 };
72227206
7223 /// C7.2.11 AND (vector)
7224 pub const And = packed struct {
7207 /// C7.2.65 FCMLT (zero)
7208 pub const Fcmlt = packed struct {
72257209 Rd: Register.Encoded,
72267210 Rn: Register.Encoded,
7227 decoded10: u1 = 0b1,
7228 opcode: u5 = 0b00011,
7229 Rm: Register.Encoded,
7230 decoded21: u1 = 0b1,
7231 size: Size = .byte,
7232 decoded24: u5 = 0b01110,
7233 U: u1 = 0b0,
7234 Q: Q,
7235 decoded31: u1 = 0b0,
7211 decoded10: u2 = 0b10,
7212 opcode: u5 = 0b01110,
7213 decoded17: u6 = 0b111100,
7214 o2: u1 = 0b1,
7215 decoded24: u5 = 0b11110,
7216 U: std.builtin.Signedness = .signed,
7217 decoded30: u2 = 0b01,
72367218 };
72377219
7238 /// C7.2.21 BIC (vector, register)
7239 pub const Bic = packed struct {
7220 /// C7.2.84 FCVTPS (vector)
7221 pub const Fcvtps = packed struct {
72407222 Rd: Register.Encoded,
72417223 Rn: Register.Encoded,
7242 decoded10: u1 = 0b1,
7243 opcode: u5 = 0b00011,
7244 Rm: Register.Encoded,
7245 decoded21: u1 = 0b1,
7246 size: Size = .half,
7247 decoded24: u5 = 0b01110,
7248 U: u1 = 0b0,
7249 Q: Q,
7250 decoded31: u1 = 0b0,
7224 decoded10: u2 = 0b10,
7225 opcode: u5 = 0b11010,
7226 decoded17: u6 = 0b111100,
7227 o2: u1 = 0b1,
7228 decoded24: u5 = 0b11110,
7229 U: std.builtin.Signedness = .signed,
7230 decoded30: u2 = 0b01,
72517231 };
72527232
7253 /// C7.2.213 ORR (vector, register)
7254 pub const Orr = packed struct {
7233 /// C7.2.90 FCVTZS (vector, integer)
7234 pub const Fcvtzs = packed struct {
72557235 Rd: Register.Encoded,
72567236 Rn: Register.Encoded,
7257 decoded10: u1 = 0b1,
7258 opcode: u5 = 0b00011,
7259 Rm: Register.Encoded,
7260 decoded21: u1 = 0b1,
7261 size: Size = .single,
7262 decoded24: u5 = 0b01110,
7263 U: u1 = 0b0,
7264 Q: Q,
7265 decoded31: u1 = 0b0,
7237 decoded10: u2 = 0b10,
7238 opcode: u5 = 0b11011,
7239 decoded17: u6 = 0b111100,
7240 o2: u1 = 0b1,
7241 decoded24: u5 = 0b11110,
7242 U: std.builtin.Signedness = .signed,
7243 decoded30: u2 = 0b01,
72667244 };
72677245
7268 /// C7.2.211 ORN (vector)
7269 pub const Orn = packed struct {
7246 /// C7.2.144 FRECPE
7247 pub const Frecpe = packed struct {
72707248 Rd: Register.Encoded,
72717249 Rn: Register.Encoded,
7272 decoded10: u1 = 0b1,
7273 opcode: u5 = 0b00011,
7274 Rm: Register.Encoded,
7275 decoded21: u1 = 0b1,
7276 size: Size = .double,
7277 decoded24: u5 = 0b01110,
7278 U: u1 = 0b0,
7279 Q: Q,
7280 decoded31: u1 = 0b0,
7250 decoded10: u2 = 0b10,
7251 opcode: u5 = 0b11101,
7252 decoded17: u6 = 0b111100,
7253 o2: u1 = 0b1,
7254 decoded24: u5 = 0b11110,
7255 U: std.builtin.Signedness = .signed,
7256 decoded30: u2 = 0b01,
72817257 };
72827258
7283 /// C7.2.41 EOR (vector)
7284 pub const Eor = packed struct {
7259 /// C7.2.146 FRECPX
7260 pub const Frecpx = packed struct {
72857261 Rd: Register.Encoded,
72867262 Rn: Register.Encoded,
7287 decoded10: u1 = 0b1,
7288 opcode: u5 = 0b00011,
7289 Rm: Register.Encoded,
7290 decoded21: u1 = 0b1,
7291 size: Size = .byte,
7292 decoded24: u5 = 0b01110,
7293 U: u1 = 0b1,
7294 Q: Q,
7295 decoded31: u1 = 0b0,
7263 decoded10: u2 = 0b10,
7264 opcode: u5 = 0b11111,
7265 decoded17: u6 = 0b111100,
7266 o2: u1 = 0b1,
7267 decoded24: u5 = 0b11110,
7268 U: std.builtin.Signedness = .signed,
7269 decoded30: u2 = 0b01,
72967270 };
7297 };
72987271
7299 /// Advanced SIMD modified immediate
7300 pub const SimdModifiedImmediate = packed union {
7301 group: @This().Group,
7302 movi: Movi,
7303 orr: Orr,
7304 fmov: Fmov,
7305 mvni: Mvni,
7306 bic: Bic,
7272 /// C7.2.82 FCVTNU (vector)
7273 pub const Fcvtnu = packed struct {
7274 Rd: Register.Encoded,
7275 Rn: Register.Encoded,
7276 decoded10: u2 = 0b10,
7277 opcode: u5 = 0b11010,
7278 decoded17: u6 = 0b111100,
7279 o2: u1 = 0b0,
7280 decoded24: u5 = 0b11110,
7281 U: std.builtin.Signedness = .unsigned,
7282 decoded30: u2 = 0b01,
7283 };
73077284
7308 pub const Group = packed struct {
7285 /// C7.2.77 FCVTMU (vector)
7286 pub const Fcvtmu = packed struct {
73097287 Rd: Register.Encoded,
7310 imm5: u5,
7311 decoded10: u1 = 0b1,
7312 o2: u1,
7313 cmode: u4,
7314 imm3: u3,
7315 decoded19: u10 = 0b0111100000,
7316 op: u1,
7317 Q: Q,
7318 decoded31: u1 = 0b0,
7288 Rn: Register.Encoded,
7289 decoded10: u2 = 0b10,
7290 opcode: u5 = 0b11011,
7291 decoded17: u6 = 0b111100,
7292 o2: u1 = 0b0,
7293 decoded24: u5 = 0b11110,
7294 U: std.builtin.Signedness = .unsigned,
7295 decoded30: u2 = 0b01,
73197296 };
73207297
7321 /// C7.2.204 MOVI
7322 pub const Movi = packed struct {
7298 /// C7.2.72 FCVTAU (vector)
7299 pub const Fcvtau = packed struct {
73237300 Rd: Register.Encoded,
7324 imm5: u5,
7325 decoded10: u1 = 0b1,
7301 Rn: Register.Encoded,
7302 decoded10: u2 = 0b10,
7303 opcode: u5 = 0b11100,
7304 decoded17: u6 = 0b111100,
73267305 o2: u1 = 0b0,
7327 cmode: u4,
7328 imm3: u3,
7329 decoded19: u10 = 0b0111100000,
7330 op: u1,
7331 Q: Q,
7332 decoded31: u1 = 0b0,
7306 decoded24: u5 = 0b11110,
7307 U: std.builtin.Signedness = .unsigned,
7308 decoded30: u2 = 0b01,
73337309 };
73347310
7335 /// C7.2.212 ORR (vector, immediate)
7336 pub const Orr = packed struct {
7311 /// C7.2.353 UCVTF (vector, integer)
7312 pub const Ucvtf = packed struct {
73377313 Rd: Register.Encoded,
7338 imm5: u5,
7339 decoded10: u1 = 0b1,
7314 Rn: Register.Encoded,
7315 decoded10: u2 = 0b10,
7316 opcode: u5 = 0b11101,
7317 decoded17: u6 = 0b111100,
73407318 o2: u1 = 0b0,
7341 cmode0: u1 = 0b1,
7342 cmode: u3,
7343 imm3: u3,
7344 decoded19: u10 = 0b0111100000,
7345 op: u1 = 0b0,
7346 Q: Q,
7347 decoded31: u1 = 0b0,
7319 decoded24: u5 = 0b11110,
7320 U: std.builtin.Signedness = .unsigned,
7321 decoded30: u2 = 0b01,
73487322 };
73497323
7350 /// C7.2.129 FMOV (vector, immediate)
7351 pub const Fmov = packed struct {
7324 /// C7.2.59 FCMGE (zero)
7325 pub const Fcmge = packed struct {
73527326 Rd: Register.Encoded,
7353 imm5: u5,
7354 decoded10: u1 = 0b1,
7327 Rn: Register.Encoded,
7328 decoded10: u2 = 0b10,
7329 opcode: u5 = 0b01100,
7330 decoded17: u6 = 0b111100,
73557331 o2: u1 = 0b1,
7356 cmode: u4 = 0b1111,
7357 imm3: u3,
7358 decoded19: u10 = 0b0111100000,
7359 op: u1 = 0b0,
7360 Q: Q,
7361 decoded31: u1 = 0b0,
7332 decoded24: u5 = 0b11110,
7333 U: std.builtin.Signedness = .unsigned,
7334 decoded30: u2 = 0b01,
73627335 };
73637336
7364 /// C7.2.208 MVNI
7365 pub const Mvni = packed struct {
7337 /// C7.2.64 FCMLE (zero)
7338 pub const Fcmle = packed struct {
73667339 Rd: Register.Encoded,
7367 imm5: u5,
7368 decoded10: u1 = 0b1,
7369 o2: u1 = 0b0,
7370 cmode: u4,
7371 imm3: u3,
7372 decoded19: u10 = 0b0111100000,
7373 op: u1 = 0b1,
7374 Q: Q,
7375 decoded31: u1 = 0b0,
7340 Rn: Register.Encoded,
7341 decoded10: u2 = 0b10,
7342 opcode: u5 = 0b01101,
7343 decoded17: u6 = 0b111100,
7344 o2: u1 = 0b1,
7345 decoded24: u5 = 0b11110,
7346 U: std.builtin.Signedness = .unsigned,
7347 decoded30: u2 = 0b01,
73767348 };
73777349
7378 /// C7.2.20 BIC (vector, immediate)
7379 pub const Bic = packed struct {
7350 /// C7.2.86 FCVTPU (vector)
7351 pub const Fcvtpu = packed struct {
73807352 Rd: Register.Encoded,
7381 imm5: u5,
7382 decoded10: u1 = 0b1,
7383 o2: u1 = 0b0,
7384 cmode0: u1 = 0b1,
7385 cmode: u3,
7386 imm3: u3,
7387 decoded19: u10 = 0b0111100000,
7388 op: u1 = 0b1,
7389 Q: Q,
7390 decoded31: u1 = 0b0,
7353 Rn: Register.Encoded,
7354 decoded10: u2 = 0b10,
7355 opcode: u5 = 0b11010,
7356 decoded17: u6 = 0b111100,
7357 o2: u1 = 0b1,
7358 decoded24: u5 = 0b11110,
7359 U: std.builtin.Signedness = .unsigned,
7360 decoded30: u2 = 0b01,
7361 };
7362
7363 /// C7.2.94 FCVTZU (vector, integer)
7364 pub const Fcvtzu = packed struct {
7365 Rd: Register.Encoded,
7366 Rn: Register.Encoded,
7367 decoded10: u2 = 0b10,
7368 opcode: u5 = 0b11011,
7369 decoded17: u6 = 0b111100,
7370 o2: u1 = 0b1,
7371 decoded24: u5 = 0b11110,
7372 U: std.builtin.Signedness = .unsigned,
7373 decoded30: u2 = 0b01,
7374 };
7375
7376 /// C7.2.169 FRSQRTE
7377 pub const Frsqrte = packed struct {
7378 Rd: Register.Encoded,
7379 Rn: Register.Encoded,
7380 decoded10: u2 = 0b10,
7381 opcode: u5 = 0b11101,
7382 decoded17: u6 = 0b111100,
7383 o2: u1 = 0b1,
7384 decoded24: u5 = 0b11110,
7385 U: std.builtin.Signedness = .unsigned,
7386 decoded30: u2 = 0b01,
73917387 };
73927388 };
73937389
7394 /// Conversion between floating-point and integer
7395 pub const ConvertFloatInteger = packed union {
7390 /// Advanced SIMD scalar two-register miscellaneous
7391 pub const SimdScalarTwoRegisterMiscellaneous = packed union {
73967392 group: @This().Group,
7393 suqadd: Suqadd,
7394 sqabs: Sqabs,
7395 cmgt: Cmgt,
7396 cmeq: Cmeq,
7397 cmlt: Cmlt,
7398 abs: Abs,
7399 sqxtn: Sqxtn,
73977400 fcvtns: Fcvtns,
7398 fcvtnu: Fcvtnu,
7399 scvtf: Scvtf,
7400 ucvtf: Ucvtf,
7401 fcvtms: Fcvtms,
74017402 fcvtas: Fcvtas,
7402 fcvtau: Fcvtau,
7403 fmov: Fmov,
7403 scvtf: Scvtf,
7404 fcmgt: Fcmgt,
7405 fcmeq: Fcmeq,
7406 fcmlt: Fcmlt,
74047407 fcvtps: Fcvtps,
7405 fcvtpu: Fcvtpu,
7406 fcvtms: Fcvtms,
7407 fcvtmu: Fcvtmu,
74087408 fcvtzs: Fcvtzs,
7409 frecpe: Frecpe,
7410 frecpx: Frecpx,
7411 usqadd: Usqadd,
7412 sqneg: Sqneg,
7413 cmge: Cmge,
7414 cmle: Cmle,
7415 neg: Neg,
7416 sqxtun: Sqxtun,
7417 uqxtn: Uqxtn,
7418 fcvtxn: Fcvtxn,
7419 fcvtnu: Fcvtnu,
7420 fcvtmu: Fcvtmu,
7421 fcvtau: Fcvtau,
7422 ucvtf: Ucvtf,
7423 fcmge: Fcmge,
7424 fcmle: Fcmle,
7425 fcvtpu: Fcvtpu,
74097426 fcvtzu: Fcvtzu,
7410 fjcvtzs: Fjcvtzs,
7427 frsqrte: Frsqrte,
74117428
74127429 pub const Group = packed struct {
74137430 Rd: Register.Encoded,
74147431 Rn: Register.Encoded,
7415 decoded10: u6 = 0b000000,
7416 opcode: u3,
7417 rmode: u2,
7418 decoded21: u1 = 0b1,
7419 ptype: Ftype,
7432 decoded10: u2 = 0b10,
7433 opcode: u5,
7434 decoded17: u5 = 0b10000,
7435 size: Size,
74207436 decoded24: u5 = 0b11110,
7421 S: bool,
7422 decoded30: u1 = 0b0,
7423 sf: Register.IntegerSize,
7437 U: std.builtin.Signedness,
7438 decoded30: u2 = 0b01,
74247439 };
74257440
7426 /// C7.2.81 FCVTNS (scalar)
7427 pub const Fcvtns = packed struct {
7441 /// C7.2.337 SUQADD
7442 pub const Suqadd = packed struct {
74287443 Rd: Register.Encoded,
74297444 Rn: Register.Encoded,
7430 decoded10: u6 = 0b000000,
7431 opcode: u3 = 0b000,
7432 rmode: Rmode = .n,
7433 decoded21: u1 = 0b1,
7434 ftype: Ftype,
7445 decoded10: u2 = 0b10,
7446 opcode: u5 = 0b00011,
7447 decoded17: u5 = 0b10000,
7448 size: Size,
74357449 decoded24: u5 = 0b11110,
7436 S: bool = false,
7437 decoded30: u1 = 0b0,
7438 sf: Register.IntegerSize,
7450 U: std.builtin.Signedness = .signed,
7451 decoded30: u2 = 0b01,
74397452 };
74407453
7441 /// C7.2.83 FCVTNU (scalar)
7442 pub const Fcvtnu = packed struct {
7454 /// C7.2.282 SQABS
7455 pub const Sqabs = packed struct {
74437456 Rd: Register.Encoded,
74447457 Rn: Register.Encoded,
7445 decoded10: u6 = 0b000000,
7446 opcode: u3 = 0b001,
7447 rmode: Rmode = .n,
7448 decoded21: u1 = 0b1,
7449 ftype: Ftype,
7458 decoded10: u2 = 0b10,
7459 opcode: u5 = 0b00111,
7460 decoded17: u5 = 0b10000,
7461 size: Size,
74507462 decoded24: u5 = 0b11110,
7451 S: bool = false,
7452 decoded30: u1 = 0b0,
7453 sf: Register.IntegerSize,
7463 U: std.builtin.Signedness = .signed,
7464 decoded30: u2 = 0b01,
74547465 };
74557466
7456 /// C7.2.236 SCVTF (scalar, integer)
7457 pub const Scvtf = packed struct {
7467 /// C7.2.32 CMGT (zero)
7468 pub const Cmgt = packed struct {
74587469 Rd: Register.Encoded,
74597470 Rn: Register.Encoded,
7460 decoded10: u6 = 0b000000,
7461 opcode: u3 = 0b010,
7462 rmode: Rmode = .n,
7463 decoded21: u1 = 0b1,
7464 ftype: Ftype,
7471 decoded10: u2 = 0b10,
7472 opcode: u5 = 0b01000,
7473 decoded17: u5 = 0b10000,
7474 size: Size,
74657475 decoded24: u5 = 0b11110,
7466 S: bool = false,
7467 decoded30: u1 = 0b0,
7468 sf: Register.IntegerSize,
7476 U: std.builtin.Signedness = .signed,
7477 decoded30: u2 = 0b01,
74697478 };
74707479
7471 /// C7.2.355 UCVTF (scalar, integer)
7472 pub const Ucvtf = packed struct {
7480 /// C7.2.28 CMEQ (zero)
7481 pub const Cmeq = packed struct {
74737482 Rd: Register.Encoded,
74747483 Rn: Register.Encoded,
7475 decoded10: u6 = 0b000000,
7476 opcode: u3 = 0b011,
7477 rmode: Rmode = .n,
7478 decoded21: u1 = 0b1,
7479 ftype: Ftype,
7484 decoded10: u2 = 0b10,
7485 opcode: u5 = 0b01001,
7486 decoded17: u5 = 0b10000,
7487 size: Size,
74807488 decoded24: u5 = 0b11110,
7481 S: bool = false,
7482 decoded30: u1 = 0b0,
7483 sf: Register.IntegerSize,
7489 U: std.builtin.Signedness = .signed,
7490 decoded30: u2 = 0b01,
74847491 };
74857492
7486 /// C7.2.71 FCVTAS (scalar)
7487 pub const Fcvtas = packed struct {
7493 /// C7.2.36 CMLT (zero)
7494 pub const Cmlt = packed struct {
74887495 Rd: Register.Encoded,
74897496 Rn: Register.Encoded,
7490 decoded10: u6 = 0b000000,
7491 opcode: u3 = 0b100,
7492 rmode: Rmode = .n,
7493 decoded21: u1 = 0b1,
7494 ftype: Ftype,
7497 decoded10: u2 = 0b10,
7498 opcode: u5 = 0b01010,
7499 decoded17: u5 = 0b10000,
7500 size: Size,
74957501 decoded24: u5 = 0b11110,
7496 S: bool = false,
7497 decoded30: u1 = 0b0,
7498 sf: Register.IntegerSize,
7502 U: std.builtin.Signedness = .signed,
7503 decoded30: u2 = 0b01,
74997504 };
75007505
7501 /// C7.2.73 FCVTAU (scalar)
7502 pub const Fcvtau = packed struct {
7506 /// C7.2.1 ABS
7507 pub const Abs = packed struct {
75037508 Rd: Register.Encoded,
75047509 Rn: Register.Encoded,
7505 decoded10: u6 = 0b000000,
7506 opcode: u3 = 0b101,
7507 rmode: Rmode = .n,
7508 decoded21: u1 = 0b1,
7509 ftype: Ftype,
7510 decoded10: u2 = 0b10,
7511 opcode: u5 = 0b01011,
7512 decoded17: u5 = 0b10000,
7513 size: Size,
75107514 decoded24: u5 = 0b11110,
7511 S: bool = false,
7512 decoded30: u1 = 0b0,
7513 sf: Register.IntegerSize,
7515 U: std.builtin.Signedness = .signed,
7516 decoded30: u2 = 0b01,
75147517 };
75157518
7516 /// C7.2.131 FMOV (general)
7517 pub const Fmov = packed struct {
7519 /// C7.2.308 SQXTN
7520 pub const Sqxtn = packed struct {
75187521 Rd: Register.Encoded,
75197522 Rn: Register.Encoded,
7520 decoded10: u6 = 0b000000,
7521 opcode: Opcode,
7522 rmode: Fmov.Rmode,
7523 decoded21: u1 = 0b1,
7524 ftype: Ftype,
7523 decoded10: u2 = 0b10,
7524 opcode: u5 = 0b10100,
7525 decoded17: u5 = 0b10000,
7526 size: Size,
75257527 decoded24: u5 = 0b11110,
7526 S: bool = false,
7527 decoded30: u1 = 0b0,
7528 sf: Register.IntegerSize,
7529
7530 pub const Opcode = enum(u3) {
7531 float_to_integer = 0b110,
7532 integer_to_float = 0b111,
7533 _,
7534 };
7535
7536 pub const Rmode = enum(u2) {
7537 @"0" = 0b00,
7538 @"1" = 0b01,
7539 _,
7540 };
7528 U: std.builtin.Signedness = .signed,
7529 decoded30: u2 = 0b01,
75417530 };
75427531
7543 /// C7.2.85 FCVTPS (scalar)
7544 pub const Fcvtps = packed struct {
7532 /// C7.2.80 FCVTNS (vector)
7533 pub const Fcvtns = packed struct {
75457534 Rd: Register.Encoded,
75467535 Rn: Register.Encoded,
7547 decoded10: u6 = 0b000000,
7548 opcode: u3 = 0b000,
7549 rmode: Rmode = .p,
7550 decoded21: u1 = 0b1,
7551 ftype: Ftype,
7536 decoded10: u2 = 0b10,
7537 opcode: u5 = 0b11010,
7538 decoded17: u5 = 0b10000,
7539 sz: Sz,
7540 o2: u1 = 0b0,
75527541 decoded24: u5 = 0b11110,
7553 S: bool = false,
7554 decoded30: u1 = 0b0,
7555 sf: Register.IntegerSize,
7542 U: std.builtin.Signedness = .signed,
7543 decoded30: u2 = 0b01,
75567544 };
75577545
7558 /// C7.2.87 FCVTPU (scalar)
7559 pub const Fcvtpu = packed struct {
7546 /// C7.2.75 FCVTMS (vector)
7547 pub const Fcvtms = packed struct {
75607548 Rd: Register.Encoded,
75617549 Rn: Register.Encoded,
7562 decoded10: u6 = 0b000000,
7563 opcode: u3 = 0b001,
7564 rmode: Rmode = .p,
7565 decoded21: u1 = 0b1,
7566 ftype: Ftype,
7550 decoded10: u2 = 0b10,
7551 opcode: u5 = 0b11011,
7552 decoded17: u5 = 0b10000,
7553 sz: Sz,
7554 o2: u1 = 0b0,
75677555 decoded24: u5 = 0b11110,
7568 S: bool = false,
7569 decoded30: u1 = 0b0,
7570 sf: Register.IntegerSize,
7556 U: std.builtin.Signedness = .signed,
7557 decoded30: u2 = 0b01,
75717558 };
75727559
7573 /// C7.2.76 FCVTMS (scalar)
7574 pub const Fcvtms = packed struct {
7560 /// C7.2.70 FCVTAS (vector)
7561 pub const Fcvtas = packed struct {
75757562 Rd: Register.Encoded,
75767563 Rn: Register.Encoded,
7577 decoded10: u6 = 0b000000,
7578 opcode: u3 = 0b000,
7579 rmode: Rmode = .m,
7580 decoded21: u1 = 0b1,
7581 ftype: Ftype,
7564 decoded10: u2 = 0b10,
7565 opcode: u5 = 0b11100,
7566 decoded17: u5 = 0b10000,
7567 sz: Sz,
7568 o2: u1 = 0b0,
75827569 decoded24: u5 = 0b11110,
7583 S: bool = false,
7584 decoded30: u1 = 0b0,
7585 sf: Register.IntegerSize,
7570 U: std.builtin.Signedness = .signed,
7571 decoded30: u2 = 0b01,
75867572 };
75877573
7588 /// C7.2.78 FCVTMU (scalar)
7589 pub const Fcvtmu = packed struct {
7574 /// C7.2.234 SCVTF (vector, integer)
7575 pub const Scvtf = packed struct {
75907576 Rd: Register.Encoded,
75917577 Rn: Register.Encoded,
7592 decoded10: u6 = 0b000000,
7593 opcode: u3 = 0b001,
7594 rmode: Rmode = .m,
7595 decoded21: u1 = 0b1,
7596 ftype: Ftype,
7578 decoded10: u2 = 0b10,
7579 opcode: u5 = 0b11101,
7580 decoded17: u5 = 0b10000,
7581 sz: Sz,
7582 o2: u1 = 0b0,
75977583 decoded24: u5 = 0b11110,
7598 S: bool = false,
7599 decoded30: u1 = 0b0,
7600 sf: Register.IntegerSize,
7584 U: std.builtin.Signedness = .signed,
7585 decoded30: u2 = 0b01,
76017586 };
76027587
7603 /// C7.2.92 FCVTZS (scalar, integer)
7604 pub const Fcvtzs = packed struct {
7588 /// C7.2.61 FCMGT (zero)
7589 pub const Fcmgt = packed struct {
76057590 Rd: Register.Encoded,
76067591 Rn: Register.Encoded,
7607 decoded10: u6 = 0b000000,
7608 opcode: u3 = 0b000,
7609 rmode: Rmode = .z,
7610 decoded21: u1 = 0b1,
7611 ftype: Ftype,
7592 decoded10: u2 = 0b10,
7593 opcode: u5 = 0b01100,
7594 decoded17: u5 = 0b10000,
7595 sz: Sz,
7596 o2: u1 = 0b1,
76127597 decoded24: u5 = 0b11110,
7613 S: bool = false,
7614 decoded30: u1 = 0b0,
7615 sf: Register.IntegerSize,
7598 U: std.builtin.Signedness = .signed,
7599 decoded30: u2 = 0b01,
76167600 };
76177601
7618 /// C7.2.96 FCVTZU (scalar, integer)
7619 pub const Fcvtzu = packed struct {
7602 /// C7.2.57 FCMEQ (zero)
7603 pub const Fcmeq = packed struct {
76207604 Rd: Register.Encoded,
76217605 Rn: Register.Encoded,
7622 decoded10: u6 = 0b000000,
7623 opcode: u3 = 0b001,
7624 rmode: Rmode = .z,
7625 decoded21: u1 = 0b1,
7626 ftype: Ftype,
7606 decoded10: u2 = 0b10,
7607 opcode: u5 = 0b01101,
7608 decoded17: u5 = 0b10000,
7609 sz: Sz,
7610 o2: u1 = 0b1,
76277611 decoded24: u5 = 0b11110,
7628 S: bool = false,
7629 decoded30: u1 = 0b0,
7630 sf: Register.IntegerSize,
7612 U: std.builtin.Signedness = .signed,
7613 decoded30: u2 = 0b01,
76317614 };
76327615
7633 /// C7.2.99 FJCVTZS
7634 pub const Fjcvtzs = packed struct {
7616 /// C7.2.65 FCMLT (zero)
7617 pub const Fcmlt = packed struct {
76357618 Rd: Register.Encoded,
76367619 Rn: Register.Encoded,
7637 decoded10: u6 = 0b000000,
7638 opcode: u3 = 0b110,
7639 rmode: Rmode = .z,
7640 decoded21: u1 = 0b1,
7641 ftype: Ftype = .double,
7620 decoded10: u2 = 0b10,
7621 opcode: u5 = 0b01110,
7622 decoded17: u5 = 0b10000,
7623 sz: Sz,
7624 o2: u1 = 0b1,
76427625 decoded24: u5 = 0b11110,
7643 S: bool = false,
7644 decoded30: u1 = 0b0,
7645 sf: Register.IntegerSize = .word,
7626 U: std.builtin.Signedness = .signed,
7627 decoded30: u2 = 0b01,
76467628 };
76477629
7648 pub const Rmode = enum(u2) {
7649 /// to nearest
7650 n = 0b00,
7651 /// toward plus infinity
7652 p = 0b01,
7653 /// toward minus infinity
7654 m = 0b10,
7655 /// toward zero
7656 z = 0b11,
7630 /// C7.2.84 FCVTPS (vector)
7631 pub const Fcvtps = packed struct {
7632 Rd: Register.Encoded,
7633 Rn: Register.Encoded,
7634 decoded10: u2 = 0b10,
7635 opcode: u5 = 0b11010,
7636 decoded17: u5 = 0b10000,
7637 sz: Sz,
7638 o2: u1 = 0b1,
7639 decoded24: u5 = 0b11110,
7640 U: std.builtin.Signedness = .signed,
7641 decoded30: u2 = 0b01,
76577642 };
7658 };
7659
7660 /// Floating-point data-processing (1 source)
7661 pub const FloatDataProcessingOneSource = packed union {
7662 group: @This().Group,
7663 fmov: Fmov,
7664 fabs: Fabs,
7665 fneg: Fneg,
7666 fsqrt: Fsqrt,
7667 fcvt: Fcvt,
7668 frintn: Frintn,
7669 frintp: Frintp,
7670 frintm: Frintm,
7671 frintz: Frintz,
7672 frinta: Frinta,
7673 frintx: Frintx,
7674 frinti: Frinti,
76757643
7676 pub const Group = packed struct {
7644 /// C7.2.90 FCVTZS (vector, integer)
7645 pub const Fcvtzs = packed struct {
76777646 Rd: Register.Encoded,
76787647 Rn: Register.Encoded,
7679 decoded10: u5 = 0b10000,
7680 opcode: u6,
7681 decoded21: u1 = 0b1,
7682 ptype: Ftype,
7648 decoded10: u2 = 0b10,
7649 opcode: u5 = 0b11011,
7650 decoded17: u5 = 0b10000,
7651 sz: Sz,
7652 o2: u1 = 0b1,
76837653 decoded24: u5 = 0b11110,
7684 S: bool,
7685 decoded30: u1 = 0b0,
7686 M: u1,
7654 U: std.builtin.Signedness = .signed,
7655 decoded30: u2 = 0b01,
76877656 };
76887657
7689 /// C7.2.130 FMOV (register)
7690 pub const Fmov = packed struct {
7658 /// C7.2.144 FRECPE
7659 pub const Frecpe = packed struct {
76917660 Rd: Register.Encoded,
76927661 Rn: Register.Encoded,
7693 decoded10: u5 = 0b10000,
7694 opc: u2 = 0b00,
7695 decoded17: u4 = 0b0000,
7696 decoded21: u1 = 0b1,
7697 ftype: Ftype,
7662 decoded10: u2 = 0b10,
7663 opcode: u5 = 0b11101,
7664 decoded17: u5 = 0b10000,
7665 sz: Sz,
7666 o2: u1 = 0b1,
76987667 decoded24: u5 = 0b11110,
7699 S: bool = false,
7700 decoded30: u1 = 0b0,
7701 M: u1 = 0b0,
7668 U: std.builtin.Signedness = .signed,
7669 decoded30: u2 = 0b01,
77027670 };
77037671
7704 /// C7.2.46 FABS (scalar)
7705 pub const Fabs = packed struct {
7672 /// C7.2.146 FRECPX
7673 pub const Frecpx = packed struct {
77067674 Rd: Register.Encoded,
77077675 Rn: Register.Encoded,
7708 decoded10: u5 = 0b10000,
7709 opc: u2 = 0b01,
7710 decoded17: u4 = 0b0000,
7711 decoded21: u1 = 0b1,
7712 ftype: Ftype,
7676 decoded10: u2 = 0b10,
7677 opcode: u5 = 0b11111,
7678 decoded17: u5 = 0b10000,
7679 sz: Sz,
7680 o2: u1 = 0b1,
77137681 decoded24: u5 = 0b11110,
7714 S: bool = false,
7715 decoded30: u1 = 0b0,
7716 M: u1 = 0b0,
7682 U: std.builtin.Signedness = .signed,
7683 decoded30: u2 = 0b01,
77177684 };
77187685
7719 /// C7.2.140 FNEG (scalar)
7720 pub const Fneg = packed struct {
7686 /// C7.2.394 USQADD
7687 pub const Usqadd = packed struct {
77217688 Rd: Register.Encoded,
77227689 Rn: Register.Encoded,
7723 decoded10: u5 = 0b10000,
7724 opc: u2 = 0b10,
7725 decoded17: u4 = 0b0000,
7726 decoded21: u1 = 0b1,
7727 ftype: Ftype,
7690 decoded10: u2 = 0b10,
7691 opcode: u5 = 0b00011,
7692 decoded17: u5 = 0b10000,
7693 size: Size,
77287694 decoded24: u5 = 0b11110,
7729 S: bool = false,
7730 decoded30: u1 = 0b0,
7731 M: u1 = 0b0,
7695 U: std.builtin.Signedness = .unsigned,
7696 decoded30: u2 = 0b01,
77327697 };
77337698
7734 /// C7.2.172 FSQRT (scalar)
7735 pub const Fsqrt = packed struct {
7699 /// C7.2.292 SQNEG
7700 pub const Sqneg = packed struct {
77367701 Rd: Register.Encoded,
77377702 Rn: Register.Encoded,
7738 decoded10: u5 = 0b10000,
7739 opc: u2 = 0b11,
7740 decoded17: u4 = 0b0000,
7741 decoded21: u1 = 0b1,
7742 ftype: Ftype,
7703 decoded10: u2 = 0b10,
7704 opcode: u5 = 0b00111,
7705 decoded17: u5 = 0b10000,
7706 size: Size,
77437707 decoded24: u5 = 0b11110,
7744 S: bool = false,
7745 decoded30: u1 = 0b0,
7746 M: u1 = 0b0,
7708 U: std.builtin.Signedness = .unsigned,
7709 decoded30: u2 = 0b01,
77477710 };
77487711
7749 /// C7.2.69 FCVT
7750 pub const Fcvt = packed struct {
7712 /// C7.2.30 CMGE (zero)
7713 pub const Cmge = packed struct {
77517714 Rd: Register.Encoded,
77527715 Rn: Register.Encoded,
7753 decoded10: u5 = 0b10000,
7754 opc: Ftype,
7755 decoded17: u4 = 0b0001,
7756 decoded21: u1 = 0b1,
7757 ftype: Ftype,
7716 decoded10: u2 = 0b10,
7717 opcode: u5 = 0b01000,
7718 decoded17: u5 = 0b10000,
7719 size: Size,
77587720 decoded24: u5 = 0b11110,
7759 S: bool = false,
7760 decoded30: u1 = 0b0,
7761 M: u1 = 0b0,
7721 U: std.builtin.Signedness = .unsigned,
7722 decoded30: u2 = 0b01,
77627723 };
77637724
7764 /// C7.2.162 FRINTN (scalar)
7765 pub const Frintn = packed struct {
7725 /// C7.2.35 CMLE (zero)
7726 pub const Cmle = packed struct {
77667727 Rd: Register.Encoded,
77677728 Rn: Register.Encoded,
7768 decoded10: u5 = 0b10000,
7769 rmode: Rmode = .n,
7770 decoded18: u3 = 0b001,
7771 decoded21: u1 = 0b1,
7772 ftype: Ftype,
7729 decoded10: u2 = 0b10,
7730 opcode: u5 = 0b01001,
7731 decoded17: u5 = 0b10000,
7732 size: Size,
77737733 decoded24: u5 = 0b11110,
7774 S: bool = false,
7775 decoded30: u1 = 0b0,
7776 M: u1 = 0b0,
7734 U: std.builtin.Signedness = .unsigned,
7735 decoded30: u2 = 0b01,
77777736 };
77787737
7779 /// C7.2.164 FRINTP (scalar)
7780 pub const Frintp = packed struct {
7738 /// C7.2.209 NEG (vector)
7739 pub const Neg = packed struct {
77817740 Rd: Register.Encoded,
77827741 Rn: Register.Encoded,
7783 decoded10: u5 = 0b10000,
7784 rmode: Rmode = .p,
7785 decoded18: u3 = 0b001,
7786 decoded21: u1 = 0b1,
7787 ftype: Ftype,
7742 decoded10: u2 = 0b10,
7743 opcode: u5 = 0b01011,
7744 decoded17: u5 = 0b10000,
7745 size: Size,
77887746 decoded24: u5 = 0b11110,
7789 S: bool = false,
7790 decoded30: u1 = 0b0,
7791 M: u1 = 0b0,
7747 U: std.builtin.Signedness = .unsigned,
7748 decoded30: u2 = 0b01,
77927749 };
77937750
7794 /// C7.2.160 FRINTM (scalar)
7795 pub const Frintm = packed struct {
7751 /// C7.2.309 SQXTUN
7752 pub const Sqxtun = packed struct {
77967753 Rd: Register.Encoded,
77977754 Rn: Register.Encoded,
7798 decoded10: u5 = 0b10000,
7799 rmode: Rmode = .m,
7800 decoded18: u3 = 0b001,
7801 decoded21: u1 = 0b1,
7802 ftype: Ftype,
7755 decoded10: u2 = 0b10,
7756 opcode: u5 = 0b10010,
7757 decoded17: u5 = 0b10000,
7758 size: Size,
78037759 decoded24: u5 = 0b11110,
7804 S: bool = false,
7805 decoded30: u1 = 0b0,
7806 M: u1 = 0b0,
7760 U: std.builtin.Signedness = .unsigned,
7761 decoded30: u2 = 0b01,
78077762 };
78087763
7809 /// C7.2.168 FRINTZ (scalar)
7810 pub const Frintz = packed struct {
7764 /// C7.2.381 UQXTN
7765 pub const Uqxtn = packed struct {
78117766 Rd: Register.Encoded,
78127767 Rn: Register.Encoded,
7813 decoded10: u5 = 0b10000,
7814 rmode: Rmode = .z,
7815 decoded18: u3 = 0b001,
7816 decoded21: u1 = 0b1,
7817 ftype: Ftype,
7768 decoded10: u2 = 0b10,
7769 opcode: u5 = 0b10100,
7770 decoded17: u5 = 0b10000,
7771 size: Size,
78187772 decoded24: u5 = 0b11110,
7819 S: bool = false,
7820 decoded30: u1 = 0b0,
7821 M: u1 = 0b0,
7773 U: std.builtin.Signedness = .unsigned,
7774 decoded30: u2 = 0b01,
78227775 };
78237776
7824 /// C7.2.156 FRINTA (scalar)
7825 pub const Frinta = packed struct {
7777 /// C7.2.88 FCVTXN
7778 pub const Fcvtxn = packed struct {
78267779 Rd: Register.Encoded,
78277780 Rn: Register.Encoded,
7828 decoded10: u5 = 0b10000,
7829 rmode: Rmode = .a,
7830 decoded18: u3 = 0b001,
7831 decoded21: u1 = 0b1,
7832 ftype: Ftype,
7781 decoded10: u2 = 0b10,
7782 opcode: u5 = 0b10110,
7783 decoded17: u5 = 0b10000,
7784 sz: Sz,
7785 o2: u1 = 0b0,
78337786 decoded24: u5 = 0b11110,
7834 S: bool = false,
7835 decoded30: u1 = 0b0,
7836 M: u1 = 0b0,
7787 U: std.builtin.Signedness = .unsigned,
7788 decoded30: u2 = 0b01,
78377789 };
78387790
7839 /// C7.2.166 FRINTX (scalar)
7840 pub const Frintx = packed struct {
7791 /// C7.2.82 FCVTNU (vector)
7792 pub const Fcvtnu = packed struct {
78417793 Rd: Register.Encoded,
78427794 Rn: Register.Encoded,
7843 decoded10: u5 = 0b10000,
7844 rmode: Rmode = .x,
7845 decoded18: u3 = 0b001,
7846 decoded21: u1 = 0b1,
7847 ftype: Ftype,
7795 decoded10: u2 = 0b10,
7796 opcode: u5 = 0b11010,
7797 decoded17: u5 = 0b10000,
7798 sz: Sz,
7799 o2: u1 = 0b0,
78487800 decoded24: u5 = 0b11110,
7849 S: bool = false,
7850 decoded30: u1 = 0b0,
7851 M: u1 = 0b0,
7801 U: std.builtin.Signedness = .unsigned,
7802 decoded30: u2 = 0b01,
78527803 };
78537804
7854 /// C7.2.158 FRINTI (scalar)
7855 pub const Frinti = packed struct {
7805 /// C7.2.77 FCVTMU (vector)
7806 pub const Fcvtmu = packed struct {
78567807 Rd: Register.Encoded,
78577808 Rn: Register.Encoded,
7858 decoded10: u5 = 0b10000,
7859 rmode: Rmode = .i,
7860 decoded18: u3 = 0b001,
7861 decoded21: u1 = 0b1,
7862 ftype: Ftype,
7809 decoded10: u2 = 0b10,
7810 opcode: u5 = 0b11011,
7811 decoded17: u5 = 0b10000,
7812 sz: Sz,
7813 o2: u1 = 0b0,
78637814 decoded24: u5 = 0b11110,
7864 S: bool = false,
7865 decoded30: u1 = 0b0,
7866 M: u1 = 0b0,
7815 U: std.builtin.Signedness = .unsigned,
7816 decoded30: u2 = 0b01,
78677817 };
78687818
7869 pub const Rmode = enum(u3) {
7870 /// to nearest with ties to even
7871 n = 0b000,
7872 /// toward plus infinity
7873 p = 0b001,
7874 /// toward minus infinity
7875 m = 0b010,
7876 /// toward zero
7877 z = 0b011,
7878 /// to nearest with ties to away
7879 a = 0b100,
7880 /// exact, using current rounding mode
7881 x = 0b110,
7882 /// using current rounding mode
7883 i = 0b111,
7884 _,
7819 /// C7.2.72 FCVTAU (vector)
7820 pub const Fcvtau = packed struct {
7821 Rd: Register.Encoded,
7822 Rn: Register.Encoded,
7823 decoded10: u2 = 0b10,
7824 opcode: u5 = 0b11100,
7825 decoded17: u5 = 0b10000,
7826 sz: Sz,
7827 o2: u1 = 0b0,
7828 decoded24: u5 = 0b11110,
7829 U: std.builtin.Signedness = .unsigned,
7830 decoded30: u2 = 0b01,
78857831 };
7886 };
7887
7888 /// Floating-point compare
7889 pub const FloatCompare = packed union {
7890 group: @This().Group,
7891 fcmp: Fcmp,
7892 fcmpe: Fcmpe,
78937832
7894 pub const Group = packed struct {
7895 opcode2: u5,
7833 /// C7.2.353 UCVTF (vector, integer)
7834 pub const Ucvtf = packed struct {
7835 Rd: Register.Encoded,
78967836 Rn: Register.Encoded,
7897 decoded10: u4 = 0b1000,
7898 op: u2,
7899 Rm: Register.Encoded,
7900 decoded21: u1 = 0b1,
7901 ptype: Ftype,
7837 decoded10: u2 = 0b10,
7838 opcode: u5 = 0b11101,
7839 decoded17: u5 = 0b10000,
7840 sz: Sz,
7841 o2: u1 = 0b0,
79027842 decoded24: u5 = 0b11110,
7903 S: bool,
7904 decoded30: u1 = 0b0,
7905 M: u1,
7843 U: std.builtin.Signedness = .unsigned,
7844 decoded30: u2 = 0b01,
79067845 };
79077846
7908 /// C7.2.66 FCMP
7909 pub const Fcmp = packed struct {
7910 decoded0: u3 = 0b000,
7911 opc0: Opc0,
7912 opc1: u1 = 0b0,
7847 /// C7.2.59 FCMGE (zero)
7848 pub const Fcmge = packed struct {
7849 Rd: Register.Encoded,
79137850 Rn: Register.Encoded,
7914 decoded10: u4 = 0b1000,
7915 op: u2 = 0b00,
7916 Rm: Register.Encoded,
7917 decoded21: u1 = 0b1,
7918 ftype: Ftype,
7851 decoded10: u2 = 0b10,
7852 opcode: u5 = 0b01100,
7853 decoded17: u5 = 0b10000,
7854 sz: Sz,
7855 o2: u1 = 0b1,
79197856 decoded24: u5 = 0b11110,
7920 S: bool = false,
7921 decoded30: u1 = 0b0,
7922 M: u1 = 0b0,
7857 U: std.builtin.Signedness = .unsigned,
7858 decoded30: u2 = 0b01,
79237859 };
79247860
7925 /// C7.2.67 FCMPE
7926 pub const Fcmpe = packed struct {
7927 decoded0: u3 = 0b000,
7928 opc0: Opc0,
7929 opc1: u1 = 0b1,
7861 /// C7.2.64 FCMLE (zero)
7862 pub const Fcmle = packed struct {
7863 Rd: Register.Encoded,
79307864 Rn: Register.Encoded,
7931 decoded10: u4 = 0b1000,
7932 op: u2 = 0b00,
7933 Rm: Register.Encoded,
7934 decoded21: u1 = 0b1,
7935 ftype: Ftype,
7865 decoded10: u2 = 0b10,
7866 opcode: u5 = 0b01101,
7867 decoded17: u5 = 0b10000,
7868 sz: Sz,
7869 o2: u1 = 0b1,
79367870 decoded24: u5 = 0b11110,
7937 S: bool = false,
7938 decoded30: u1 = 0b0,
7939 M: u1 = 0b0,
7871 U: std.builtin.Signedness = .unsigned,
7872 decoded30: u2 = 0b01,
79407873 };
79417874
7942 pub const Opc0 = enum(u1) {
7943 register = 0b00,
7944 zero = 0b01,
7875 /// C7.2.86 FCVTPU (vector)
7876 pub const Fcvtpu = packed struct {
7877 Rd: Register.Encoded,
7878 Rn: Register.Encoded,
7879 decoded10: u2 = 0b10,
7880 opcode: u5 = 0b11010,
7881 decoded17: u5 = 0b10000,
7882 sz: Sz,
7883 o2: u1 = 0b1,
7884 decoded24: u5 = 0b11110,
7885 U: std.builtin.Signedness = .unsigned,
7886 decoded30: u2 = 0b01,
79457887 };
7946 };
7947
7948 /// Floating-point immediate
7949 pub const FloatImmediate = packed union {
7950 group: @This().Group,
7951 fmov: Fmov,
79527888
7953 pub const Group = packed struct {
7889 /// C7.2.94 FCVTZU (vector, integer)
7890 pub const Fcvtzu = packed struct {
79547891 Rd: Register.Encoded,
7955 imm5: u5,
7956 decoded10: u3 = 0b100,
7957 imm8: u8,
7958 decoded21: u1 = 0b1,
7959 ptype: Ftype,
7892 Rn: Register.Encoded,
7893 decoded10: u2 = 0b10,
7894 opcode: u5 = 0b11011,
7895 decoded17: u5 = 0b10000,
7896 sz: Sz,
7897 o2: u1 = 0b1,
79607898 decoded24: u5 = 0b11110,
7961 S: bool,
7962 decoded30: u1 = 0b0,
7963 M: u1,
7899 U: std.builtin.Signedness = .unsigned,
7900 decoded30: u2 = 0b01,
79647901 };
79657902
7966 /// C7.2.132 FMOV (scalar, immediate)
7967 pub const Fmov = packed struct {
7903 /// C7.2.169 FRSQRTE
7904 pub const Frsqrte = packed struct {
79687905 Rd: Register.Encoded,
7969 imm5: u5 = 0b00000,
7970 decoded10: u3 = 0b100,
7971 imm8: u8,
7972 decoded21: u1 = 0b1,
7973 ftype: Ftype,
7906 Rn: Register.Encoded,
7907 decoded10: u2 = 0b10,
7908 opcode: u5 = 0b11101,
7909 decoded17: u5 = 0b10000,
7910 sz: Sz,
7911 o2: u1 = 0b1,
79747912 decoded24: u5 = 0b11110,
7975 S: bool = false,
7976 decoded30: u1 = 0b0,
7977 M: u1 = 0b0,
7913 U: std.builtin.Signedness = .unsigned,
7914 decoded30: u2 = 0b01,
79787915 };
79797916 };
79807917
7981 /// Floating-point data-processing (2 source)
7982 pub const FloatDataProcessingTwoSource = packed union {
7918 /// Advanced SIMD scalar pairwise
7919 pub const SimdScalarPairwise = packed union {
79837920 group: @This().Group,
7984 fmul: Fmul,
7985 fdiv: Fdiv,
7986 fadd: Fadd,
7987 fsub: Fsub,
7988 fmax: Fmax,
7989 fmin: Fmin,
7990 fmaxnm: Fmaxnm,
7991 fminnm: Fminnm,
7992 fnmul: Fnmul,
7921 addp: Addp,
79937922
79947923 pub const Group = packed struct {
79957924 Rd: Register.Encoded,
79967925 Rn: Register.Encoded,
79977926 decoded10: u2 = 0b10,
7998 opcode: Opcode,
7999 Rm: Register.Encoded,
8000 decoded21: u1 = 0b1,
8001 ptype: Ftype,
7927 opcode: u5,
7928 decoded17: u5 = 0b11000,
7929 size: Size,
80027930 decoded24: u5 = 0b11110,
8003 S: bool,
8004 decoded30: u1 = 0b0,
8005 M: u1,
7931 U: std.builtin.Signedness,
7932 decoded30: u2 = 0b01,
80067933 };
80077934
8008 /// C7.2.136 FMUL (scalar)
8009 pub const Fmul = packed struct {
7935 /// C7.2.4 ADDP (scalar)
7936 pub const Addp = packed struct {
80107937 Rd: Register.Encoded,
80117938 Rn: Register.Encoded,
80127939 decoded10: u2 = 0b10,
8013 opcode: Opcode = .fmul,
8014 Rm: Register.Encoded,
8015 decoded21: u1 = 0b1,
8016 ftype: Ftype,
7940 opcode: u5 = 0b11011,
7941 decoded17: u5 = 0b11000,
7942 size: Size,
80177943 decoded24: u5 = 0b11110,
8018 S: bool = false,
8019 decoded30: u1 = 0b0,
8020 M: u1 = 0b0,
7944 U: std.builtin.Signedness = .signed,
7945 decoded30: u2 = 0b01,
80217946 };
7947 };
80227948
8023 /// C7.2.98 FDIV (scalar)
8024 pub const Fdiv = packed struct {
7949 /// Advanced SIMD copy
7950 pub const SimdCopy = packed union {
7951 group: @This().Group,
7952 dup: Dup,
7953 smov: Smov,
7954 umov: Umov,
7955 ins: Ins,
7956
7957 pub const Group = packed struct {
80257958 Rd: Register.Encoded,
80267959 Rn: Register.Encoded,
8027 decoded10: u2 = 0b10,
8028 opcode: Opcode = .fdiv,
8029 Rm: Register.Encoded,
8030 decoded21: u1 = 0b1,
8031 ftype: Ftype,
8032 decoded24: u5 = 0b11110,
8033 S: bool = false,
8034 decoded30: u1 = 0b0,
8035 M: u1 = 0b0,
7960 decoded10: u1 = 0b1,
7961 imm4: u4,
7962 decoded15: u1 = 0b0,
7963 imm5: u5,
7964 decoded21: u8 = 0b01110000,
7965 op: u1,
7966 Q: u1,
7967 decoded31: u1 = 0b0,
80367968 };
80377969
8038 /// C7.2.50 FADD (scalar)
8039 pub const Fadd = packed struct {
7970 /// C7.2.39 DUP (element)
7971 /// C7.2.40 DUP (general)
7972 pub const Dup = packed struct {
80407973 Rd: Register.Encoded,
80417974 Rn: Register.Encoded,
8042 decoded10: u2 = 0b10,
8043 opcode: Opcode = .fadd,
8044 Rm: Register.Encoded,
8045 decoded21: u1 = 0b1,
8046 ftype: Ftype,
8047 decoded24: u5 = 0b11110,
8048 S: bool = false,
8049 decoded30: u1 = 0b0,
8050 M: u1 = 0b0,
7975 decoded10: u1 = 0b1,
7976 imm4: Imm4,
7977 decoded15: u1 = 0b0,
7978 imm5: u5,
7979 decoded21: u8 = 0b01110000,
7980 op: u1 = 0b0,
7981 Q: Q,
7982 decoded31: u1 = 0b0,
7983
7984 pub const Imm4 = enum(u4) {
7985 element = 0b0000,
7986 general = 0b0001,
7987 _,
7988 };
80517989 };
80527990
8053 /// C7.2.174 FSUB (scalar)
8054 pub const Fsub = packed struct {
7991 /// C7.2.279 SMOV
7992 pub const Smov = packed struct {
80557993 Rd: Register.Encoded,
80567994 Rn: Register.Encoded,
8057 decoded10: u2 = 0b10,
8058 opcode: Opcode = .fsub,
8059 Rm: Register.Encoded,
8060 decoded21: u1 = 0b1,
8061 ftype: Ftype,
8062 decoded24: u5 = 0b11110,
8063 S: bool = false,
8064 decoded30: u1 = 0b0,
8065 M: u1 = 0b0,
7995 decoded10: u1 = 0b1,
7996 imm4: u4 = 0b0101,
7997 decoded15: u1 = 0b0,
7998 imm5: u5,
7999 decoded21: u8 = 0b01110000,
8000 op: u1 = 0b0,
8001 Q: Register.IntegerSize,
8002 decoded31: u1 = 0b0,
80668003 };
80678004
8068 /// C7.2.102 FMAX (scalar)
8069 pub const Fmax = packed struct {
8005 /// C7.2.371 UMOV
8006 pub const Umov = packed struct {
80708007 Rd: Register.Encoded,
80718008 Rn: Register.Encoded,
8072 decoded10: u2 = 0b10,
8073 opcode: Opcode = .fmax,
8074 Rm: Register.Encoded,
8075 decoded21: u1 = 0b1,
8076 ftype: Ftype,
8077 decoded24: u5 = 0b11110,
8078 S: bool = false,
8079 decoded30: u1 = 0b0,
8080 M: u1 = 0b0,
8009 decoded10: u1 = 0b1,
8010 imm4: u4 = 0b0111,
8011 decoded15: u1 = 0b0,
8012 imm5: u5,
8013 decoded21: u8 = 0b01110000,
8014 op: u1 = 0b0,
8015 Q: Register.IntegerSize,
8016 decoded31: u1 = 0b0,
80818017 };
80828018
8083 /// C7.2.112 FMIN (scalar)
8084 pub const Fmin = packed struct {
8019 /// C7.2.175 INS (element)
8020 /// C7.2.176 INS (general)
8021 pub const Ins = packed struct {
80858022 Rd: Register.Encoded,
80868023 Rn: Register.Encoded,
8087 decoded10: u2 = 0b10,
8088 opcode: Opcode = .fmin,
8089 Rm: Register.Encoded,
8090 decoded21: u1 = 0b1,
8091 ftype: Ftype,
8092 decoded24: u5 = 0b11110,
8093 S: bool = false,
8094 decoded30: u1 = 0b0,
8095 M: u1 = 0b0,
8024 decoded10: u1 = 0b1,
8025 imm4: Imm4,
8026 decoded15: u1 = 0b0,
8027 imm5: u5,
8028 decoded21: u8 = 0b01110000,
8029 op: Op,
8030 Q: u1 = 0b1,
8031 decoded31: u1 = 0b0,
8032
8033 pub const Imm4 = packed union {
8034 general: General,
8035 element: u4,
8036
8037 pub const General = enum(u4) {
8038 general = 0b0011,
8039 _,
8040 };
8041 };
8042
8043 pub const Op = enum(u1) {
8044 general = 0b0,
8045 element = 0b1,
8046 };
80968047 };
80978048
8098 /// C7.2.104 FMAXNM (scalar)
8099 pub const Fmaxnm = packed struct {
8049 pub const Decoded = union(enum) {
8050 unallocated,
8051 dup: Dup,
8052 smov: Smov,
8053 umov: Umov,
8054 ins: Ins,
8055 };
8056 pub fn decode(inst: @This()) @This().Decoded {
8057 return switch (inst.group.op) {
8058 0b0 => switch (inst.group.imm4) {
8059 0b0000, 0b0001 => .{ .dup = inst.dup },
8060 else => .unallocated,
8061 0b0101 => switch (@ctz(inst.group.imm5)) {
8062 0, 1 => .{ .smov = inst.smov },
8063 2 => switch (inst.group.Q) {
8064 0b1 => .{ .smov = inst.smov },
8065 0b0 => .unallocated,
8066 },
8067 else => .unallocated,
8068 },
8069 0b0111 => switch (@ctz(inst.group.imm5)) {
8070 0, 1, 2 => switch (inst.group.Q) {
8071 0b0 => .{ .umov = inst.umov },
8072 0b1 => .unallocated,
8073 },
8074 3 => switch (inst.group.Q) {
8075 0b1 => .{ .umov = inst.umov },
8076 0b0 => .unallocated,
8077 },
8078 else => .unallocated,
8079 },
8080 },
8081 0b1 => switch (inst.group.Q) {
8082 0b0 => .unallocated,
8083 0b1 => .{ .ins = inst.ins },
8084 },
8085 };
8086 }
8087 };
8088
8089 /// Advanced SIMD two-register miscellaneous (FP16)
8090 pub const SimdTwoRegisterMiscellaneousFp16 = packed union {
8091 group: @This().Group,
8092 frintn: Frintn,
8093 frintm: Frintm,
8094 fcvtns: Fcvtns,
8095 fcvtms: Fcvtms,
8096 fcvtas: Fcvtas,
8097 scvtf: Scvtf,
8098 fcmgt: Fcmgt,
8099 fcmeq: Fcmeq,
8100 fcmlt: Fcmlt,
8101 fabs: Fabs,
8102 frintp: Frintp,
8103 frintz: Frintz,
8104 fcvtps: Fcvtps,
8105 fcvtzs: Fcvtzs,
8106 frecpe: Frecpe,
8107 frinta: Frinta,
8108 frintx: Frintx,
8109 fcvtnu: Fcvtnu,
8110 fcvtmu: Fcvtmu,
8111 fcvtau: Fcvtau,
8112 ucvtf: Ucvtf,
8113 fcmge: Fcmge,
8114 fcmle: Fcmle,
8115 fneg: Fneg,
8116 frinti: Frinti,
8117 fcvtpu: Fcvtpu,
8118 fcvtzu: Fcvtzu,
8119 frsqrte: Frsqrte,
8120 fsqrt: Fsqrt,
8121
8122 pub const Group = packed struct {
81008123 Rd: Register.Encoded,
81018124 Rn: Register.Encoded,
81028125 decoded10: u2 = 0b10,
8103 opcode: Opcode = .fmaxnm,
8104 Rm: Register.Encoded,
8105 decoded21: u1 = 0b1,
8106 ftype: Ftype,
8107 decoded24: u5 = 0b11110,
8108 S: bool = false,
8109 decoded30: u1 = 0b0,
8110 M: u1 = 0b0,
8126 opcode: u5,
8127 decoded17: u6 = 0b111100,
8128 a: u1,
8129 decoded24: u5 = 0b01110,
8130 U: std.builtin.Signedness,
8131 Q: Q,
8132 decoded31: u1 = 0b0,
81118133 };
81128134
8113 /// C7.2.114 FMINNM (scalar)
8114 pub const Fminnm = packed struct {
8135 /// C7.2.161 FRINTN (vector)
8136 pub const Frintn = packed struct {
81158137 Rd: Register.Encoded,
81168138 Rn: Register.Encoded,
81178139 decoded10: u2 = 0b10,
8118 opcode: Opcode = .fminnm,
8119 Rm: Register.Encoded,
8120 decoded21: u1 = 0b1,
8121 ftype: Ftype,
8122 decoded24: u5 = 0b11110,
8123 S: bool = false,
8124 decoded30: u1 = 0b0,
8125 M: u1 = 0b0,
8140 opcode: u5 = 0b11000,
8141 decoded17: u6 = 0b111100,
8142 o2: u1 = 0b0,
8143 decoded24: u5 = 0b01110,
8144 U: std.builtin.Signedness = .signed,
8145 Q: Q,
8146 decoded31: u1 = 0b0,
81268147 };
81278148
8128 /// C7.2.143 FNMUL (scalar)
8129 pub const Fnmul = packed struct {
8149 /// C7.2.159 FRINTM (vector)
8150 pub const Frintm = packed struct {
81308151 Rd: Register.Encoded,
81318152 Rn: Register.Encoded,
81328153 decoded10: u2 = 0b10,
8133 opcode: Opcode = .fnmul,
8134 Rm: Register.Encoded,
8135 decoded21: u1 = 0b1,
8136 ftype: Ftype,
8137 decoded24: u5 = 0b11110,
8138 S: bool = false,
8139 decoded30: u1 = 0b0,
8140 M: u1 = 0b0,
8141 };
8142
8143 pub const Opcode = enum(u4) {
8144 fmul = 0b0000,
8145 fdiv = 0b0001,
8146 fadd = 0b0010,
8147 fsub = 0b0011,
8148 fmax = 0b0100,
8149 fmin = 0b0101,
8150 fmaxnm = 0b0110,
8151 fminnm = 0b0111,
8152 fnmul = 0b1000,
8153 _,
8154 opcode: u5 = 0b11001,
8155 decoded17: u6 = 0b111100,
8156 o2: u1 = 0b0,
8157 decoded24: u5 = 0b01110,
8158 U: std.builtin.Signedness = .signed,
8159 Q: Q,
8160 decoded31: u1 = 0b0,
81548161 };
8155 };
8156
8157 /// Floating-point data-processing (3 source)
8158 pub const FloatDataProcessingThreeSource = packed union {
8159 group: @This().Group,
8160 fmadd: Fmadd,
8161 fmsub: Fmsub,
8162 fnmadd: Fnmadd,
8163 fnmsub: Fnmsub,
81648162
8165 pub const Group = packed struct {
8163 /// C7.2.80 FCVTNS (vector)
8164 pub const Fcvtns = packed struct {
81668165 Rd: Register.Encoded,
81678166 Rn: Register.Encoded,
8168 Ra: Register.Encoded,
8169 o0: AddSubtractOp,
8170 Rm: Register.Encoded,
8171 o1: u1,
8172 ptype: Ftype,
8173 decoded24: u5 = 0b11111,
8174 S: bool,
8175 decoded30: u1 = 0b0,
8176 M: u1,
8167 decoded10: u2 = 0b10,
8168 opcode: u5 = 0b11010,
8169 decoded17: u6 = 0b111100,
8170 o2: u1 = 0b0,
8171 decoded24: u5 = 0b01110,
8172 U: std.builtin.Signedness = .signed,
8173 Q: Q,
8174 decoded31: u1 = 0b0,
81778175 };
81788176
8179 /// C7.2.100 FMADD
8180 pub const Fmadd = packed struct {
8177 /// C7.2.75 FCVTMS (vector)
8178 pub const Fcvtms = packed struct {
81818179 Rd: Register.Encoded,
81828180 Rn: Register.Encoded,
8183 Ra: Register.Encoded,
8184 o0: AddSubtractOp = .add,
8185 Rm: Register.Encoded,
8186 o1: O1 = .fm,
8187 ftype: Ftype,
8188 decoded24: u5 = 0b11111,
8189 S: bool = false,
8190 decoded30: u1 = 0b0,
8191 M: u1 = 0b0,
8181 decoded10: u2 = 0b10,
8182 opcode: u5 = 0b11011,
8183 decoded17: u6 = 0b111100,
8184 o2: u1 = 0b0,
8185 decoded24: u5 = 0b01110,
8186 U: std.builtin.Signedness = .signed,
8187 Q: Q,
8188 decoded31: u1 = 0b0,
81928189 };
81938190
8194 /// C7.2.133 FMSUB
8195 pub const Fmsub = packed struct {
8191 /// C7.2.70 FCVTAS (vector)
8192 pub const Fcvtas = packed struct {
81968193 Rd: Register.Encoded,
81978194 Rn: Register.Encoded,
8198 Ra: Register.Encoded,
8199 o0: AddSubtractOp = .sub,
8195 decoded10: u2 = 0b10,
8196 opcode: u5 = 0b11100,
8197 decoded17: u6 = 0b111100,
8198 o2: u1 = 0b0,
8199 decoded24: u5 = 0b01110,
8200 U: std.builtin.Signedness = .signed,
8201 Q: Q,
8202 decoded31: u1 = 0b0,
8203 };
8204
8205 /// C7.2.234 SCVTF (vector, integer)
8206 pub const Scvtf = packed struct {
8207 Rd: Register.Encoded,
8208 Rn: Register.Encoded,
8209 decoded10: u2 = 0b10,
8210 opcode: u5 = 0b11101,
8211 decoded17: u6 = 0b111100,
8212 o2: u1 = 0b0,
8213 decoded24: u5 = 0b01110,
8214 U: std.builtin.Signedness = .signed,
8215 Q: Q,
8216 decoded31: u1 = 0b0,
8217 };
8218
8219 /// C7.2.61 FCMGT (zero)
8220 pub const Fcmgt = packed struct {
8221 Rd: Register.Encoded,
8222 Rn: Register.Encoded,
8223 decoded10: u2 = 0b10,
8224 opcode: u5 = 0b01100,
8225 decoded17: u6 = 0b111100,
8226 o2: u1 = 0b1,
8227 decoded24: u5 = 0b01110,
8228 U: std.builtin.Signedness = .signed,
8229 Q: Q,
8230 decoded31: u1 = 0b0,
8231 };
8232
8233 /// C7.2.57 FCMEQ (zero)
8234 pub const Fcmeq = packed struct {
8235 Rd: Register.Encoded,
8236 Rn: Register.Encoded,
8237 decoded10: u2 = 0b10,
8238 opcode: u5 = 0b01101,
8239 decoded17: u6 = 0b111100,
8240 o2: u1 = 0b1,
8241 decoded24: u5 = 0b01110,
8242 U: std.builtin.Signedness = .signed,
8243 Q: Q,
8244 decoded31: u1 = 0b0,
8245 };
8246
8247 /// C7.2.65 FCMLT (zero)
8248 pub const Fcmlt = packed struct {
8249 Rd: Register.Encoded,
8250 Rn: Register.Encoded,
8251 decoded10: u2 = 0b10,
8252 opcode: u5 = 0b01110,
8253 decoded17: u6 = 0b111100,
8254 o2: u1 = 0b1,
8255 decoded24: u5 = 0b01110,
8256 U: std.builtin.Signedness = .signed,
8257 Q: Q,
8258 decoded31: u1 = 0b0,
8259 };
8260
8261 /// C7.2.45 FABS (vector)
8262 pub const Fabs = packed struct {
8263 Rd: Register.Encoded,
8264 Rn: Register.Encoded,
8265 decoded10: u2 = 0b10,
8266 opcode: u5 = 0b01111,
8267 decoded17: u6 = 0b111100,
8268 o2: u1 = 0b1,
8269 decoded24: u5 = 0b01110,
8270 U: std.builtin.Signedness = .signed,
8271 Q: Q,
8272 decoded31: u1 = 0b0,
8273 };
8274
8275 /// C7.2.163 FRINTP (vector)
8276 pub const Frintp = packed struct {
8277 Rd: Register.Encoded,
8278 Rn: Register.Encoded,
8279 decoded10: u2 = 0b10,
8280 opcode: u5 = 0b11000,
8281 decoded17: u6 = 0b111100,
8282 o2: u1 = 0b1,
8283 decoded24: u5 = 0b01110,
8284 U: std.builtin.Signedness = .signed,
8285 Q: Q,
8286 decoded31: u1 = 0b0,
8287 };
8288
8289 /// C7.2.167 FRINTZ (vector)
8290 pub const Frintz = packed struct {
8291 Rd: Register.Encoded,
8292 Rn: Register.Encoded,
8293 decoded10: u2 = 0b10,
8294 opcode: u5 = 0b11001,
8295 decoded17: u6 = 0b111100,
8296 o2: u1 = 0b1,
8297 decoded24: u5 = 0b01110,
8298 U: std.builtin.Signedness = .signed,
8299 Q: Q,
8300 decoded31: u1 = 0b0,
8301 };
8302
8303 /// C7.2.84 FCVTPS (vector)
8304 pub const Fcvtps = packed struct {
8305 Rd: Register.Encoded,
8306 Rn: Register.Encoded,
8307 decoded10: u2 = 0b10,
8308 opcode: u5 = 0b11010,
8309 decoded17: u6 = 0b111100,
8310 o2: u1 = 0b1,
8311 decoded24: u5 = 0b01110,
8312 U: std.builtin.Signedness = .signed,
8313 Q: Q,
8314 decoded31: u1 = 0b0,
8315 };
8316
8317 /// C7.2.90 FCVTZS (vector, integer)
8318 pub const Fcvtzs = packed struct {
8319 Rd: Register.Encoded,
8320 Rn: Register.Encoded,
8321 decoded10: u2 = 0b10,
8322 opcode: u5 = 0b11011,
8323 decoded17: u6 = 0b111100,
8324 o2: u1 = 0b1,
8325 decoded24: u5 = 0b01110,
8326 U: std.builtin.Signedness = .signed,
8327 Q: Q,
8328 decoded31: u1 = 0b0,
8329 };
8330
8331 /// C7.2.144 FRECPE
8332 pub const Frecpe = packed struct {
8333 Rd: Register.Encoded,
8334 Rn: Register.Encoded,
8335 decoded10: u2 = 0b10,
8336 opcode: u5 = 0b11101,
8337 decoded17: u6 = 0b111100,
8338 o2: u1 = 0b1,
8339 decoded24: u5 = 0b01110,
8340 U: std.builtin.Signedness = .signed,
8341 Q: Q,
8342 decoded31: u1 = 0b0,
8343 };
8344
8345 /// C7.2.155 FRINTA (vector)
8346 pub const Frinta = packed struct {
8347 Rd: Register.Encoded,
8348 Rn: Register.Encoded,
8349 decoded10: u2 = 0b10,
8350 opcode: u5 = 0b11000,
8351 decoded17: u6 = 0b111100,
8352 o2: u1 = 0b0,
8353 decoded24: u5 = 0b01110,
8354 U: std.builtin.Signedness = .unsigned,
8355 Q: Q,
8356 decoded31: u1 = 0b0,
8357 };
8358
8359 /// C7.2.159 FRINTX (vector)
8360 pub const Frintx = packed struct {
8361 Rd: Register.Encoded,
8362 Rn: Register.Encoded,
8363 decoded10: u2 = 0b10,
8364 opcode: u5 = 0b11001,
8365 decoded17: u6 = 0b111100,
8366 o2: u1 = 0b0,
8367 decoded24: u5 = 0b01110,
8368 U: std.builtin.Signedness = .unsigned,
8369 Q: Q,
8370 decoded31: u1 = 0b0,
8371 };
8372
8373 /// C7.2.82 FCVTNU (vector)
8374 pub const Fcvtnu = packed struct {
8375 Rd: Register.Encoded,
8376 Rn: Register.Encoded,
8377 decoded10: u2 = 0b10,
8378 opcode: u5 = 0b11010,
8379 decoded17: u6 = 0b111100,
8380 o2: u1 = 0b0,
8381 decoded24: u5 = 0b01110,
8382 U: std.builtin.Signedness = .unsigned,
8383 Q: Q,
8384 decoded31: u1 = 0b0,
8385 };
8386
8387 /// C7.2.77 FCVTMU (vector)
8388 pub const Fcvtmu = packed struct {
8389 Rd: Register.Encoded,
8390 Rn: Register.Encoded,
8391 decoded10: u2 = 0b10,
8392 opcode: u5 = 0b11011,
8393 decoded17: u6 = 0b111100,
8394 o2: u1 = 0b0,
8395 decoded24: u5 = 0b01110,
8396 U: std.builtin.Signedness = .unsigned,
8397 Q: Q,
8398 decoded31: u1 = 0b0,
8399 };
8400
8401 /// C7.2.72 FCVTAU (vector)
8402 pub const Fcvtau = packed struct {
8403 Rd: Register.Encoded,
8404 Rn: Register.Encoded,
8405 decoded10: u2 = 0b10,
8406 opcode: u5 = 0b11100,
8407 decoded17: u6 = 0b111100,
8408 o2: u1 = 0b0,
8409 decoded24: u5 = 0b01110,
8410 U: std.builtin.Signedness = .unsigned,
8411 Q: Q,
8412 decoded31: u1 = 0b0,
8413 };
8414
8415 /// C7.2.353 UCVTF (vector, integer)
8416 pub const Ucvtf = packed struct {
8417 Rd: Register.Encoded,
8418 Rn: Register.Encoded,
8419 decoded10: u2 = 0b10,
8420 opcode: u5 = 0b11101,
8421 decoded17: u6 = 0b111100,
8422 o2: u1 = 0b0,
8423 decoded24: u5 = 0b01110,
8424 U: std.builtin.Signedness = .unsigned,
8425 Q: Q,
8426 decoded31: u1 = 0b0,
8427 };
8428
8429 /// C7.2.59 FCMGE (zero)
8430 pub const Fcmge = packed struct {
8431 Rd: Register.Encoded,
8432 Rn: Register.Encoded,
8433 decoded10: u2 = 0b10,
8434 opcode: u5 = 0b01100,
8435 decoded17: u6 = 0b111100,
8436 o2: u1 = 0b1,
8437 decoded24: u5 = 0b01110,
8438 U: std.builtin.Signedness = .unsigned,
8439 Q: Q,
8440 decoded31: u1 = 0b0,
8441 };
8442
8443 /// C7.2.64 FCMLE (zero)
8444 pub const Fcmle = packed struct {
8445 Rd: Register.Encoded,
8446 Rn: Register.Encoded,
8447 decoded10: u2 = 0b10,
8448 opcode: u5 = 0b01101,
8449 decoded17: u6 = 0b111100,
8450 o2: u1 = 0b1,
8451 decoded24: u5 = 0b01110,
8452 U: std.builtin.Signedness = .unsigned,
8453 Q: Q,
8454 decoded31: u1 = 0b0,
8455 };
8456
8457 /// C7.2.139 FNEG (vector)
8458 pub const Fneg = packed struct {
8459 Rd: Register.Encoded,
8460 Rn: Register.Encoded,
8461 decoded10: u2 = 0b10,
8462 opcode: u5 = 0b01111,
8463 decoded17: u6 = 0b111100,
8464 o2: u1 = 0b1,
8465 decoded24: u5 = 0b01110,
8466 U: std.builtin.Signedness = .unsigned,
8467 Q: Q,
8468 decoded31: u1 = 0b0,
8469 };
8470
8471 /// C7.2.157 FRINTI (vector)
8472 pub const Frinti = packed struct {
8473 Rd: Register.Encoded,
8474 Rn: Register.Encoded,
8475 decoded10: u2 = 0b10,
8476 opcode: u5 = 0b11001,
8477 decoded17: u6 = 0b111100,
8478 o2: u1 = 0b1,
8479 decoded24: u5 = 0b01110,
8480 U: std.builtin.Signedness = .unsigned,
8481 Q: Q,
8482 decoded31: u1 = 0b0,
8483 };
8484
8485 /// C7.2.86 FCVTPU (vector)
8486 pub const Fcvtpu = packed struct {
8487 Rd: Register.Encoded,
8488 Rn: Register.Encoded,
8489 decoded10: u2 = 0b10,
8490 opcode: u5 = 0b11010,
8491 decoded17: u6 = 0b111100,
8492 o2: u1 = 0b1,
8493 decoded24: u5 = 0b01110,
8494 U: std.builtin.Signedness = .unsigned,
8495 Q: Q,
8496 decoded31: u1 = 0b0,
8497 };
8498
8499 /// C7.2.94 FCVTZU (vector, integer)
8500 pub const Fcvtzu = packed struct {
8501 Rd: Register.Encoded,
8502 Rn: Register.Encoded,
8503 decoded10: u2 = 0b10,
8504 opcode: u5 = 0b11011,
8505 decoded17: u6 = 0b111100,
8506 o2: u1 = 0b1,
8507 decoded24: u5 = 0b01110,
8508 U: std.builtin.Signedness = .unsigned,
8509 Q: Q,
8510 decoded31: u1 = 0b0,
8511 };
8512
8513 /// C7.2.169 FRSQRTE
8514 pub const Frsqrte = packed struct {
8515 Rd: Register.Encoded,
8516 Rn: Register.Encoded,
8517 decoded10: u2 = 0b10,
8518 opcode: u5 = 0b11101,
8519 decoded17: u6 = 0b111100,
8520 o2: u1 = 0b1,
8521 decoded24: u5 = 0b01110,
8522 U: std.builtin.Signedness = .unsigned,
8523 Q: Q,
8524 decoded31: u1 = 0b0,
8525 };
8526
8527 /// C7.2.171 FSQRT
8528 pub const Fsqrt = packed struct {
8529 Rd: Register.Encoded,
8530 Rn: Register.Encoded,
8531 decoded10: u2 = 0b10,
8532 opcode: u5 = 0b11111,
8533 decoded17: u6 = 0b111100,
8534 o2: u1 = 0b1,
8535 decoded24: u5 = 0b01110,
8536 U: std.builtin.Signedness = .unsigned,
8537 Q: Q,
8538 decoded31: u1 = 0b0,
8539 };
8540 };
8541
8542 /// Advanced SIMD two-register miscellaneous
8543 pub const SimdTwoRegisterMiscellaneous = packed union {
8544 group: @This().Group,
8545 suqadd: Suqadd,
8546 cnt: Cnt,
8547 sqabs: Sqabs,
8548 cmgt: Cmgt,
8549 cmeq: Cmeq,
8550 cmlt: Cmlt,
8551 abs: Abs,
8552 sqxtn: Sqxtn,
8553 frintn: Frintn,
8554 frintm: Frintm,
8555 fcvtns: Fcvtns,
8556 fcvtms: Fcvtms,
8557 fcvtas: Fcvtas,
8558 scvtf: Scvtf,
8559 fcmgt: Fcmgt,
8560 fcmeq: Fcmeq,
8561 fcmlt: Fcmlt,
8562 fabs: Fabs,
8563 frintp: Frintp,
8564 frintz: Frintz,
8565 fcvtps: Fcvtps,
8566 fcvtzs: Fcvtzs,
8567 frecpe: Frecpe,
8568 usqadd: Usqadd,
8569 sqneg: Sqneg,
8570 cmge: Cmge,
8571 cmle: Cmle,
8572 neg: Neg,
8573 sqxtun: Sqxtun,
8574 uqxtn: Uqxtn,
8575 fcvtxn: Fcvtxn,
8576 frinta: Frinta,
8577 frintx: Frintx,
8578 fcvtnu: Fcvtnu,
8579 fcvtmu: Fcvtmu,
8580 fcvtau: Fcvtau,
8581 ucvtf: Ucvtf,
8582 not: Not,
8583 fcmge: Fcmge,
8584 fcmle: Fcmle,
8585 fneg: Fneg,
8586 frinti: Frinti,
8587 fcvtpu: Fcvtpu,
8588 fcvtzu: Fcvtzu,
8589 frsqrte: Frsqrte,
8590 fsqrt: Fsqrt,
8591
8592 pub const Group = packed struct {
8593 Rd: Register.Encoded,
8594 Rn: Register.Encoded,
8595 decoded10: u2 = 0b10,
8596 opcode: u5,
8597 decoded17: u5 = 0b10000,
8598 size: Size,
8599 decoded24: u5 = 0b01110,
8600 U: std.builtin.Signedness,
8601 Q: Q,
8602 decoded31: u1 = 0b0,
8603 };
8604
8605 /// C7.2.337 SUQADD
8606 pub const Suqadd = packed struct {
8607 Rd: Register.Encoded,
8608 Rn: Register.Encoded,
8609 decoded10: u2 = 0b10,
8610 opcode: u5 = 0b00011,
8611 decoded17: u5 = 0b10000,
8612 size: Size,
8613 decoded24: u5 = 0b01110,
8614 U: std.builtin.Signedness = .signed,
8615 Q: Q,
8616 decoded31: u1 = 0b0,
8617 };
8618
8619 /// C7.2.38 CNT
8620 pub const Cnt = packed struct {
8621 Rd: Register.Encoded,
8622 Rn: Register.Encoded,
8623 decoded10: u2 = 0b10,
8624 opcode: u5 = 0b00101,
8625 decoded17: u5 = 0b10000,
8626 size: Size,
8627 decoded24: u5 = 0b01110,
8628 U: std.builtin.Signedness = .signed,
8629 Q: Q,
8630 decoded31: u1 = 0b0,
8631 };
8632
8633 /// C7.2.282 SQABS
8634 pub const Sqabs = packed struct {
8635 Rd: Register.Encoded,
8636 Rn: Register.Encoded,
8637 decoded10: u2 = 0b10,
8638 opcode: u5 = 0b00111,
8639 decoded17: u5 = 0b10000,
8640 size: Size,
8641 decoded24: u5 = 0b01110,
8642 U: std.builtin.Signedness = .signed,
8643 Q: Q,
8644 decoded31: u1 = 0b0,
8645 };
8646
8647 /// C7.2.32 CMGT (zero)
8648 pub const Cmgt = packed struct {
8649 Rd: Register.Encoded,
8650 Rn: Register.Encoded,
8651 decoded10: u2 = 0b10,
8652 opcode: u5 = 0b01000,
8653 decoded17: u5 = 0b10000,
8654 size: Size,
8655 decoded24: u5 = 0b01110,
8656 U: std.builtin.Signedness = .signed,
8657 Q: Q,
8658 decoded31: u1 = 0b0,
8659 };
8660
8661 /// C7.2.28 CMEQ (zero)
8662 pub const Cmeq = packed struct {
8663 Rd: Register.Encoded,
8664 Rn: Register.Encoded,
8665 decoded10: u2 = 0b10,
8666 opcode: u5 = 0b01001,
8667 decoded17: u5 = 0b10000,
8668 size: Size,
8669 decoded24: u5 = 0b01110,
8670 U: std.builtin.Signedness = .signed,
8671 Q: Q,
8672 decoded31: u1 = 0b0,
8673 };
8674
8675 /// C7.2.36 CMLT (zero)
8676 pub const Cmlt = packed struct {
8677 Rd: Register.Encoded,
8678 Rn: Register.Encoded,
8679 decoded10: u2 = 0b10,
8680 opcode: u5 = 0b01010,
8681 decoded17: u5 = 0b10000,
8682 size: Size,
8683 decoded24: u5 = 0b01110,
8684 U: std.builtin.Signedness = .signed,
8685 Q: Q,
8686 decoded31: u1 = 0b0,
8687 };
8688
8689 /// C7.2.1 ABS
8690 pub const Abs = packed struct {
8691 Rd: Register.Encoded,
8692 Rn: Register.Encoded,
8693 decoded10: u2 = 0b10,
8694 opcode: u5 = 0b01011,
8695 decoded17: u5 = 0b10000,
8696 size: Size,
8697 decoded24: u5 = 0b01110,
8698 U: std.builtin.Signedness = .signed,
8699 Q: Q,
8700 decoded31: u1 = 0b0,
8701 };
8702
8703 /// C7.2.308 SQXTN
8704 pub const Sqxtn = packed struct {
8705 Rd: Register.Encoded,
8706 Rn: Register.Encoded,
8707 decoded10: u2 = 0b10,
8708 opcode: u5 = 0b10100,
8709 decoded17: u5 = 0b10000,
8710 size: Size,
8711 decoded24: u5 = 0b01110,
8712 U: std.builtin.Signedness = .signed,
8713 Q: Q,
8714 decoded31: u1 = 0b0,
8715 };
8716
8717 /// C7.2.161 FRINTN (vector)
8718 pub const Frintn = packed struct {
8719 Rd: Register.Encoded,
8720 Rn: Register.Encoded,
8721 decoded10: u2 = 0b10,
8722 opcode: u5 = 0b11000,
8723 decoded17: u5 = 0b10000,
8724 sz: Sz,
8725 o2: u1 = 0b0,
8726 decoded24: u5 = 0b01110,
8727 U: std.builtin.Signedness = .signed,
8728 Q: Q,
8729 decoded31: u1 = 0b0,
8730 };
8731
8732 /// C7.2.159 FRINTM (vector)
8733 pub const Frintm = packed struct {
8734 Rd: Register.Encoded,
8735 Rn: Register.Encoded,
8736 decoded10: u2 = 0b10,
8737 opcode: u5 = 0b11001,
8738 decoded17: u5 = 0b10000,
8739 sz: Sz,
8740 o2: u1 = 0b0,
8741 decoded24: u5 = 0b01110,
8742 U: std.builtin.Signedness = .signed,
8743 Q: Q,
8744 decoded31: u1 = 0b0,
8745 };
8746
8747 /// C7.2.80 FCVTNS (vector)
8748 pub const Fcvtns = packed struct {
8749 Rd: Register.Encoded,
8750 Rn: Register.Encoded,
8751 decoded10: u2 = 0b10,
8752 opcode: u5 = 0b11010,
8753 decoded17: u5 = 0b10000,
8754 sz: Sz,
8755 o2: u1 = 0b0,
8756 decoded24: u5 = 0b01110,
8757 U: std.builtin.Signedness = .signed,
8758 Q: Q,
8759 decoded31: u1 = 0b0,
8760 };
8761
8762 /// C7.2.75 FCVTMS (vector)
8763 pub const Fcvtms = packed struct {
8764 Rd: Register.Encoded,
8765 Rn: Register.Encoded,
8766 decoded10: u2 = 0b10,
8767 opcode: u5 = 0b11011,
8768 decoded17: u5 = 0b10000,
8769 sz: Sz,
8770 o2: u1 = 0b0,
8771 decoded24: u5 = 0b01110,
8772 U: std.builtin.Signedness = .signed,
8773 Q: Q,
8774 decoded31: u1 = 0b0,
8775 };
8776
8777 /// C7.2.70 FCVTAS (vector)
8778 pub const Fcvtas = packed struct {
8779 Rd: Register.Encoded,
8780 Rn: Register.Encoded,
8781 decoded10: u2 = 0b10,
8782 opcode: u5 = 0b11100,
8783 decoded17: u5 = 0b10000,
8784 sz: Sz,
8785 o2: u1 = 0b0,
8786 decoded24: u5 = 0b01110,
8787 U: std.builtin.Signedness = .signed,
8788 Q: Q,
8789 decoded31: u1 = 0b0,
8790 };
8791
8792 /// C7.2.234 SCVTF (vector, integer)
8793 pub const Scvtf = packed struct {
8794 Rd: Register.Encoded,
8795 Rn: Register.Encoded,
8796 decoded10: u2 = 0b10,
8797 opcode: u5 = 0b11101,
8798 decoded17: u5 = 0b10000,
8799 sz: Sz,
8800 o2: u1 = 0b0,
8801 decoded24: u5 = 0b01110,
8802 U: std.builtin.Signedness = .signed,
8803 Q: Q,
8804 decoded31: u1 = 0b0,
8805 };
8806
8807 /// C7.2.61 FCMGT (zero)
8808 pub const Fcmgt = packed struct {
8809 Rd: Register.Encoded,
8810 Rn: Register.Encoded,
8811 decoded10: u2 = 0b10,
8812 opcode: u5 = 0b01100,
8813 decoded17: u5 = 0b10000,
8814 sz: Sz,
8815 o2: u1 = 0b1,
8816 decoded24: u5 = 0b01110,
8817 U: std.builtin.Signedness = .signed,
8818 Q: Q,
8819 decoded31: u1 = 0b0,
8820 };
8821
8822 /// C7.2.57 FCMEQ (zero)
8823 pub const Fcmeq = packed struct {
8824 Rd: Register.Encoded,
8825 Rn: Register.Encoded,
8826 decoded10: u2 = 0b10,
8827 opcode: u5 = 0b01101,
8828 decoded17: u5 = 0b10000,
8829 sz: Sz,
8830 o2: u1 = 0b1,
8831 decoded24: u5 = 0b01110,
8832 U: std.builtin.Signedness = .signed,
8833 Q: Q,
8834 decoded31: u1 = 0b0,
8835 };
8836
8837 /// C7.2.65 FCMLT (zero)
8838 pub const Fcmlt = packed struct {
8839 Rd: Register.Encoded,
8840 Rn: Register.Encoded,
8841 decoded10: u2 = 0b10,
8842 opcode: u5 = 0b01110,
8843 decoded17: u5 = 0b10000,
8844 sz: Sz,
8845 o2: u1 = 0b1,
8846 decoded24: u5 = 0b01110,
8847 U: std.builtin.Signedness = .signed,
8848 Q: Q,
8849 decoded31: u1 = 0b0,
8850 };
8851
8852 /// C7.2.45 FABS (vector)
8853 pub const Fabs = packed struct {
8854 Rd: Register.Encoded,
8855 Rn: Register.Encoded,
8856 decoded10: u2 = 0b10,
8857 opcode: u5 = 0b01111,
8858 decoded17: u5 = 0b10000,
8859 sz: Sz,
8860 o2: u1 = 0b1,
8861 decoded24: u5 = 0b01110,
8862 U: std.builtin.Signedness = .signed,
8863 Q: Q,
8864 decoded31: u1 = 0b0,
8865 };
8866
8867 /// C7.2.163 FRINTP (vector)
8868 pub const Frintp = packed struct {
8869 Rd: Register.Encoded,
8870 Rn: Register.Encoded,
8871 decoded10: u2 = 0b10,
8872 opcode: u5 = 0b11000,
8873 decoded17: u5 = 0b10000,
8874 sz: Sz,
8875 o2: u1 = 0b1,
8876 decoded24: u5 = 0b01110,
8877 U: std.builtin.Signedness = .signed,
8878 Q: Q,
8879 decoded31: u1 = 0b0,
8880 };
8881
8882 /// C7.2.167 FRINTZ (vector)
8883 pub const Frintz = packed struct {
8884 Rd: Register.Encoded,
8885 Rn: Register.Encoded,
8886 decoded10: u2 = 0b10,
8887 opcode: u5 = 0b11001,
8888 decoded17: u5 = 0b10000,
8889 sz: Sz,
8890 o2: u1 = 0b1,
8891 decoded24: u5 = 0b01110,
8892 U: std.builtin.Signedness = .signed,
8893 Q: Q,
8894 decoded31: u1 = 0b0,
8895 };
8896
8897 /// C7.2.84 FCVTPS (vector)
8898 pub const Fcvtps = packed struct {
8899 Rd: Register.Encoded,
8900 Rn: Register.Encoded,
8901 decoded10: u2 = 0b10,
8902 opcode: u5 = 0b11010,
8903 decoded17: u5 = 0b10000,
8904 sz: Sz,
8905 o2: u1 = 0b1,
8906 decoded24: u5 = 0b01110,
8907 U: std.builtin.Signedness = .signed,
8908 Q: Q,
8909 decoded31: u1 = 0b0,
8910 };
8911
8912 /// C7.2.90 FCVTZS (vector, integer)
8913 pub const Fcvtzs = packed struct {
8914 Rd: Register.Encoded,
8915 Rn: Register.Encoded,
8916 decoded10: u2 = 0b10,
8917 opcode: u5 = 0b11011,
8918 decoded17: u5 = 0b10000,
8919 sz: Sz,
8920 o2: u1 = 0b1,
8921 decoded24: u5 = 0b01110,
8922 U: std.builtin.Signedness = .signed,
8923 Q: Q,
8924 decoded31: u1 = 0b0,
8925 };
8926
8927 /// C7.2.144 FRECPE
8928 pub const Frecpe = packed struct {
8929 Rd: Register.Encoded,
8930 Rn: Register.Encoded,
8931 decoded10: u2 = 0b10,
8932 opcode: u5 = 0b11101,
8933 decoded17: u5 = 0b10000,
8934 sz: Sz,
8935 o2: u1 = 0b1,
8936 decoded24: u5 = 0b01110,
8937 U: std.builtin.Signedness = .signed,
8938 Q: Q,
8939 decoded31: u1 = 0b0,
8940 };
8941
8942 /// C7.2.394 USQADD
8943 pub const Usqadd = packed struct {
8944 Rd: Register.Encoded,
8945 Rn: Register.Encoded,
8946 decoded10: u2 = 0b10,
8947 opcode: u5 = 0b00011,
8948 decoded17: u5 = 0b10000,
8949 size: Size,
8950 decoded24: u5 = 0b01110,
8951 U: std.builtin.Signedness = .unsigned,
8952 Q: Q,
8953 decoded31: u1 = 0b0,
8954 };
8955
8956 /// C7.2.292 SQNEG
8957 pub const Sqneg = packed struct {
8958 Rd: Register.Encoded,
8959 Rn: Register.Encoded,
8960 decoded10: u2 = 0b10,
8961 opcode: u5 = 0b00111,
8962 decoded17: u5 = 0b10000,
8963 size: Size,
8964 decoded24: u5 = 0b01110,
8965 U: std.builtin.Signedness = .unsigned,
8966 Q: Q,
8967 decoded31: u1 = 0b0,
8968 };
8969
8970 /// C7.2.30 CMGE (zero)
8971 pub const Cmge = packed struct {
8972 Rd: Register.Encoded,
8973 Rn: Register.Encoded,
8974 decoded10: u2 = 0b10,
8975 opcode: u5 = 0b01000,
8976 decoded17: u5 = 0b10000,
8977 size: Size,
8978 decoded24: u5 = 0b01110,
8979 U: std.builtin.Signedness = .unsigned,
8980 Q: Q,
8981 decoded31: u1 = 0b0,
8982 };
8983
8984 /// C7.2.35 CMLE (zero)
8985 pub const Cmle = packed struct {
8986 Rd: Register.Encoded,
8987 Rn: Register.Encoded,
8988 decoded10: u2 = 0b10,
8989 opcode: u5 = 0b01001,
8990 decoded17: u5 = 0b10000,
8991 size: Size,
8992 decoded24: u5 = 0b01110,
8993 U: std.builtin.Signedness = .unsigned,
8994 Q: Q,
8995 decoded31: u1 = 0b0,
8996 };
8997
8998 /// C7.2.209 NEG (vector)
8999 pub const Neg = packed struct {
9000 Rd: Register.Encoded,
9001 Rn: Register.Encoded,
9002 decoded10: u2 = 0b10,
9003 opcode: u5 = 0b01011,
9004 decoded17: u5 = 0b10000,
9005 size: Size,
9006 decoded24: u5 = 0b01110,
9007 U: std.builtin.Signedness = .unsigned,
9008 Q: Q,
9009 decoded31: u1 = 0b0,
9010 };
9011
9012 /// C7.2.309 SQXTUN
9013 pub const Sqxtun = packed struct {
9014 Rd: Register.Encoded,
9015 Rn: Register.Encoded,
9016 decoded10: u2 = 0b10,
9017 opcode: u5 = 0b10010,
9018 decoded17: u5 = 0b10000,
9019 size: Size,
9020 decoded24: u5 = 0b01110,
9021 U: std.builtin.Signedness = .unsigned,
9022 Q: Q,
9023 decoded31: u1 = 0b0,
9024 };
9025
9026 /// C7.2.381 UQXTN
9027 pub const Uqxtn = packed struct {
9028 Rd: Register.Encoded,
9029 Rn: Register.Encoded,
9030 decoded10: u2 = 0b10,
9031 opcode: u5 = 0b10100,
9032 decoded17: u5 = 0b10000,
9033 size: Size,
9034 decoded24: u5 = 0b01110,
9035 U: std.builtin.Signedness = .unsigned,
9036 Q: Q,
9037 decoded31: u1 = 0b0,
9038 };
9039
9040 /// C7.2.88 FCVTXN
9041 pub const Fcvtxn = packed struct {
9042 Rd: Register.Encoded,
9043 Rn: Register.Encoded,
9044 decoded10: u2 = 0b10,
9045 opcode: u5 = 0b10110,
9046 decoded17: u5 = 0b10000,
9047 sz: Sz,
9048 o2: u1 = 0b0,
9049 decoded24: u5 = 0b01110,
9050 U: std.builtin.Signedness = .unsigned,
9051 Q: Q,
9052 decoded31: u1 = 0b0,
9053 };
9054
9055 /// C7.2.155 FRINTA (vector)
9056 pub const Frinta = packed struct {
9057 Rd: Register.Encoded,
9058 Rn: Register.Encoded,
9059 decoded10: u2 = 0b10,
9060 opcode: u5 = 0b11000,
9061 decoded17: u5 = 0b10000,
9062 sz: Sz,
9063 o2: u1 = 0b0,
9064 decoded24: u5 = 0b01110,
9065 U: std.builtin.Signedness = .unsigned,
9066 Q: Q,
9067 decoded31: u1 = 0b0,
9068 };
9069
9070 /// C7.2.165 FRINTX (vector)
9071 pub const Frintx = packed struct {
9072 Rd: Register.Encoded,
9073 Rn: Register.Encoded,
9074 decoded10: u2 = 0b10,
9075 opcode: u5 = 0b11001,
9076 decoded17: u5 = 0b10000,
9077 sz: Sz,
9078 o2: u1 = 0b0,
9079 decoded24: u5 = 0b01110,
9080 U: std.builtin.Signedness = .unsigned,
9081 Q: Q,
9082 decoded31: u1 = 0b0,
9083 };
9084
9085 /// C7.2.82 FCVTNU (vector)
9086 pub const Fcvtnu = packed struct {
9087 Rd: Register.Encoded,
9088 Rn: Register.Encoded,
9089 decoded10: u2 = 0b10,
9090 opcode: u5 = 0b11010,
9091 decoded17: u5 = 0b10000,
9092 sz: Sz,
9093 o2: u1 = 0b0,
9094 decoded24: u5 = 0b01110,
9095 U: std.builtin.Signedness = .unsigned,
9096 Q: Q,
9097 decoded31: u1 = 0b0,
9098 };
9099
9100 /// C7.2.77 FCVTMU (vector)
9101 pub const Fcvtmu = packed struct {
9102 Rd: Register.Encoded,
9103 Rn: Register.Encoded,
9104 decoded10: u2 = 0b10,
9105 opcode: u5 = 0b11011,
9106 decoded17: u5 = 0b10000,
9107 sz: Sz,
9108 o2: u1 = 0b0,
9109 decoded24: u5 = 0b01110,
9110 U: std.builtin.Signedness = .unsigned,
9111 Q: Q,
9112 decoded31: u1 = 0b0,
9113 };
9114
9115 /// C7.2.72 FCVTAU (vector)
9116 pub const Fcvtau = packed struct {
9117 Rd: Register.Encoded,
9118 Rn: Register.Encoded,
9119 decoded10: u2 = 0b10,
9120 opcode: u5 = 0b11100,
9121 decoded17: u5 = 0b10000,
9122 sz: Sz,
9123 o2: u1 = 0b0,
9124 decoded24: u5 = 0b01110,
9125 U: std.builtin.Signedness = .unsigned,
9126 Q: Q,
9127 decoded31: u1 = 0b0,
9128 };
9129
9130 /// C7.2.353 UCVTF (vector, integer)
9131 pub const Ucvtf = packed struct {
9132 Rd: Register.Encoded,
9133 Rn: Register.Encoded,
9134 decoded10: u2 = 0b10,
9135 opcode: u5 = 0b11101,
9136 decoded17: u5 = 0b10000,
9137 sz: Sz,
9138 o2: u1 = 0b0,
9139 decoded24: u5 = 0b01110,
9140 U: std.builtin.Signedness = .unsigned,
9141 Q: Q,
9142 decoded31: u1 = 0b0,
9143 };
9144
9145 /// C7.2.210 NOT
9146 pub const Not = packed struct {
9147 Rd: Register.Encoded,
9148 Rn: Register.Encoded,
9149 decoded10: u2 = 0b10,
9150 opcode: u5 = 0b00101,
9151 decoded17: u5 = 0b10000,
9152 size: Size = .byte,
9153 decoded24: u5 = 0b01110,
9154 U: std.builtin.Signedness = .unsigned,
9155 Q: Q,
9156 decoded31: u1 = 0b0,
9157 };
9158
9159 /// C7.2.59 FCMGE (zero)
9160 pub const Fcmge = packed struct {
9161 Rd: Register.Encoded,
9162 Rn: Register.Encoded,
9163 decoded10: u2 = 0b10,
9164 opcode: u5 = 0b01100,
9165 decoded17: u5 = 0b10000,
9166 sz: Sz,
9167 o2: u1 = 0b1,
9168 decoded24: u5 = 0b01110,
9169 U: std.builtin.Signedness = .unsigned,
9170 Q: Q,
9171 decoded31: u1 = 0b0,
9172 };
9173
9174 /// C7.2.64 FCMLE (zero)
9175 pub const Fcmle = packed struct {
9176 Rd: Register.Encoded,
9177 Rn: Register.Encoded,
9178 decoded10: u2 = 0b10,
9179 opcode: u5 = 0b01101,
9180 decoded17: u5 = 0b10000,
9181 sz: Sz,
9182 o2: u1 = 0b1,
9183 decoded24: u5 = 0b01110,
9184 U: std.builtin.Signedness = .unsigned,
9185 Q: Q,
9186 decoded31: u1 = 0b0,
9187 };
9188
9189 /// C7.2.139 FNEG (vector)
9190 pub const Fneg = packed struct {
9191 Rd: Register.Encoded,
9192 Rn: Register.Encoded,
9193 decoded10: u2 = 0b10,
9194 opcode: u5 = 0b01111,
9195 decoded17: u5 = 0b10000,
9196 sz: Sz,
9197 o2: u1 = 0b1,
9198 decoded24: u5 = 0b01110,
9199 U: std.builtin.Signedness = .unsigned,
9200 Q: Q,
9201 decoded31: u1 = 0b0,
9202 };
9203
9204 /// C7.2.157 FRINTI (vector)
9205 pub const Frinti = packed struct {
9206 Rd: Register.Encoded,
9207 Rn: Register.Encoded,
9208 decoded10: u2 = 0b10,
9209 opcode: u5 = 0b11001,
9210 decoded17: u5 = 0b10000,
9211 sz: Sz,
9212 o2: u1 = 0b1,
9213 decoded24: u5 = 0b01110,
9214 U: std.builtin.Signedness = .unsigned,
9215 Q: Q,
9216 decoded31: u1 = 0b0,
9217 };
9218
9219 /// C7.2.86 FCVTPU (vector)
9220 pub const Fcvtpu = packed struct {
9221 Rd: Register.Encoded,
9222 Rn: Register.Encoded,
9223 decoded10: u2 = 0b10,
9224 opcode: u5 = 0b11010,
9225 decoded17: u5 = 0b10000,
9226 sz: Sz,
9227 o2: u1 = 0b1,
9228 decoded24: u5 = 0b01110,
9229 U: std.builtin.Signedness = .unsigned,
9230 Q: Q,
9231 decoded31: u1 = 0b0,
9232 };
9233
9234 /// C7.2.94 FCVTZU (vector, integer)
9235 pub const Fcvtzu = packed struct {
9236 Rd: Register.Encoded,
9237 Rn: Register.Encoded,
9238 decoded10: u2 = 0b10,
9239 opcode: u5 = 0b11011,
9240 decoded17: u5 = 0b10000,
9241 sz: Sz,
9242 o2: u1 = 0b1,
9243 decoded24: u5 = 0b01110,
9244 U: std.builtin.Signedness = .unsigned,
9245 Q: Q,
9246 decoded31: u1 = 0b0,
9247 };
9248
9249 /// C7.2.169 FRSQRTE
9250 pub const Frsqrte = packed struct {
9251 Rd: Register.Encoded,
9252 Rn: Register.Encoded,
9253 decoded10: u2 = 0b10,
9254 opcode: u5 = 0b11101,
9255 decoded17: u5 = 0b10000,
9256 sz: Sz,
9257 o2: u1 = 0b1,
9258 decoded24: u5 = 0b01110,
9259 U: std.builtin.Signedness = .unsigned,
9260 Q: Q,
9261 decoded31: u1 = 0b0,
9262 };
9263
9264 /// C7.2.171 FSQRT (vector)
9265 pub const Fsqrt = packed struct {
9266 Rd: Register.Encoded,
9267 Rn: Register.Encoded,
9268 decoded10: u2 = 0b10,
9269 opcode: u5 = 0b11111,
9270 decoded17: u5 = 0b10000,
9271 sz: Sz,
9272 o2: u1 = 0b1,
9273 decoded24: u5 = 0b01110,
9274 U: std.builtin.Signedness = .unsigned,
9275 Q: Q,
9276 decoded31: u1 = 0b0,
9277 };
9278 };
9279
9280 /// Advanced SIMD across lanes
9281 pub const SimdAcrossLanes = packed union {
9282 group: @This().Group,
9283 addv: Addv,
9284
9285 pub const Group = packed struct {
9286 Rd: Register.Encoded,
9287 Rn: Register.Encoded,
9288 decoded10: u2 = 0b10,
9289 opcode: u5,
9290 decoded17: u5 = 0b11000,
9291 size: Size,
9292 decoded24: u5 = 0b01110,
9293 U: std.builtin.Signedness,
9294 Q: Q,
9295 decoded31: u1 = 0b0,
9296 };
9297
9298 /// C7.2.6 ADDV
9299 pub const Addv = packed struct {
9300 Rd: Register.Encoded,
9301 Rn: Register.Encoded,
9302 decoded10: u2 = 0b10,
9303 opcode: u5 = 0b11011,
9304 decoded17: u5 = 0b11000,
9305 size: Size,
9306 decoded24: u5 = 0b01110,
9307 U: std.builtin.Signedness = .signed,
9308 Q: Q,
9309 decoded31: u1 = 0b0,
9310 };
9311 };
9312
9313 /// Advanced SIMD three same
9314 pub const SimdThreeSame = packed union {
9315 group: @This().Group,
9316 addp: Addp,
9317 @"and": And,
9318 bic: Bic,
9319 orr: Orr,
9320 orn: Orn,
9321 eor: Eor,
9322 bsl: Bsl,
9323 bit: Bit,
9324 bif: Bif,
9325
9326 pub const Group = packed struct {
9327 Rd: Register.Encoded,
9328 Rn: Register.Encoded,
9329 decoded10: u1 = 0b1,
9330 opcode: u5,
9331 Rm: Register.Encoded,
9332 decoded21: u1 = 0b1,
9333 size: Size,
9334 decoded24: u5 = 0b01110,
9335 U: std.builtin.Signedness,
9336 Q: Q,
9337 decoded31: u1 = 0b0,
9338 };
9339
9340 /// C7.2.5 ADDP (vector)
9341 pub const Addp = packed struct {
9342 Rd: Register.Encoded,
9343 Rn: Register.Encoded,
9344 decoded10: u1 = 0b1,
9345 opcode: u5 = 0b10111,
9346 Rm: Register.Encoded,
9347 decoded21: u1 = 0b1,
9348 size: Size,
9349 decoded24: u5 = 0b01110,
9350 U: std.builtin.Signedness = .signed,
9351 Q: Q,
9352 decoded31: u1 = 0b0,
9353 };
9354
9355 /// C7.2.11 AND (vector)
9356 pub const And = packed struct {
9357 Rd: Register.Encoded,
9358 Rn: Register.Encoded,
9359 decoded10: u1 = 0b1,
9360 opcode: u5 = 0b00011,
9361 Rm: Register.Encoded,
9362 decoded21: u1 = 0b1,
9363 size: Size = .byte,
9364 decoded24: u5 = 0b01110,
9365 U: std.builtin.Signedness = .signed,
9366 Q: Q,
9367 decoded31: u1 = 0b0,
9368 };
9369
9370 /// C7.2.21 BIC (vector, register)
9371 pub const Bic = packed struct {
9372 Rd: Register.Encoded,
9373 Rn: Register.Encoded,
9374 decoded10: u1 = 0b1,
9375 opcode: u5 = 0b00011,
9376 Rm: Register.Encoded,
9377 decoded21: u1 = 0b1,
9378 size: Size = .half,
9379 decoded24: u5 = 0b01110,
9380 U: std.builtin.Signedness = .signed,
9381 Q: Q,
9382 decoded31: u1 = 0b0,
9383 };
9384
9385 /// C7.2.213 ORR (vector, register)
9386 pub const Orr = packed struct {
9387 Rd: Register.Encoded,
9388 Rn: Register.Encoded,
9389 decoded10: u1 = 0b1,
9390 opcode: u5 = 0b00011,
9391 Rm: Register.Encoded,
9392 decoded21: u1 = 0b1,
9393 size: Size = .single,
9394 decoded24: u5 = 0b01110,
9395 U: std.builtin.Signedness = .signed,
9396 Q: Q,
9397 decoded31: u1 = 0b0,
9398 };
9399
9400 /// C7.2.211 ORN (vector)
9401 pub const Orn = packed struct {
9402 Rd: Register.Encoded,
9403 Rn: Register.Encoded,
9404 decoded10: u1 = 0b1,
9405 opcode: u5 = 0b00011,
9406 Rm: Register.Encoded,
9407 decoded21: u1 = 0b1,
9408 size: Size = .double,
9409 decoded24: u5 = 0b01110,
9410 U: std.builtin.Signedness = .signed,
9411 Q: Q,
9412 decoded31: u1 = 0b0,
9413 };
9414
9415 /// C7.2.41 EOR (vector)
9416 pub const Eor = packed struct {
9417 Rd: Register.Encoded,
9418 Rn: Register.Encoded,
9419 decoded10: u1 = 0b1,
9420 opcode: u5 = 0b00011,
9421 Rm: Register.Encoded,
9422 decoded21: u1 = 0b1,
9423 size: Size = .byte,
9424 decoded24: u5 = 0b01110,
9425 U: std.builtin.Signedness = .unsigned,
9426 Q: Q,
9427 decoded31: u1 = 0b0,
9428 };
9429
9430 /// C7.2.24 BSL
9431 pub const Bsl = packed struct {
9432 Rd: Register.Encoded,
9433 Rn: Register.Encoded,
9434 decoded10: u1 = 0b1,
9435 opcode: u5 = 0b00011,
9436 Rm: Register.Encoded,
9437 decoded21: u1 = 0b1,
9438 size: Size = .half,
9439 decoded24: u5 = 0b01110,
9440 U: std.builtin.Signedness = .unsigned,
9441 Q: Q,
9442 decoded31: u1 = 0b0,
9443 };
9444
9445 /// C7.2.23 BIT
9446 pub const Bit = packed struct {
9447 Rd: Register.Encoded,
9448 Rn: Register.Encoded,
9449 decoded10: u1 = 0b1,
9450 opcode: u5 = 0b00011,
9451 Rm: Register.Encoded,
9452 decoded21: u1 = 0b1,
9453 size: Size = .single,
9454 decoded24: u5 = 0b01110,
9455 U: std.builtin.Signedness = .unsigned,
9456 Q: Q,
9457 decoded31: u1 = 0b0,
9458 };
9459
9460 /// C7.2.22 BIF
9461 pub const Bif = packed struct {
9462 Rd: Register.Encoded,
9463 Rn: Register.Encoded,
9464 decoded10: u1 = 0b1,
9465 opcode: u5 = 0b00011,
9466 Rm: Register.Encoded,
9467 decoded21: u1 = 0b1,
9468 size: Size = .double,
9469 decoded24: u5 = 0b01110,
9470 U: std.builtin.Signedness = .unsigned,
9471 Q: Q,
9472 decoded31: u1 = 0b0,
9473 };
9474 };
9475
9476 /// Advanced SIMD modified immediate
9477 pub const SimdModifiedImmediate = packed union {
9478 group: @This().Group,
9479 movi: Movi,
9480 orr: Orr,
9481 fmov: Fmov,
9482 mvni: Mvni,
9483 bic: Bic,
9484
9485 pub const Group = packed struct {
9486 Rd: Register.Encoded,
9487 imm5: u5,
9488 decoded10: u1 = 0b1,
9489 o2: u1,
9490 cmode: u4,
9491 imm3: u3,
9492 decoded19: u10 = 0b0111100000,
9493 op: u1,
9494 Q: Q,
9495 decoded31: u1 = 0b0,
9496 };
9497
9498 /// C7.2.204 MOVI
9499 pub const Movi = packed struct {
9500 Rd: Register.Encoded,
9501 imm5: u5,
9502 decoded10: u1 = 0b1,
9503 o2: u1 = 0b0,
9504 cmode: u4,
9505 imm3: u3,
9506 decoded19: u10 = 0b0111100000,
9507 op: u1,
9508 Q: Q,
9509 decoded31: u1 = 0b0,
9510 };
9511
9512 /// C7.2.212 ORR (vector, immediate)
9513 pub const Orr = packed struct {
9514 Rd: Register.Encoded,
9515 imm5: u5,
9516 decoded10: u1 = 0b1,
9517 o2: u1 = 0b0,
9518 cmode0: u1 = 0b1,
9519 cmode: u3,
9520 imm3: u3,
9521 decoded19: u10 = 0b0111100000,
9522 op: u1 = 0b0,
9523 Q: Q,
9524 decoded31: u1 = 0b0,
9525 };
9526
9527 /// C7.2.129 FMOV (vector, immediate)
9528 pub const Fmov = packed struct {
9529 Rd: Register.Encoded,
9530 imm5: u5,
9531 decoded10: u1 = 0b1,
9532 o2: u1 = 0b1,
9533 cmode: u4 = 0b1111,
9534 imm3: u3,
9535 decoded19: u10 = 0b0111100000,
9536 op: u1 = 0b0,
9537 Q: Q,
9538 decoded31: u1 = 0b0,
9539 };
9540
9541 /// C7.2.208 MVNI
9542 pub const Mvni = packed struct {
9543 Rd: Register.Encoded,
9544 imm5: u5,
9545 decoded10: u1 = 0b1,
9546 o2: u1 = 0b0,
9547 cmode: u4,
9548 imm3: u3,
9549 decoded19: u10 = 0b0111100000,
9550 op: u1 = 0b1,
9551 Q: Q,
9552 decoded31: u1 = 0b0,
9553 };
9554
9555 /// C7.2.20 BIC (vector, immediate)
9556 pub const Bic = packed struct {
9557 Rd: Register.Encoded,
9558 imm5: u5,
9559 decoded10: u1 = 0b1,
9560 o2: u1 = 0b0,
9561 cmode0: u1 = 0b1,
9562 cmode: u3,
9563 imm3: u3,
9564 decoded19: u10 = 0b0111100000,
9565 op: u1 = 0b1,
9566 Q: Q,
9567 decoded31: u1 = 0b0,
9568 };
9569 };
9570
9571 /// Conversion between floating-point and integer
9572 pub const ConvertFloatInteger = packed union {
9573 group: @This().Group,
9574 fcvtns: Fcvtns,
9575 fcvtnu: Fcvtnu,
9576 scvtf: Scvtf,
9577 ucvtf: Ucvtf,
9578 fcvtas: Fcvtas,
9579 fcvtau: Fcvtau,
9580 fmov: Fmov,
9581 fcvtps: Fcvtps,
9582 fcvtpu: Fcvtpu,
9583 fcvtms: Fcvtms,
9584 fcvtmu: Fcvtmu,
9585 fcvtzs: Fcvtzs,
9586 fcvtzu: Fcvtzu,
9587 fjcvtzs: Fjcvtzs,
9588
9589 pub const Group = packed struct {
9590 Rd: Register.Encoded,
9591 Rn: Register.Encoded,
9592 decoded10: u6 = 0b000000,
9593 opcode: u3,
9594 rmode: u2,
9595 decoded21: u1 = 0b1,
9596 ptype: Ftype,
9597 decoded24: u5 = 0b11110,
9598 S: bool,
9599 decoded30: u1 = 0b0,
9600 sf: Register.IntegerSize,
9601 };
9602
9603 /// C7.2.81 FCVTNS (scalar)
9604 pub const Fcvtns = packed struct {
9605 Rd: Register.Encoded,
9606 Rn: Register.Encoded,
9607 decoded10: u6 = 0b000000,
9608 opcode: u3 = 0b000,
9609 rmode: Rmode = .n,
9610 decoded21: u1 = 0b1,
9611 ftype: Ftype,
9612 decoded24: u5 = 0b11110,
9613 S: bool = false,
9614 decoded30: u1 = 0b0,
9615 sf: Register.IntegerSize,
9616 };
9617
9618 /// C7.2.83 FCVTNU (scalar)
9619 pub const Fcvtnu = packed struct {
9620 Rd: Register.Encoded,
9621 Rn: Register.Encoded,
9622 decoded10: u6 = 0b000000,
9623 opcode: u3 = 0b001,
9624 rmode: Rmode = .n,
9625 decoded21: u1 = 0b1,
9626 ftype: Ftype,
9627 decoded24: u5 = 0b11110,
9628 S: bool = false,
9629 decoded30: u1 = 0b0,
9630 sf: Register.IntegerSize,
9631 };
9632
9633 /// C7.2.236 SCVTF (scalar, integer)
9634 pub const Scvtf = packed struct {
9635 Rd: Register.Encoded,
9636 Rn: Register.Encoded,
9637 decoded10: u6 = 0b000000,
9638 opcode: u3 = 0b010,
9639 rmode: Rmode = .n,
9640 decoded21: u1 = 0b1,
9641 ftype: Ftype,
9642 decoded24: u5 = 0b11110,
9643 S: bool = false,
9644 decoded30: u1 = 0b0,
9645 sf: Register.IntegerSize,
9646 };
9647
9648 /// C7.2.355 UCVTF (scalar, integer)
9649 pub const Ucvtf = packed struct {
9650 Rd: Register.Encoded,
9651 Rn: Register.Encoded,
9652 decoded10: u6 = 0b000000,
9653 opcode: u3 = 0b011,
9654 rmode: Rmode = .n,
9655 decoded21: u1 = 0b1,
9656 ftype: Ftype,
9657 decoded24: u5 = 0b11110,
9658 S: bool = false,
9659 decoded30: u1 = 0b0,
9660 sf: Register.IntegerSize,
9661 };
9662
9663 /// C7.2.71 FCVTAS (scalar)
9664 pub const Fcvtas = packed struct {
9665 Rd: Register.Encoded,
9666 Rn: Register.Encoded,
9667 decoded10: u6 = 0b000000,
9668 opcode: u3 = 0b100,
9669 rmode: Rmode = .n,
9670 decoded21: u1 = 0b1,
9671 ftype: Ftype,
9672 decoded24: u5 = 0b11110,
9673 S: bool = false,
9674 decoded30: u1 = 0b0,
9675 sf: Register.IntegerSize,
9676 };
9677
9678 /// C7.2.73 FCVTAU (scalar)
9679 pub const Fcvtau = packed struct {
9680 Rd: Register.Encoded,
9681 Rn: Register.Encoded,
9682 decoded10: u6 = 0b000000,
9683 opcode: u3 = 0b101,
9684 rmode: Rmode = .n,
9685 decoded21: u1 = 0b1,
9686 ftype: Ftype,
9687 decoded24: u5 = 0b11110,
9688 S: bool = false,
9689 decoded30: u1 = 0b0,
9690 sf: Register.IntegerSize,
9691 };
9692
9693 /// C7.2.131 FMOV (general)
9694 pub const Fmov = packed struct {
9695 Rd: Register.Encoded,
9696 Rn: Register.Encoded,
9697 decoded10: u6 = 0b000000,
9698 opcode: Opcode,
9699 rmode: Fmov.Rmode,
9700 decoded21: u1 = 0b1,
9701 ftype: Ftype,
9702 decoded24: u5 = 0b11110,
9703 S: bool = false,
9704 decoded30: u1 = 0b0,
9705 sf: Register.IntegerSize,
9706
9707 pub const Opcode = enum(u3) {
9708 float_to_integer = 0b110,
9709 integer_to_float = 0b111,
9710 _,
9711 };
9712
9713 pub const Rmode = enum(u2) {
9714 @"0" = 0b00,
9715 @"1" = 0b01,
9716 _,
9717 };
9718 };
9719
9720 /// C7.2.85 FCVTPS (scalar)
9721 pub const Fcvtps = packed struct {
9722 Rd: Register.Encoded,
9723 Rn: Register.Encoded,
9724 decoded10: u6 = 0b000000,
9725 opcode: u3 = 0b000,
9726 rmode: Rmode = .p,
9727 decoded21: u1 = 0b1,
9728 ftype: Ftype,
9729 decoded24: u5 = 0b11110,
9730 S: bool = false,
9731 decoded30: u1 = 0b0,
9732 sf: Register.IntegerSize,
9733 };
9734
9735 /// C7.2.87 FCVTPU (scalar)
9736 pub const Fcvtpu = packed struct {
9737 Rd: Register.Encoded,
9738 Rn: Register.Encoded,
9739 decoded10: u6 = 0b000000,
9740 opcode: u3 = 0b001,
9741 rmode: Rmode = .p,
9742 decoded21: u1 = 0b1,
9743 ftype: Ftype,
9744 decoded24: u5 = 0b11110,
9745 S: bool = false,
9746 decoded30: u1 = 0b0,
9747 sf: Register.IntegerSize,
9748 };
9749
9750 /// C7.2.76 FCVTMS (scalar)
9751 pub const Fcvtms = packed struct {
9752 Rd: Register.Encoded,
9753 Rn: Register.Encoded,
9754 decoded10: u6 = 0b000000,
9755 opcode: u3 = 0b000,
9756 rmode: Rmode = .m,
9757 decoded21: u1 = 0b1,
9758 ftype: Ftype,
9759 decoded24: u5 = 0b11110,
9760 S: bool = false,
9761 decoded30: u1 = 0b0,
9762 sf: Register.IntegerSize,
9763 };
9764
9765 /// C7.2.78 FCVTMU (scalar)
9766 pub const Fcvtmu = packed struct {
9767 Rd: Register.Encoded,
9768 Rn: Register.Encoded,
9769 decoded10: u6 = 0b000000,
9770 opcode: u3 = 0b001,
9771 rmode: Rmode = .m,
9772 decoded21: u1 = 0b1,
9773 ftype: Ftype,
9774 decoded24: u5 = 0b11110,
9775 S: bool = false,
9776 decoded30: u1 = 0b0,
9777 sf: Register.IntegerSize,
9778 };
9779
9780 /// C7.2.92 FCVTZS (scalar, integer)
9781 pub const Fcvtzs = packed struct {
9782 Rd: Register.Encoded,
9783 Rn: Register.Encoded,
9784 decoded10: u6 = 0b000000,
9785 opcode: u3 = 0b000,
9786 rmode: Rmode = .z,
9787 decoded21: u1 = 0b1,
9788 ftype: Ftype,
9789 decoded24: u5 = 0b11110,
9790 S: bool = false,
9791 decoded30: u1 = 0b0,
9792 sf: Register.IntegerSize,
9793 };
9794
9795 /// C7.2.96 FCVTZU (scalar, integer)
9796 pub const Fcvtzu = packed struct {
9797 Rd: Register.Encoded,
9798 Rn: Register.Encoded,
9799 decoded10: u6 = 0b000000,
9800 opcode: u3 = 0b001,
9801 rmode: Rmode = .z,
9802 decoded21: u1 = 0b1,
9803 ftype: Ftype,
9804 decoded24: u5 = 0b11110,
9805 S: bool = false,
9806 decoded30: u1 = 0b0,
9807 sf: Register.IntegerSize,
9808 };
9809
9810 /// C7.2.99 FJCVTZS
9811 pub const Fjcvtzs = packed struct {
9812 Rd: Register.Encoded,
9813 Rn: Register.Encoded,
9814 decoded10: u6 = 0b000000,
9815 opcode: u3 = 0b110,
9816 rmode: Rmode = .z,
9817 decoded21: u1 = 0b1,
9818 ftype: Ftype = .double,
9819 decoded24: u5 = 0b11110,
9820 S: bool = false,
9821 decoded30: u1 = 0b0,
9822 sf: Register.IntegerSize = .word,
9823 };
9824
9825 pub const Rmode = enum(u2) {
9826 /// to nearest
9827 n = 0b00,
9828 /// toward plus infinity
9829 p = 0b01,
9830 /// toward minus infinity
9831 m = 0b10,
9832 /// toward zero
9833 z = 0b11,
9834 };
9835 };
9836
9837 /// Floating-point data-processing (1 source)
9838 pub const FloatDataProcessingOneSource = packed union {
9839 group: @This().Group,
9840 fmov: Fmov,
9841 fabs: Fabs,
9842 fneg: Fneg,
9843 fsqrt: Fsqrt,
9844 fcvt: Fcvt,
9845 frintn: Frintn,
9846 frintp: Frintp,
9847 frintm: Frintm,
9848 frintz: Frintz,
9849 frinta: Frinta,
9850 frintx: Frintx,
9851 frinti: Frinti,
9852
9853 pub const Group = packed struct {
9854 Rd: Register.Encoded,
9855 Rn: Register.Encoded,
9856 decoded10: u5 = 0b10000,
9857 opcode: u6,
9858 decoded21: u1 = 0b1,
9859 ptype: Ftype,
9860 decoded24: u5 = 0b11110,
9861 S: bool,
9862 decoded30: u1 = 0b0,
9863 M: u1,
9864 };
9865
9866 /// C7.2.130 FMOV (register)
9867 pub const Fmov = packed struct {
9868 Rd: Register.Encoded,
9869 Rn: Register.Encoded,
9870 decoded10: u5 = 0b10000,
9871 opc: u2 = 0b00,
9872 decoded17: u4 = 0b0000,
9873 decoded21: u1 = 0b1,
9874 ftype: Ftype,
9875 decoded24: u5 = 0b11110,
9876 S: bool = false,
9877 decoded30: u1 = 0b0,
9878 M: u1 = 0b0,
9879 };
9880
9881 /// C7.2.46 FABS (scalar)
9882 pub const Fabs = packed struct {
9883 Rd: Register.Encoded,
9884 Rn: Register.Encoded,
9885 decoded10: u5 = 0b10000,
9886 opc: u2 = 0b01,
9887 decoded17: u4 = 0b0000,
9888 decoded21: u1 = 0b1,
9889 ftype: Ftype,
9890 decoded24: u5 = 0b11110,
9891 S: bool = false,
9892 decoded30: u1 = 0b0,
9893 M: u1 = 0b0,
9894 };
9895
9896 /// C7.2.140 FNEG (scalar)
9897 pub const Fneg = packed struct {
9898 Rd: Register.Encoded,
9899 Rn: Register.Encoded,
9900 decoded10: u5 = 0b10000,
9901 opc: u2 = 0b10,
9902 decoded17: u4 = 0b0000,
9903 decoded21: u1 = 0b1,
9904 ftype: Ftype,
9905 decoded24: u5 = 0b11110,
9906 S: bool = false,
9907 decoded30: u1 = 0b0,
9908 M: u1 = 0b0,
9909 };
9910
9911 /// C7.2.172 FSQRT (scalar)
9912 pub const Fsqrt = packed struct {
9913 Rd: Register.Encoded,
9914 Rn: Register.Encoded,
9915 decoded10: u5 = 0b10000,
9916 opc: u2 = 0b11,
9917 decoded17: u4 = 0b0000,
9918 decoded21: u1 = 0b1,
9919 ftype: Ftype,
9920 decoded24: u5 = 0b11110,
9921 S: bool = false,
9922 decoded30: u1 = 0b0,
9923 M: u1 = 0b0,
9924 };
9925
9926 /// C7.2.69 FCVT
9927 pub const Fcvt = packed struct {
9928 Rd: Register.Encoded,
9929 Rn: Register.Encoded,
9930 decoded10: u5 = 0b10000,
9931 opc: Ftype,
9932 decoded17: u4 = 0b0001,
9933 decoded21: u1 = 0b1,
9934 ftype: Ftype,
9935 decoded24: u5 = 0b11110,
9936 S: bool = false,
9937 decoded30: u1 = 0b0,
9938 M: u1 = 0b0,
9939 };
9940
9941 /// C7.2.162 FRINTN (scalar)
9942 pub const Frintn = packed struct {
9943 Rd: Register.Encoded,
9944 Rn: Register.Encoded,
9945 decoded10: u5 = 0b10000,
9946 rmode: Rmode = .n,
9947 decoded18: u3 = 0b001,
9948 decoded21: u1 = 0b1,
9949 ftype: Ftype,
9950 decoded24: u5 = 0b11110,
9951 S: bool = false,
9952 decoded30: u1 = 0b0,
9953 M: u1 = 0b0,
9954 };
9955
9956 /// C7.2.164 FRINTP (scalar)
9957 pub const Frintp = packed struct {
9958 Rd: Register.Encoded,
9959 Rn: Register.Encoded,
9960 decoded10: u5 = 0b10000,
9961 rmode: Rmode = .p,
9962 decoded18: u3 = 0b001,
9963 decoded21: u1 = 0b1,
9964 ftype: Ftype,
9965 decoded24: u5 = 0b11110,
9966 S: bool = false,
9967 decoded30: u1 = 0b0,
9968 M: u1 = 0b0,
9969 };
9970
9971 /// C7.2.160 FRINTM (scalar)
9972 pub const Frintm = packed struct {
9973 Rd: Register.Encoded,
9974 Rn: Register.Encoded,
9975 decoded10: u5 = 0b10000,
9976 rmode: Rmode = .m,
9977 decoded18: u3 = 0b001,
9978 decoded21: u1 = 0b1,
9979 ftype: Ftype,
9980 decoded24: u5 = 0b11110,
9981 S: bool = false,
9982 decoded30: u1 = 0b0,
9983 M: u1 = 0b0,
9984 };
9985
9986 /// C7.2.168 FRINTZ (scalar)
9987 pub const Frintz = packed struct {
9988 Rd: Register.Encoded,
9989 Rn: Register.Encoded,
9990 decoded10: u5 = 0b10000,
9991 rmode: Rmode = .z,
9992 decoded18: u3 = 0b001,
9993 decoded21: u1 = 0b1,
9994 ftype: Ftype,
9995 decoded24: u5 = 0b11110,
9996 S: bool = false,
9997 decoded30: u1 = 0b0,
9998 M: u1 = 0b0,
9999 };
10000
10001 /// C7.2.156 FRINTA (scalar)
10002 pub const Frinta = packed struct {
10003 Rd: Register.Encoded,
10004 Rn: Register.Encoded,
10005 decoded10: u5 = 0b10000,
10006 rmode: Rmode = .a,
10007 decoded18: u3 = 0b001,
10008 decoded21: u1 = 0b1,
10009 ftype: Ftype,
10010 decoded24: u5 = 0b11110,
10011 S: bool = false,
10012 decoded30: u1 = 0b0,
10013 M: u1 = 0b0,
10014 };
10015
10016 /// C7.2.166 FRINTX (scalar)
10017 pub const Frintx = packed struct {
10018 Rd: Register.Encoded,
10019 Rn: Register.Encoded,
10020 decoded10: u5 = 0b10000,
10021 rmode: Rmode = .x,
10022 decoded18: u3 = 0b001,
10023 decoded21: u1 = 0b1,
10024 ftype: Ftype,
10025 decoded24: u5 = 0b11110,
10026 S: bool = false,
10027 decoded30: u1 = 0b0,
10028 M: u1 = 0b0,
10029 };
10030
10031 /// C7.2.158 FRINTI (scalar)
10032 pub const Frinti = packed struct {
10033 Rd: Register.Encoded,
10034 Rn: Register.Encoded,
10035 decoded10: u5 = 0b10000,
10036 rmode: Rmode = .i,
10037 decoded18: u3 = 0b001,
10038 decoded21: u1 = 0b1,
10039 ftype: Ftype,
10040 decoded24: u5 = 0b11110,
10041 S: bool = false,
10042 decoded30: u1 = 0b0,
10043 M: u1 = 0b0,
10044 };
10045
10046 pub const Rmode = enum(u3) {
10047 /// to nearest with ties to even
10048 n = 0b000,
10049 /// toward plus infinity
10050 p = 0b001,
10051 /// toward minus infinity
10052 m = 0b010,
10053 /// toward zero
10054 z = 0b011,
10055 /// to nearest with ties to away
10056 a = 0b100,
10057 /// exact, using current rounding mode
10058 x = 0b110,
10059 /// using current rounding mode
10060 i = 0b111,
10061 _,
10062 };
10063 };
10064
10065 /// Floating-point compare
10066 pub const FloatCompare = packed union {
10067 group: @This().Group,
10068 fcmp: Fcmp,
10069 fcmpe: Fcmpe,
10070
10071 pub const Group = packed struct {
10072 opcode2: u5,
10073 Rn: Register.Encoded,
10074 decoded10: u4 = 0b1000,
10075 op: u2,
10076 Rm: Register.Encoded,
10077 decoded21: u1 = 0b1,
10078 ptype: Ftype,
10079 decoded24: u5 = 0b11110,
10080 S: bool,
10081 decoded30: u1 = 0b0,
10082 M: u1,
10083 };
10084
10085 /// C7.2.66 FCMP
10086 pub const Fcmp = packed struct {
10087 decoded0: u3 = 0b000,
10088 opc0: Opc0,
10089 opc1: u1 = 0b0,
10090 Rn: Register.Encoded,
10091 decoded10: u4 = 0b1000,
10092 op: u2 = 0b00,
10093 Rm: Register.Encoded,
10094 decoded21: u1 = 0b1,
10095 ftype: Ftype,
10096 decoded24: u5 = 0b11110,
10097 S: bool = false,
10098 decoded30: u1 = 0b0,
10099 M: u1 = 0b0,
10100 };
10101
10102 /// C7.2.67 FCMPE
10103 pub const Fcmpe = packed struct {
10104 decoded0: u3 = 0b000,
10105 opc0: Opc0,
10106 opc1: u1 = 0b1,
10107 Rn: Register.Encoded,
10108 decoded10: u4 = 0b1000,
10109 op: u2 = 0b00,
10110 Rm: Register.Encoded,
10111 decoded21: u1 = 0b1,
10112 ftype: Ftype,
10113 decoded24: u5 = 0b11110,
10114 S: bool = false,
10115 decoded30: u1 = 0b0,
10116 M: u1 = 0b0,
10117 };
10118
10119 pub const Opc0 = enum(u1) {
10120 register = 0b00,
10121 zero = 0b01,
10122 };
10123 };
10124
10125 /// Floating-point immediate
10126 pub const FloatImmediate = packed union {
10127 group: @This().Group,
10128 fmov: Fmov,
10129
10130 pub const Group = packed struct {
10131 Rd: Register.Encoded,
10132 imm5: u5,
10133 decoded10: u3 = 0b100,
10134 imm8: u8,
10135 decoded21: u1 = 0b1,
10136 ptype: Ftype,
10137 decoded24: u5 = 0b11110,
10138 S: bool,
10139 decoded30: u1 = 0b0,
10140 M: u1,
10141 };
10142
10143 /// C7.2.132 FMOV (scalar, immediate)
10144 pub const Fmov = packed struct {
10145 Rd: Register.Encoded,
10146 imm5: u5 = 0b00000,
10147 decoded10: u3 = 0b100,
10148 imm8: u8,
10149 decoded21: u1 = 0b1,
10150 ftype: Ftype,
10151 decoded24: u5 = 0b11110,
10152 S: bool = false,
10153 decoded30: u1 = 0b0,
10154 M: u1 = 0b0,
10155 };
10156 };
10157
10158 /// Floating-point data-processing (2 source)
10159 pub const FloatDataProcessingTwoSource = packed union {
10160 group: @This().Group,
10161 fmul: Fmul,
10162 fdiv: Fdiv,
10163 fadd: Fadd,
10164 fsub: Fsub,
10165 fmax: Fmax,
10166 fmin: Fmin,
10167 fmaxnm: Fmaxnm,
10168 fminnm: Fminnm,
10169 fnmul: Fnmul,
10170
10171 pub const Group = packed struct {
10172 Rd: Register.Encoded,
10173 Rn: Register.Encoded,
10174 decoded10: u2 = 0b10,
10175 opcode: Opcode,
10176 Rm: Register.Encoded,
10177 decoded21: u1 = 0b1,
10178 ptype: Ftype,
10179 decoded24: u5 = 0b11110,
10180 S: bool,
10181 decoded30: u1 = 0b0,
10182 M: u1,
10183 };
10184
10185 /// C7.2.136 FMUL (scalar)
10186 pub const Fmul = packed struct {
10187 Rd: Register.Encoded,
10188 Rn: Register.Encoded,
10189 decoded10: u2 = 0b10,
10190 opcode: Opcode = .fmul,
10191 Rm: Register.Encoded,
10192 decoded21: u1 = 0b1,
10193 ftype: Ftype,
10194 decoded24: u5 = 0b11110,
10195 S: bool = false,
10196 decoded30: u1 = 0b0,
10197 M: u1 = 0b0,
10198 };
10199
10200 /// C7.2.98 FDIV (scalar)
10201 pub const Fdiv = packed struct {
10202 Rd: Register.Encoded,
10203 Rn: Register.Encoded,
10204 decoded10: u2 = 0b10,
10205 opcode: Opcode = .fdiv,
10206 Rm: Register.Encoded,
10207 decoded21: u1 = 0b1,
10208 ftype: Ftype,
10209 decoded24: u5 = 0b11110,
10210 S: bool = false,
10211 decoded30: u1 = 0b0,
10212 M: u1 = 0b0,
10213 };
10214
10215 /// C7.2.50 FADD (scalar)
10216 pub const Fadd = packed struct {
10217 Rd: Register.Encoded,
10218 Rn: Register.Encoded,
10219 decoded10: u2 = 0b10,
10220 opcode: Opcode = .fadd,
10221 Rm: Register.Encoded,
10222 decoded21: u1 = 0b1,
10223 ftype: Ftype,
10224 decoded24: u5 = 0b11110,
10225 S: bool = false,
10226 decoded30: u1 = 0b0,
10227 M: u1 = 0b0,
10228 };
10229
10230 /// C7.2.174 FSUB (scalar)
10231 pub const Fsub = packed struct {
10232 Rd: Register.Encoded,
10233 Rn: Register.Encoded,
10234 decoded10: u2 = 0b10,
10235 opcode: Opcode = .fsub,
10236 Rm: Register.Encoded,
10237 decoded21: u1 = 0b1,
10238 ftype: Ftype,
10239 decoded24: u5 = 0b11110,
10240 S: bool = false,
10241 decoded30: u1 = 0b0,
10242 M: u1 = 0b0,
10243 };
10244
10245 /// C7.2.102 FMAX (scalar)
10246 pub const Fmax = packed struct {
10247 Rd: Register.Encoded,
10248 Rn: Register.Encoded,
10249 decoded10: u2 = 0b10,
10250 opcode: Opcode = .fmax,
10251 Rm: Register.Encoded,
10252 decoded21: u1 = 0b1,
10253 ftype: Ftype,
10254 decoded24: u5 = 0b11110,
10255 S: bool = false,
10256 decoded30: u1 = 0b0,
10257 M: u1 = 0b0,
10258 };
10259
10260 /// C7.2.112 FMIN (scalar)
10261 pub const Fmin = packed struct {
10262 Rd: Register.Encoded,
10263 Rn: Register.Encoded,
10264 decoded10: u2 = 0b10,
10265 opcode: Opcode = .fmin,
10266 Rm: Register.Encoded,
10267 decoded21: u1 = 0b1,
10268 ftype: Ftype,
10269 decoded24: u5 = 0b11110,
10270 S: bool = false,
10271 decoded30: u1 = 0b0,
10272 M: u1 = 0b0,
10273 };
10274
10275 /// C7.2.104 FMAXNM (scalar)
10276 pub const Fmaxnm = packed struct {
10277 Rd: Register.Encoded,
10278 Rn: Register.Encoded,
10279 decoded10: u2 = 0b10,
10280 opcode: Opcode = .fmaxnm,
10281 Rm: Register.Encoded,
10282 decoded21: u1 = 0b1,
10283 ftype: Ftype,
10284 decoded24: u5 = 0b11110,
10285 S: bool = false,
10286 decoded30: u1 = 0b0,
10287 M: u1 = 0b0,
10288 };
10289
10290 /// C7.2.114 FMINNM (scalar)
10291 pub const Fminnm = packed struct {
10292 Rd: Register.Encoded,
10293 Rn: Register.Encoded,
10294 decoded10: u2 = 0b10,
10295 opcode: Opcode = .fminnm,
10296 Rm: Register.Encoded,
10297 decoded21: u1 = 0b1,
10298 ftype: Ftype,
10299 decoded24: u5 = 0b11110,
10300 S: bool = false,
10301 decoded30: u1 = 0b0,
10302 M: u1 = 0b0,
10303 };
10304
10305 /// C7.2.143 FNMUL (scalar)
10306 pub const Fnmul = packed struct {
10307 Rd: Register.Encoded,
10308 Rn: Register.Encoded,
10309 decoded10: u2 = 0b10,
10310 opcode: Opcode = .fnmul,
10311 Rm: Register.Encoded,
10312 decoded21: u1 = 0b1,
10313 ftype: Ftype,
10314 decoded24: u5 = 0b11110,
10315 S: bool = false,
10316 decoded30: u1 = 0b0,
10317 M: u1 = 0b0,
10318 };
10319
10320 pub const Opcode = enum(u4) {
10321 fmul = 0b0000,
10322 fdiv = 0b0001,
10323 fadd = 0b0010,
10324 fsub = 0b0011,
10325 fmax = 0b0100,
10326 fmin = 0b0101,
10327 fmaxnm = 0b0110,
10328 fminnm = 0b0111,
10329 fnmul = 0b1000,
10330 _,
10331 };
10332 };
10333
10334 /// Floating-point conditional select
10335 pub const FloatConditionalSelect = packed union {
10336 group: @This().Group,
10337 fcsel: Fcsel,
10338
10339 pub const Group = packed struct {
10340 Rd: Register.Encoded,
10341 Rn: Register.Encoded,
10342 decoded10: u2 = 0b11,
10343 cond: ConditionCode,
10344 Rm: Register.Encoded,
10345 decoded21: u1 = 0b1,
10346 ptype: Ftype,
10347 decoded24: u5 = 0b11110,
10348 S: bool,
10349 decoded30: u1 = 0b0,
10350 M: u1,
10351 };
10352
10353 /// C7.2.68 FCSEL
10354 pub const Fcsel = packed struct {
10355 Rd: Register.Encoded,
10356 Rn: Register.Encoded,
10357 decoded10: u2 = 0b11,
10358 cond: ConditionCode,
10359 Rm: Register.Encoded,
10360 decoded21: u1 = 0b1,
10361 ftype: Ftype,
10362 decoded24: u5 = 0b11110,
10363 S: bool = false,
10364 decoded30: u1 = 0b0,
10365 M: u1 = 0b0,
10366 };
10367
10368 pub const Decoded = union(enum) {
10369 unallocated,
10370 fcsel: Fcsel,
10371 };
10372 pub fn decode(inst: @This()) @This().Decoded {
10373 return switch (inst.group.ptype) {
10374 .quad => .unallocated,
10375 .single, .double, .half => switch (inst.group.S) {
10376 true => .unallocated,
10377 false => switch (inst.group.M) {
10378 0b0 => .{ .fcsel = inst.fcsel },
10379 0b1 => .unallocated,
10380 },
10381 },
10382 };
10383 }
10384 };
10385
10386 /// Floating-point data-processing (3 source)
10387 pub const FloatDataProcessingThreeSource = packed union {
10388 group: @This().Group,
10389 fmadd: Fmadd,
10390 fmsub: Fmsub,
10391 fnmadd: Fnmadd,
10392 fnmsub: Fnmsub,
10393
10394 pub const Group = packed struct {
10395 Rd: Register.Encoded,
10396 Rn: Register.Encoded,
10397 Ra: Register.Encoded,
10398 o0: AddSubtractOp,
10399 Rm: Register.Encoded,
10400 o1: u1,
10401 ptype: Ftype,
10402 decoded24: u5 = 0b11111,
10403 S: bool,
10404 decoded30: u1 = 0b0,
10405 M: u1,
10406 };
10407
10408 /// C7.2.100 FMADD
10409 pub const Fmadd = packed struct {
10410 Rd: Register.Encoded,
10411 Rn: Register.Encoded,
10412 Ra: Register.Encoded,
10413 o0: AddSubtractOp = .add,
10414 Rm: Register.Encoded,
10415 o1: O1 = .fm,
10416 ftype: Ftype,
10417 decoded24: u5 = 0b11111,
10418 S: bool = false,
10419 decoded30: u1 = 0b0,
10420 M: u1 = 0b0,
10421 };
10422
10423 /// C7.2.133 FMSUB
10424 pub const Fmsub = packed struct {
10425 Rd: Register.Encoded,
10426 Rn: Register.Encoded,
10427 Ra: Register.Encoded,
10428 o0: AddSubtractOp = .sub,
820010429 Rm: Register.Encoded,
820110430 o1: O1 = .fm,
820210431 ftype: Ftype,
......@@ -8242,42 +10471,81 @@ pub const Instruction = packed union {
824210471 };
824310472 };
824410473
8245 pub const Q = enum(u1) {
8246 double = 0b0,
8247 quad = 0b1,
8248 };
8249
825010474 pub const Size = enum(u2) {
825110475 byte = 0b00,
825210476 half = 0b01,
825310477 single = 0b10,
825410478 double = 0b11,
825510479
8256 pub fn toVectorSize(s: Size) Register.VectorSize {
8257 return switch (s) {
8258 .byte => .byte,
8259 .half => .half,
10480 pub fn toVectorSize(s: Size) Register.VectorSize {
10481 return switch (s) {
10482 .byte => .byte,
10483 .half => .half,
10484 .single => .single,
10485 .double => .double,
10486 };
10487 }
10488
10489 pub fn fromVectorSize(vs: Register.VectorSize) Size {
10490 return switch (vs) {
10491 else => unreachable,
10492 .byte => .byte,
10493 .half => .half,
10494 .single => .single,
10495 .double => .double,
10496 };
10497 }
10498 };
10499
10500 pub const Sz = enum(u1) {
10501 single = 0b0,
10502 double = 0b1,
10503
10504 pub fn toVectorSize(sz: Sz) Register.VectorSize {
10505 return switch (sz) {
10506 .single => .single,
10507 .double => .double,
10508 };
10509 }
10510
10511 pub fn fromVectorSize(vs: Register.VectorSize) Sz {
10512 return switch (vs) {
10513 else => unreachable,
10514 .single => .single,
10515 .double => .double,
10516 };
10517 }
10518 };
10519
10520 pub const Q = enum(u1) {
10521 double = 0b0,
10522 quad = 0b1,
10523 };
10524
10525 pub const Ftype = enum(u2) {
10526 single = 0b00,
10527 double = 0b01,
10528 quad = 0b10,
10529 half = 0b11,
10530
10531 pub fn toVectorSize(ftype: Ftype) Register.VectorSize {
10532 return switch (ftype) {
10533 _ => unreachable,
826010534 .single => .single,
826110535 .double => .double,
10536 .half => .half,
826210537 };
826310538 }
826410539
8265 pub fn fromVectorSize(vs: Register.VectorSize) Size {
10540 pub fn fromVectorSize(vs: Register.VectorSize) Ftype {
826610541 return switch (vs) {
8267 .byte => .byte,
8268 .half => .half,
10542 else => unreachable,
826910543 .single => .single,
827010544 .double => .double,
10545 .half => .half,
827110546 };
827210547 }
827310548 };
8274
8275 pub const Ftype = enum(u2) {
8276 single = 0b00,
8277 double = 0b01,
8278 quad = 0b10,
8279 half = 0b11,
8280 };
828110549 };
828210550
828310551 pub const AddSubtractOp = enum(u1) {
......@@ -8320,6 +10588,33 @@ pub const Instruction = packed union {
832010588 };
832110589 }
832210590
10591 /// C7.2.1 ABS (zero)
10592 pub fn abs(d: Register, n: Register) Instruction {
10593 switch (d.format) {
10594 else => unreachable,
10595 .scalar => |elem_size| {
10596 assert(elem_size == .double and elem_size == n.format.scalar);
10597 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
10598 .abs = .{
10599 .Rd = d.alias.encode(.{ .V = true }),
10600 .Rn = n.alias.encode(.{ .V = true }),
10601 .size = .fromVectorSize(elem_size),
10602 },
10603 } } };
10604 },
10605 .vector => |arrangement| {
10606 assert(arrangement != .@"1d" and n.format.vector == arrangement);
10607 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
10608 .abs = .{
10609 .Rd = d.alias.encode(.{ .V = true }),
10610 .Rn = n.alias.encode(.{ .V = true }),
10611 .size = arrangement.elemSize(),
10612 .Q = arrangement.size(),
10613 },
10614 } } };
10615 },
10616 }
10617 }
832310618 /// C6.2.1 ADC
832410619 pub fn adc(d: Register, n: Register, m: Register) Instruction {
832510620 const sf = d.format.integer;
......@@ -8867,6 +11162,45 @@ pub const Instruction = packed union {
886711162 } },
886811163 }
886911164 }
11165 /// C7.2.22 BIF
11166 pub fn bif(d: Register, n: Register, m: Register) Instruction {
11167 const arrangement = d.format.vector;
11168 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement and m.format.vector == arrangement);
11169 return .{ .data_processing_vector = .{ .simd_three_same = .{
11170 .bif = .{
11171 .Rd = d.alias.encode(.{ .V = true }),
11172 .Rn = n.alias.encode(.{ .V = true }),
11173 .Rm = m.alias.encode(.{ .V = true }),
11174 .Q = arrangement.size(),
11175 },
11176 } } };
11177 }
11178 /// C7.2.23 BIT
11179 pub fn bit(d: Register, n: Register, m: Register) Instruction {
11180 const arrangement = d.format.vector;
11181 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement and m.format.vector == arrangement);
11182 return .{ .data_processing_vector = .{ .simd_three_same = .{
11183 .bit = .{
11184 .Rd = d.alias.encode(.{ .V = true }),
11185 .Rn = n.alias.encode(.{ .V = true }),
11186 .Rm = m.alias.encode(.{ .V = true }),
11187 .Q = arrangement.size(),
11188 },
11189 } } };
11190 }
11191 /// C7.2.24 BSL
11192 pub fn bsl(d: Register, n: Register, m: Register) Instruction {
11193 const arrangement = d.format.vector;
11194 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement and m.format.vector == arrangement);
11195 return .{ .data_processing_vector = .{ .simd_three_same = .{
11196 .bsl = .{
11197 .Rd = d.alias.encode(.{ .V = true }),
11198 .Rn = n.alias.encode(.{ .V = true }),
11199 .Rm = m.alias.encode(.{ .V = true }),
11200 .Q = arrangement.size(),
11201 },
11202 } } };
11203 }
887011204 /// C6.2.34 BL
887111205 pub fn bl(label: i28) Instruction {
887211206 return .{ .branch_exception_generating_system = .{ .unconditional_branch_immediate = .{
......@@ -8999,6 +11333,151 @@ pub const Instruction = packed union {
899911333 },
900011334 } } };
900111335 }
11336 /// C7.2.28 CMEQ (zero)
11337 pub fn cmeq(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11338 switch (form) {
11339 .zero => switch (d.format) {
11340 else => unreachable,
11341 .scalar => |elem_size| {
11342 assert(elem_size == .double and elem_size == n.format.scalar);
11343 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11344 .cmeq = .{
11345 .Rd = d.alias.encode(.{ .V = true }),
11346 .Rn = n.alias.encode(.{ .V = true }),
11347 .size = .fromVectorSize(elem_size),
11348 },
11349 } } };
11350 },
11351 .vector => |arrangement| {
11352 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11353 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11354 .cmeq = .{
11355 .Rd = d.alias.encode(.{ .V = true }),
11356 .Rn = n.alias.encode(.{ .V = true }),
11357 .size = arrangement.elemSize(),
11358 .Q = arrangement.size(),
11359 },
11360 } } };
11361 },
11362 },
11363 }
11364 }
11365 /// C7.2.30 CMGE (zero)
11366 pub fn cmge(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11367 switch (form) {
11368 .zero => switch (d.format) {
11369 else => unreachable,
11370 .scalar => |elem_size| {
11371 assert(elem_size == .double and elem_size == n.format.scalar);
11372 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11373 .cmge = .{
11374 .Rd = d.alias.encode(.{ .V = true }),
11375 .Rn = n.alias.encode(.{ .V = true }),
11376 .size = .fromVectorSize(elem_size),
11377 },
11378 } } };
11379 },
11380 .vector => |arrangement| {
11381 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11382 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11383 .cmge = .{
11384 .Rd = d.alias.encode(.{ .V = true }),
11385 .Rn = n.alias.encode(.{ .V = true }),
11386 .size = arrangement.elemSize(),
11387 .Q = arrangement.size(),
11388 },
11389 } } };
11390 },
11391 },
11392 }
11393 }
11394 /// C7.2.32 CMGT (zero)
11395 pub fn cmgt(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11396 switch (form) {
11397 .zero => switch (d.format) {
11398 else => unreachable,
11399 .scalar => |elem_size| {
11400 assert(elem_size == .double and elem_size == n.format.scalar);
11401 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11402 .cmgt = .{
11403 .Rd = d.alias.encode(.{ .V = true }),
11404 .Rn = n.alias.encode(.{ .V = true }),
11405 .size = .fromVectorSize(elem_size),
11406 },
11407 } } };
11408 },
11409 .vector => |arrangement| {
11410 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11411 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11412 .cmgt = .{
11413 .Rd = d.alias.encode(.{ .V = true }),
11414 .Rn = n.alias.encode(.{ .V = true }),
11415 .size = arrangement.elemSize(),
11416 .Q = arrangement.size(),
11417 },
11418 } } };
11419 },
11420 },
11421 }
11422 }
11423 /// C7.2.35 CMLE (zero)
11424 pub fn cmle(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11425 switch (form) {
11426 .zero => switch (d.format) {
11427 else => unreachable,
11428 .scalar => |elem_size| {
11429 assert(elem_size == .double and elem_size == n.format.scalar);
11430 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11431 .cmle = .{
11432 .Rd = d.alias.encode(.{ .V = true }),
11433 .Rn = n.alias.encode(.{ .V = true }),
11434 .size = .fromVectorSize(elem_size),
11435 },
11436 } } };
11437 },
11438 .vector => |arrangement| {
11439 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11440 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11441 .cmle = .{
11442 .Rd = d.alias.encode(.{ .V = true }),
11443 .Rn = n.alias.encode(.{ .V = true }),
11444 .size = arrangement.elemSize(),
11445 .Q = arrangement.size(),
11446 },
11447 } } };
11448 },
11449 },
11450 }
11451 }
11452 /// C7.2.36 CMLT (zero)
11453 pub fn cmlt(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11454 switch (form) {
11455 .zero => switch (d.format) {
11456 else => unreachable,
11457 .scalar => |elem_size| {
11458 assert(elem_size == .double and elem_size == n.format.scalar);
11459 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11460 .cmlt = .{
11461 .Rd = d.alias.encode(.{ .V = true }),
11462 .Rn = n.alias.encode(.{ .V = true }),
11463 .size = .fromVectorSize(elem_size),
11464 },
11465 } } };
11466 },
11467 .vector => |arrangement| {
11468 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11469 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11470 .cmlt = .{
11471 .Rd = d.alias.encode(.{ .V = true }),
11472 .Rn = n.alias.encode(.{ .V = true }),
11473 .size = arrangement.elemSize(),
11474 .Q = arrangement.size(),
11475 },
11476 } } };
11477 },
11478 },
11479 }
11480 }
900211481 /// C7.2.38 CNT
900311482 pub fn cnt(d: Register, n: Register) Instruction {
900411483 const arrangement = d.format.vector;
......@@ -9094,6 +11573,57 @@ pub const Instruction = packed union {
909411573 },
909511574 } } };
909611575 }
11576 /// C7.2.39 DUP (element)
11577 /// C7.2.40 DUP (general)
11578 pub fn dup(d: Register, n: Register) Instruction {
11579 switch (d.format) {
11580 else => unreachable,
11581 .scalar => |elem_size| {
11582 assert(@intFromEnum(elem_size) <= @intFromEnum(Register.VectorSize.double) and elem_size == n.format.element.size);
11583 return .{ .data_processing_vector = .{ .simd_scalar_copy = .{
11584 .dup = .{
11585 .Rd = d.alias.encode(.{ .V = true }),
11586 .Rn = n.alias.encode(.{ .V = true }),
11587 .imm5 = @shlExact(@as(u5, n.format.element.index) << 1 | @as(u5, 0b1), @intFromEnum(elem_size)),
11588 },
11589 } } };
11590 },
11591 .vector => |arrangement| {
11592 assert(arrangement != .@"1d");
11593 const elem_size = arrangement.elemSize();
11594 switch (n.format) {
11595 else => unreachable,
11596 .element => |element| {
11597 assert(elem_size.toVectorSize() == element.size);
11598 return .{ .data_processing_vector = .{ .simd_copy = .{
11599 .dup = .{
11600 .Rd = d.alias.encode(.{ .V = true }),
11601 .Rn = n.alias.encode(.{ .V = true }),
11602 .imm4 = .element,
11603 .imm5 = @shlExact(@as(u5, element.index) << 1 | @as(u5, 0b1), @intFromEnum(elem_size)),
11604 .Q = arrangement.size(),
11605 },
11606 } } };
11607 },
11608 .integer => |sf| {
11609 assert(sf == @as(Register.IntegerSize, switch (elem_size) {
11610 .byte, .half, .single => .word,
11611 .double => .doubleword,
11612 }));
11613 return .{ .data_processing_vector = .{ .simd_copy = .{
11614 .dup = .{
11615 .Rd = d.alias.encode(.{ .V = true }),
11616 .Rn = n.alias.encode(.{}),
11617 .imm4 = .general,
11618 .imm5 = @shlExact(@as(u5, 0b1), @intFromEnum(elem_size)),
11619 .Q = arrangement.size(),
11620 },
11621 } } };
11622 },
11623 }
11624 },
11625 }
11626 }
909711627 /// C6.2.118 EON (shifted register)
909811628 pub fn eon(d: Register, n: Register, form: union(enum) {
909911629 register: Register,
......@@ -9180,72 +11710,343 @@ pub const Instruction = packed union {
918011710 } },
918111711 }
918211712 },
9183 .vector => |arrangement| {
9184 const m = form.register;
9185 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement and m.format.vector == arrangement);
9186 return .{ .data_processing_vector = .{ .simd_three_same = .{
9187 .eor = .{
9188 .Rd = d.alias.encode(.{ .V = true }),
9189 .Rn = n.alias.encode(.{ .V = true }),
9190 .Rm = m.alias.encode(.{ .V = true }),
9191 .Q = arrangement.size(),
11713 .vector => |arrangement| {
11714 const m = form.register;
11715 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement and m.format.vector == arrangement);
11716 return .{ .data_processing_vector = .{ .simd_three_same = .{
11717 .eor = .{
11718 .Rd = d.alias.encode(.{ .V = true }),
11719 .Rn = n.alias.encode(.{ .V = true }),
11720 .Rm = m.alias.encode(.{ .V = true }),
11721 .Q = arrangement.size(),
11722 },
11723 } } };
11724 },
11725 }
11726 }
11727 /// C6.2.124 EXTR
11728 pub fn extr(d: Register, n: Register, m: Register, lsb: u6) Instruction {
11729 const sf = d.format.integer;
11730 assert(n.format.integer == sf and m.format.integer == sf);
11731 return .{ .data_processing_immediate = .{ .extract = .{
11732 .extr = .{
11733 .Rd = d.alias.encode(.{}),
11734 .Rn = n.alias.encode(.{}),
11735 .imms = switch (sf) {
11736 .word => @as(u5, @intCast(lsb)),
11737 .doubleword => @as(u6, @intCast(lsb)),
11738 },
11739 .Rm = m.alias.encode(.{}),
11740 .N = sf,
11741 .sf = sf,
11742 },
11743 } } };
11744 }
11745 /// C7.2.45 FABS (vector)
11746 /// C7.2.46 FABS (scalar)
11747 pub fn fabs(d: Register, n: Register) Instruction {
11748 switch (d.format) {
11749 else => unreachable,
11750 .vector => |arrangement| {
11751 assert(n.format.vector == arrangement);
11752 switch (arrangement.elemSize()) {
11753 else => unreachable,
11754 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
11755 .fabs = .{
11756 .Rd = d.alias.encode(.{ .V = true }),
11757 .Rn = n.alias.encode(.{ .V = true }),
11758 .Q = arrangement.size(),
11759 },
11760 } } },
11761 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11762 .fabs = .{
11763 .Rd = d.alias.encode(.{ .V = true }),
11764 .Rn = n.alias.encode(.{ .V = true }),
11765 .sz = arrangement.elemSz(),
11766 .Q = arrangement.size(),
11767 },
11768 } } },
11769 }
11770 },
11771 .scalar => |ftype| {
11772 assert(n.format.scalar == ftype);
11773 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
11774 .fabs = .{
11775 .Rd = d.alias.encode(.{ .V = true }),
11776 .Rn = n.alias.encode(.{ .V = true }),
11777 .ftype = .fromVectorSize(ftype),
11778 },
11779 } } };
11780 },
11781 }
11782 }
11783 /// C7.2.50 FADD (scalar)
11784 pub fn fadd(d: Register, n: Register, m: Register) Instruction {
11785 const ftype = d.format.scalar;
11786 assert(n.format.scalar == ftype and m.format.scalar == ftype);
11787 return .{ .data_processing_vector = .{ .float_data_processing_two_source = .{
11788 .fadd = .{
11789 .Rd = d.alias.encode(.{ .V = true }),
11790 .Rn = n.alias.encode(.{ .V = true }),
11791 .Rm = m.alias.encode(.{ .V = true }),
11792 .ftype = .fromVectorSize(ftype),
11793 },
11794 } } };
11795 }
11796 /// C7.2.57 FCMEQ (zero)
11797 pub fn fcmeq(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11798 switch (form) {
11799 .zero => switch (d.format) {
11800 else => unreachable,
11801 .scalar => |ftype| switch (n.format) {
11802 else => unreachable,
11803 .scalar => |n_scalar| {
11804 assert(n_scalar == ftype);
11805 switch (ftype) {
11806 else => unreachable,
11807 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
11808 .fcmeq = .{
11809 .Rd = d.alias.encode(.{ .V = true }),
11810 .Rn = n.alias.encode(.{ .V = true }),
11811 },
11812 } } },
11813 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11814 .fcmeq = .{
11815 .Rd = d.alias.encode(.{ .V = true }),
11816 .Rn = n.alias.encode(.{ .V = true }),
11817 .sz = .fromVectorSize(ftype),
11818 },
11819 } } },
11820 }
11821 },
11822 },
11823 .vector => |arrangement| {
11824 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11825 switch (arrangement.elemSize()) {
11826 else => unreachable,
11827 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
11828 .fcmeq = .{
11829 .Rd = d.alias.encode(.{ .V = true }),
11830 .Rn = n.alias.encode(.{ .V = true }),
11831 .Q = arrangement.size(),
11832 },
11833 } } },
11834 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11835 .fcmeq = .{
11836 .Rd = d.alias.encode(.{ .V = true }),
11837 .Rn = n.alias.encode(.{ .V = true }),
11838 .sz = arrangement.elemSz(),
11839 .Q = arrangement.size(),
11840 },
11841 } } },
11842 }
11843 },
11844 },
11845 }
11846 }
11847 /// C7.2.59 FCMGE (zero)
11848 pub fn fcmge(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11849 switch (form) {
11850 .zero => switch (d.format) {
11851 else => unreachable,
11852 .scalar => |ftype| switch (n.format) {
11853 else => unreachable,
11854 .scalar => |n_scalar| {
11855 assert(n_scalar == ftype);
11856 switch (ftype) {
11857 else => unreachable,
11858 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
11859 .fcmge = .{
11860 .Rd = d.alias.encode(.{ .V = true }),
11861 .Rn = n.alias.encode(.{ .V = true }),
11862 },
11863 } } },
11864 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11865 .fcmge = .{
11866 .Rd = d.alias.encode(.{ .V = true }),
11867 .Rn = n.alias.encode(.{ .V = true }),
11868 .sz = .fromVectorSize(ftype),
11869 },
11870 } } },
11871 }
919211872 },
9193 } } };
11873 },
11874 .vector => |arrangement| {
11875 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11876 switch (arrangement.elemSize()) {
11877 else => unreachable,
11878 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
11879 .fcmge = .{
11880 .Rd = d.alias.encode(.{ .V = true }),
11881 .Rn = n.alias.encode(.{ .V = true }),
11882 .Q = arrangement.size(),
11883 },
11884 } } },
11885 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11886 .fcmge = .{
11887 .Rd = d.alias.encode(.{ .V = true }),
11888 .Rn = n.alias.encode(.{ .V = true }),
11889 .sz = arrangement.elemSz(),
11890 .Q = arrangement.size(),
11891 },
11892 } } },
11893 }
11894 },
919411895 },
919511896 }
919611897 }
9197 /// C6.2.124 EXTR
9198 pub fn extr(d: Register, n: Register, m: Register, lsb: u6) Instruction {
9199 const sf = d.format.integer;
9200 assert(n.format.integer == sf and m.format.integer == sf);
9201 return .{ .data_processing_immediate = .{ .extract = .{
9202 .extr = .{
9203 .Rd = d.alias.encode(.{}),
9204 .Rn = n.alias.encode(.{}),
9205 .imms = switch (sf) {
9206 .word => @as(u5, @intCast(lsb)),
9207 .doubleword => @as(u6, @intCast(lsb)),
11898 /// C7.2.61 FCMGT (zero)
11899 pub fn fcmgt(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11900 switch (form) {
11901 .zero => switch (d.format) {
11902 else => unreachable,
11903 .scalar => |ftype| switch (n.format) {
11904 else => unreachable,
11905 .scalar => |n_scalar| {
11906 assert(n_scalar == ftype);
11907 switch (ftype) {
11908 else => unreachable,
11909 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
11910 .fcmgt = .{
11911 .Rd = d.alias.encode(.{ .V = true }),
11912 .Rn = n.alias.encode(.{ .V = true }),
11913 },
11914 } } },
11915 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11916 .fcmgt = .{
11917 .Rd = d.alias.encode(.{ .V = true }),
11918 .Rn = n.alias.encode(.{ .V = true }),
11919 .sz = .fromVectorSize(ftype),
11920 },
11921 } } },
11922 }
11923 },
11924 },
11925 .vector => |arrangement| {
11926 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11927 switch (arrangement.elemSize()) {
11928 else => unreachable,
11929 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
11930 .fcmgt = .{
11931 .Rd = d.alias.encode(.{ .V = true }),
11932 .Rn = n.alias.encode(.{ .V = true }),
11933 .Q = arrangement.size(),
11934 },
11935 } } },
11936 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11937 .fcmgt = .{
11938 .Rd = d.alias.encode(.{ .V = true }),
11939 .Rn = n.alias.encode(.{ .V = true }),
11940 .sz = arrangement.elemSz(),
11941 .Q = arrangement.size(),
11942 },
11943 } } },
11944 }
920811945 },
9209 .Rm = m.alias.encode(.{}),
9210 .N = sf,
9211 .sf = sf,
921211946 },
9213 } } };
11947 }
921411948 }
9215 /// C7.2.46 FABS (scalar)
9216 pub fn fabs(d: Register, n: Register) Instruction {
9217 const ftype = d.format.scalar;
9218 assert(n.format.scalar == ftype);
9219 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9220 .fabs = .{
9221 .Rd = d.alias.encode(.{ .V = true }),
9222 .Rn = n.alias.encode(.{ .V = true }),
9223 .ftype = switch (ftype) {
11949 /// C7.2.64 FCMLE (zero)
11950 pub fn fcmle(d: Register, n: Register, form: union(enum) { zero }) Instruction {
11951 switch (form) {
11952 .zero => switch (d.format) {
11953 else => unreachable,
11954 .scalar => |ftype| switch (n.format) {
922411955 else => unreachable,
9225 .single => .single,
9226 .double => .double,
9227 .half => .half,
11956 .scalar => |n_scalar| {
11957 assert(n_scalar == ftype);
11958 switch (ftype) {
11959 else => unreachable,
11960 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
11961 .fcmle = .{
11962 .Rd = d.alias.encode(.{ .V = true }),
11963 .Rn = n.alias.encode(.{ .V = true }),
11964 },
11965 } } },
11966 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
11967 .fcmle = .{
11968 .Rd = d.alias.encode(.{ .V = true }),
11969 .Rn = n.alias.encode(.{ .V = true }),
11970 .sz = .fromVectorSize(ftype),
11971 },
11972 } } },
11973 }
11974 },
11975 },
11976 .vector => |arrangement| {
11977 assert(arrangement != .@"1d" and n.format.vector == arrangement);
11978 switch (arrangement.elemSize()) {
11979 else => unreachable,
11980 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
11981 .fcmle = .{
11982 .Rd = d.alias.encode(.{ .V = true }),
11983 .Rn = n.alias.encode(.{ .V = true }),
11984 .Q = arrangement.size(),
11985 },
11986 } } },
11987 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
11988 .fcmle = .{
11989 .Rd = d.alias.encode(.{ .V = true }),
11990 .Rn = n.alias.encode(.{ .V = true }),
11991 .sz = arrangement.elemSz(),
11992 .Q = arrangement.size(),
11993 },
11994 } } },
11995 }
922811996 },
922911997 },
9230 } } };
11998 }
923111999 }
9232 /// C7.2.50 FADD (scalar)
9233 pub fn fadd(d: Register, n: Register, m: Register) Instruction {
9234 const ftype = d.format.scalar;
9235 assert(n.format.scalar == ftype and m.format.scalar == ftype);
9236 return .{ .data_processing_vector = .{ .float_data_processing_two_source = .{
9237 .fadd = .{
9238 .Rd = d.alias.encode(.{ .V = true }),
9239 .Rn = n.alias.encode(.{ .V = true }),
9240 .Rm = m.alias.encode(.{ .V = true }),
9241 .ftype = switch (ftype) {
12000 /// C7.2.65 FCMLT (zero)
12001 pub fn fcmlt(d: Register, n: Register, form: union(enum) { zero }) Instruction {
12002 switch (form) {
12003 .zero => switch (d.format) {
12004 else => unreachable,
12005 .scalar => |ftype| switch (n.format) {
924212006 else => unreachable,
9243 .single => .single,
9244 .double => .double,
9245 .half => .half,
12007 .scalar => |n_scalar| {
12008 assert(n_scalar == ftype);
12009 switch (ftype) {
12010 else => unreachable,
12011 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12012 .fcmlt = .{
12013 .Rd = d.alias.encode(.{ .V = true }),
12014 .Rn = n.alias.encode(.{ .V = true }),
12015 },
12016 } } },
12017 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12018 .fcmlt = .{
12019 .Rd = d.alias.encode(.{ .V = true }),
12020 .Rn = n.alias.encode(.{ .V = true }),
12021 .sz = .fromVectorSize(ftype),
12022 },
12023 } } },
12024 }
12025 },
12026 },
12027 .vector => |arrangement| {
12028 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12029 switch (arrangement.elemSize()) {
12030 else => unreachable,
12031 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12032 .fcmlt = .{
12033 .Rd = d.alias.encode(.{ .V = true }),
12034 .Rn = n.alias.encode(.{ .V = true }),
12035 .Q = arrangement.size(),
12036 },
12037 } } },
12038 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12039 .fcmlt = .{
12040 .Rd = d.alias.encode(.{ .V = true }),
12041 .Rn = n.alias.encode(.{ .V = true }),
12042 .sz = arrangement.elemSz(),
12043 .Q = arrangement.size(),
12044 },
12045 } } },
12046 }
924612047 },
924712048 },
9248 } } };
12049 }
924912050 }
925012051 /// C7.2.66 FCMP
925112052 pub fn fcmp(n: Register, form: union(enum) { register: Register, zero }) Instruction {
......@@ -9258,12 +12059,7 @@ pub const Instruction = packed union {
925812059 .opc0 = .register,
925912060 .Rn = n.alias.encode(.{ .V = true }),
926012061 .Rm = m.alias.encode(.{ .V = true }),
9261 .ftype = switch (ftype) {
9262 else => unreachable,
9263 .single => .single,
9264 .double => .double,
9265 .half => .half,
9266 },
12062 .ftype = .fromVectorSize(ftype),
926712063 },
926812064 } } };
926912065 },
......@@ -9272,12 +12068,7 @@ pub const Instruction = packed union {
927212068 .opc0 = .register,
927312069 .Rn = n.alias.encode(.{ .V = true }),
927412070 .Rm = @enumFromInt(0b00000),
9275 .ftype = switch (ftype) {
9276 else => unreachable,
9277 .single => .single,
9278 .double => .double,
9279 .half => .half,
9280 },
12071 .ftype = .fromVectorSize(ftype),
928112072 },
928212073 } } },
928312074 }
......@@ -9293,12 +12084,7 @@ pub const Instruction = packed union {
929312084 .opc0 = .zero,
929412085 .Rn = n.alias.encode(.{ .V = true }),
929512086 .Rm = m.alias.encode(.{ .V = true }),
9296 .ftype = switch (ftype) {
9297 else => unreachable,
9298 .single => .single,
9299 .double => .double,
9300 .half => .half,
9301 },
12087 .ftype = .fromVectorSize(ftype),
930212088 },
930312089 } } };
930412090 },
......@@ -9307,16 +12093,25 @@ pub const Instruction = packed union {
930712093 .opc0 = .zero,
930812094 .Rn = n.alias.encode(.{ .V = true }),
930912095 .Rm = @enumFromInt(0b00000),
9310 .ftype = switch (ftype) {
9311 else => unreachable,
9312 .single => .single,
9313 .double => .double,
9314 .half => .half,
9315 },
12096 .ftype = .fromVectorSize(ftype),
931612097 },
931712098 } } },
931812099 }
931912100 }
12101 /// C7.2.68 FCSEL
12102 pub fn fcsel(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
12103 const ftype = d.format.scalar;
12104 assert(n.format.scalar == ftype and m.format.scalar == ftype);
12105 return .{ .data_processing_vector = .{ .float_conditional_select = .{
12106 .fcsel = .{
12107 .Rd = d.alias.encode(.{ .V = true }),
12108 .Rn = n.alias.encode(.{ .V = true }),
12109 .cond = cond,
12110 .Rm = m.alias.encode(.{ .V = true }),
12111 .ftype = .fromVectorSize(ftype),
12112 },
12113 } } };
12114 }
932012115 /// C7.2.69 FCVT
932112116 pub fn fcvt(d: Register, n: Register) Instruction {
932212117 assert(d.format.scalar != n.format.scalar);
......@@ -9330,174 +12125,589 @@ pub const Instruction = packed union {
933012125 .double => .double,
933112126 .half => .half,
933212127 },
9333 .ftype = switch (n.format.scalar) {
9334 else => unreachable,
9335 .single => .single,
9336 .double => .double,
9337 .half => .half,
9338 },
12128 .ftype = .fromVectorSize(n.format.scalar),
933912129 },
934012130 } } };
934112131 }
12132 /// C7.2.70 FCVTAS (vector)
934212133 /// C7.2.71 FCVTAS (scalar)
934312134 pub fn fcvtas(d: Register, n: Register) Instruction {
9344 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9345 .fcvtas = .{
9346 .Rd = d.alias.encode(.{}),
9347 .Rn = n.alias.encode(.{ .V = true }),
9348 .ftype = switch (n.format.scalar) {
9349 else => unreachable,
9350 .single => .single,
9351 .double => .double,
9352 .half => .half,
12135 switch (d.format) {
12136 else => unreachable,
12137 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12138 .fcvtas = .{
12139 .Rd = d.alias.encode(.{}),
12140 .Rn = n.alias.encode(.{ .V = true }),
12141 .ftype = .fromVectorSize(n.format.scalar),
12142 .sf = sf,
12143 },
12144 } } },
12145 .scalar => |elem_size| switch (n.format) {
12146 else => unreachable,
12147 .scalar => |ftype| {
12148 assert(ftype == elem_size);
12149 switch (elem_size) {
12150 else => unreachable,
12151 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12152 .fcvtas = .{
12153 .Rd = d.alias.encode(.{ .V = true }),
12154 .Rn = n.alias.encode(.{ .V = true }),
12155 },
12156 } } },
12157 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12158 .fcvtas = .{
12159 .Rd = d.alias.encode(.{ .V = true }),
12160 .Rn = n.alias.encode(.{ .V = true }),
12161 .sz = .fromVectorSize(elem_size),
12162 },
12163 } } },
12164 }
935312165 },
9354 .sf = d.format.integer,
935512166 },
9356 } } };
12167 .vector => |arrangement| {
12168 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12169 switch (arrangement.elemSize()) {
12170 else => unreachable,
12171 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12172 .fcvtas = .{
12173 .Rd = d.alias.encode(.{ .V = true }),
12174 .Rn = n.alias.encode(.{ .V = true }),
12175 .Q = arrangement.size(),
12176 },
12177 } } },
12178 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12179 .fcvtas = .{
12180 .Rd = d.alias.encode(.{ .V = true }),
12181 .Rn = n.alias.encode(.{ .V = true }),
12182 .sz = arrangement.elemSz(),
12183 .Q = arrangement.size(),
12184 },
12185 } } },
12186 }
12187 },
12188 }
935712189 }
12190 /// C7.2.72 FCVTAU (vector)
935812191 /// C7.2.73 FCVTAU (scalar)
935912192 pub fn fcvtau(d: Register, n: Register) Instruction {
9360 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9361 .fcvtau = .{
9362 .Rd = d.alias.encode(.{}),
9363 .Rn = n.alias.encode(.{ .V = true }),
9364 .ftype = switch (n.format.scalar) {
9365 else => unreachable,
9366 .single => .single,
9367 .double => .double,
9368 .half => .half,
12193 switch (d.format) {
12194 else => unreachable,
12195 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12196 .fcvtau = .{
12197 .Rd = d.alias.encode(.{}),
12198 .Rn = n.alias.encode(.{ .V = true }),
12199 .ftype = .fromVectorSize(n.format.scalar),
12200 .sf = sf,
12201 },
12202 } } },
12203 .scalar => |elem_size| switch (n.format) {
12204 else => unreachable,
12205 .scalar => |ftype| {
12206 assert(ftype == elem_size);
12207 switch (elem_size) {
12208 else => unreachable,
12209 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12210 .fcvtau = .{
12211 .Rd = d.alias.encode(.{ .V = true }),
12212 .Rn = n.alias.encode(.{ .V = true }),
12213 },
12214 } } },
12215 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12216 .fcvtau = .{
12217 .Rd = d.alias.encode(.{ .V = true }),
12218 .Rn = n.alias.encode(.{ .V = true }),
12219 .sz = .fromVectorSize(elem_size),
12220 },
12221 } } },
12222 }
936912223 },
9370 .sf = d.format.integer,
937112224 },
9372 } } };
12225 .vector => |arrangement| {
12226 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12227 switch (arrangement.elemSize()) {
12228 else => unreachable,
12229 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12230 .fcvtau = .{
12231 .Rd = d.alias.encode(.{ .V = true }),
12232 .Rn = n.alias.encode(.{ .V = true }),
12233 .Q = arrangement.size(),
12234 },
12235 } } },
12236 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12237 .fcvtau = .{
12238 .Rd = d.alias.encode(.{ .V = true }),
12239 .Rn = n.alias.encode(.{ .V = true }),
12240 .sz = arrangement.elemSz(),
12241 .Q = arrangement.size(),
12242 },
12243 } } },
12244 }
12245 },
12246 }
937312247 }
12248 /// C7.2.75 FCVTMS (vector)
937412249 /// C7.2.76 FCVTMS (scalar)
937512250 pub fn fcvtms(d: Register, n: Register) Instruction {
9376 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9377 .fcvtms = .{
9378 .Rd = d.alias.encode(.{}),
9379 .Rn = n.alias.encode(.{ .V = true }),
9380 .ftype = switch (n.format.scalar) {
9381 else => unreachable,
9382 .single => .single,
9383 .double => .double,
9384 .half => .half,
12251 switch (d.format) {
12252 else => unreachable,
12253 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12254 .fcvtms = .{
12255 .Rd = d.alias.encode(.{}),
12256 .Rn = n.alias.encode(.{ .V = true }),
12257 .ftype = .fromVectorSize(n.format.scalar),
12258 .sf = sf,
12259 },
12260 } } },
12261 .scalar => |elem_size| switch (n.format) {
12262 else => unreachable,
12263 .scalar => |ftype| {
12264 assert(ftype == elem_size);
12265 switch (elem_size) {
12266 else => unreachable,
12267 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12268 .fcvtms = .{
12269 .Rd = d.alias.encode(.{ .V = true }),
12270 .Rn = n.alias.encode(.{ .V = true }),
12271 },
12272 } } },
12273 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12274 .fcvtms = .{
12275 .Rd = d.alias.encode(.{ .V = true }),
12276 .Rn = n.alias.encode(.{ .V = true }),
12277 .sz = .fromVectorSize(elem_size),
12278 },
12279 } } },
12280 }
938512281 },
9386 .sf = d.format.integer,
938712282 },
9388 } } };
12283 .vector => |arrangement| {
12284 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12285 switch (arrangement.elemSize()) {
12286 else => unreachable,
12287 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12288 .fcvtms = .{
12289 .Rd = d.alias.encode(.{ .V = true }),
12290 .Rn = n.alias.encode(.{ .V = true }),
12291 .Q = arrangement.size(),
12292 },
12293 } } },
12294 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12295 .fcvtms = .{
12296 .Rd = d.alias.encode(.{ .V = true }),
12297 .Rn = n.alias.encode(.{ .V = true }),
12298 .sz = arrangement.elemSz(),
12299 .Q = arrangement.size(),
12300 },
12301 } } },
12302 }
12303 },
12304 }
938912305 }
12306 /// C7.2.77 FCVTMU (vector)
939012307 /// C7.2.78 FCVTMU (scalar)
939112308 pub fn fcvtmu(d: Register, n: Register) Instruction {
9392 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9393 .fcvtmu = .{
9394 .Rd = d.alias.encode(.{}),
9395 .Rn = n.alias.encode(.{ .V = true }),
9396 .ftype = switch (n.format.scalar) {
9397 else => unreachable,
9398 .single => .single,
9399 .double => .double,
9400 .half => .half,
12309 switch (d.format) {
12310 else => unreachable,
12311 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12312 .fcvtmu = .{
12313 .Rd = d.alias.encode(.{}),
12314 .Rn = n.alias.encode(.{ .V = true }),
12315 .ftype = .fromVectorSize(n.format.scalar),
12316 .sf = sf,
12317 },
12318 } } },
12319 .scalar => |elem_size| switch (n.format) {
12320 else => unreachable,
12321 .scalar => |ftype| {
12322 assert(ftype == elem_size);
12323 switch (elem_size) {
12324 else => unreachable,
12325 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12326 .fcvtmu = .{
12327 .Rd = d.alias.encode(.{ .V = true }),
12328 .Rn = n.alias.encode(.{ .V = true }),
12329 },
12330 } } },
12331 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12332 .fcvtmu = .{
12333 .Rd = d.alias.encode(.{ .V = true }),
12334 .Rn = n.alias.encode(.{ .V = true }),
12335 .sz = .fromVectorSize(elem_size),
12336 },
12337 } } },
12338 }
940112339 },
9402 .sf = d.format.integer,
940312340 },
9404 } } };
12341 .vector => |arrangement| {
12342 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12343 switch (arrangement.elemSize()) {
12344 else => unreachable,
12345 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12346 .fcvtmu = .{
12347 .Rd = d.alias.encode(.{ .V = true }),
12348 .Rn = n.alias.encode(.{ .V = true }),
12349 .Q = arrangement.size(),
12350 },
12351 } } },
12352 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12353 .fcvtmu = .{
12354 .Rd = d.alias.encode(.{ .V = true }),
12355 .Rn = n.alias.encode(.{ .V = true }),
12356 .sz = arrangement.elemSz(),
12357 .Q = arrangement.size(),
12358 },
12359 } } },
12360 }
12361 },
12362 }
940512363 }
12364 /// C7.2.80 FCVTNS (vector)
940612365 /// C7.2.81 FCVTNS (scalar)
940712366 pub fn fcvtns(d: Register, n: Register) Instruction {
9408 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9409 .fcvtns = .{
9410 .Rd = d.alias.encode(.{}),
9411 .Rn = n.alias.encode(.{ .V = true }),
9412 .ftype = switch (n.format.scalar) {
9413 else => unreachable,
9414 .single => .single,
9415 .double => .double,
9416 .half => .half,
12367 switch (d.format) {
12368 else => unreachable,
12369 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12370 .fcvtns = .{
12371 .Rd = d.alias.encode(.{}),
12372 .Rn = n.alias.encode(.{ .V = true }),
12373 .ftype = .fromVectorSize(n.format.scalar),
12374 .sf = sf,
12375 },
12376 } } },
12377 .scalar => |elem_size| switch (n.format) {
12378 else => unreachable,
12379 .scalar => |ftype| {
12380 assert(ftype == elem_size);
12381 switch (elem_size) {
12382 else => unreachable,
12383 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12384 .fcvtns = .{
12385 .Rd = d.alias.encode(.{ .V = true }),
12386 .Rn = n.alias.encode(.{ .V = true }),
12387 },
12388 } } },
12389 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12390 .fcvtns = .{
12391 .Rd = d.alias.encode(.{ .V = true }),
12392 .Rn = n.alias.encode(.{ .V = true }),
12393 .sz = .fromVectorSize(elem_size),
12394 },
12395 } } },
12396 }
941712397 },
9418 .sf = d.format.integer,
941912398 },
9420 } } };
12399 .vector => |arrangement| {
12400 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12401 switch (arrangement.elemSize()) {
12402 else => unreachable,
12403 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12404 .fcvtns = .{
12405 .Rd = d.alias.encode(.{ .V = true }),
12406 .Rn = n.alias.encode(.{ .V = true }),
12407 .Q = arrangement.size(),
12408 },
12409 } } },
12410 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12411 .fcvtns = .{
12412 .Rd = d.alias.encode(.{ .V = true }),
12413 .Rn = n.alias.encode(.{ .V = true }),
12414 .sz = arrangement.elemSz(),
12415 .Q = arrangement.size(),
12416 },
12417 } } },
12418 }
12419 },
12420 }
942112421 }
12422 /// C7.2.82 FCVTNU (vector)
942212423 /// C7.2.83 FCVTNU (scalar)
942312424 pub fn fcvtnu(d: Register, n: Register) Instruction {
9424 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9425 .fcvtnu = .{
9426 .Rd = d.alias.encode(.{}),
9427 .Rn = n.alias.encode(.{ .V = true }),
9428 .ftype = switch (n.format.scalar) {
9429 else => unreachable,
9430 .single => .single,
9431 .double => .double,
9432 .half => .half,
12425 switch (d.format) {
12426 else => unreachable,
12427 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12428 .fcvtnu = .{
12429 .Rd = d.alias.encode(.{}),
12430 .Rn = n.alias.encode(.{ .V = true }),
12431 .ftype = .fromVectorSize(n.format.scalar),
12432 .sf = sf,
12433 },
12434 } } },
12435 .scalar => |elem_size| switch (n.format) {
12436 else => unreachable,
12437 .scalar => |ftype| {
12438 assert(ftype == elem_size);
12439 switch (elem_size) {
12440 else => unreachable,
12441 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12442 .fcvtnu = .{
12443 .Rd = d.alias.encode(.{ .V = true }),
12444 .Rn = n.alias.encode(.{ .V = true }),
12445 },
12446 } } },
12447 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12448 .fcvtnu = .{
12449 .Rd = d.alias.encode(.{ .V = true }),
12450 .Rn = n.alias.encode(.{ .V = true }),
12451 .sz = .fromVectorSize(elem_size),
12452 },
12453 } } },
12454 }
943312455 },
9434 .sf = d.format.integer,
943512456 },
9436 } } };
12457 .vector => |arrangement| {
12458 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12459 switch (arrangement.elemSize()) {
12460 else => unreachable,
12461 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12462 .fcvtnu = .{
12463 .Rd = d.alias.encode(.{ .V = true }),
12464 .Rn = n.alias.encode(.{ .V = true }),
12465 .Q = arrangement.size(),
12466 },
12467 } } },
12468 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12469 .fcvtnu = .{
12470 .Rd = d.alias.encode(.{ .V = true }),
12471 .Rn = n.alias.encode(.{ .V = true }),
12472 .sz = arrangement.elemSz(),
12473 .Q = arrangement.size(),
12474 },
12475 } } },
12476 }
12477 },
12478 }
943712479 }
12480 /// C7.2.84 FCVTPS (vector)
943812481 /// C7.2.85 FCVTPS (scalar)
943912482 pub fn fcvtps(d: Register, n: Register) Instruction {
9440 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9441 .fcvtps = .{
9442 .Rd = d.alias.encode(.{}),
9443 .Rn = n.alias.encode(.{ .V = true }),
9444 .ftype = switch (n.format.scalar) {
9445 else => unreachable,
9446 .single => .single,
9447 .double => .double,
9448 .half => .half,
12483 switch (d.format) {
12484 else => unreachable,
12485 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12486 .fcvtps = .{
12487 .Rd = d.alias.encode(.{}),
12488 .Rn = n.alias.encode(.{ .V = true }),
12489 .ftype = .fromVectorSize(n.format.scalar),
12490 .sf = sf,
12491 },
12492 } } },
12493 .scalar => |elem_size| switch (n.format) {
12494 else => unreachable,
12495 .scalar => |ftype| {
12496 assert(ftype == elem_size);
12497 switch (elem_size) {
12498 else => unreachable,
12499 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12500 .fcvtps = .{
12501 .Rd = d.alias.encode(.{ .V = true }),
12502 .Rn = n.alias.encode(.{ .V = true }),
12503 },
12504 } } },
12505 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12506 .fcvtps = .{
12507 .Rd = d.alias.encode(.{ .V = true }),
12508 .Rn = n.alias.encode(.{ .V = true }),
12509 .sz = .fromVectorSize(elem_size),
12510 },
12511 } } },
12512 }
944912513 },
9450 .sf = d.format.integer,
945112514 },
9452 } } };
12515 .vector => |arrangement| {
12516 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12517 switch (arrangement.elemSize()) {
12518 else => unreachable,
12519 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12520 .fcvtps = .{
12521 .Rd = d.alias.encode(.{ .V = true }),
12522 .Rn = n.alias.encode(.{ .V = true }),
12523 .Q = arrangement.size(),
12524 },
12525 } } },
12526 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12527 .fcvtps = .{
12528 .Rd = d.alias.encode(.{ .V = true }),
12529 .Rn = n.alias.encode(.{ .V = true }),
12530 .sz = arrangement.elemSz(),
12531 .Q = arrangement.size(),
12532 },
12533 } } },
12534 }
12535 },
12536 }
945312537 }
12538 /// C7.2.86 FCVTPU (vector)
945412539 /// C7.2.87 FCVTPU (scalar)
945512540 pub fn fcvtpu(d: Register, n: Register) Instruction {
9456 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9457 .fcvtpu = .{
9458 .Rd = d.alias.encode(.{}),
9459 .Rn = n.alias.encode(.{ .V = true }),
9460 .ftype = switch (n.format.scalar) {
9461 else => unreachable,
9462 .single => .single,
9463 .double => .double,
9464 .half => .half,
12541 switch (d.format) {
12542 else => unreachable,
12543 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12544 .fcvtpu = .{
12545 .Rd = d.alias.encode(.{}),
12546 .Rn = n.alias.encode(.{ .V = true }),
12547 .ftype = .fromVectorSize(n.format.scalar),
12548 .sf = sf,
12549 },
12550 } } },
12551 .scalar => |elem_size| switch (n.format) {
12552 else => unreachable,
12553 .scalar => |ftype| {
12554 assert(ftype == elem_size);
12555 switch (elem_size) {
12556 else => unreachable,
12557 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12558 .fcvtpu = .{
12559 .Rd = d.alias.encode(.{ .V = true }),
12560 .Rn = n.alias.encode(.{ .V = true }),
12561 },
12562 } } },
12563 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12564 .fcvtpu = .{
12565 .Rd = d.alias.encode(.{ .V = true }),
12566 .Rn = n.alias.encode(.{ .V = true }),
12567 .sz = .fromVectorSize(elem_size),
12568 },
12569 } } },
12570 }
946512571 },
9466 .sf = d.format.integer,
946712572 },
9468 } } };
12573 .vector => |arrangement| {
12574 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12575 switch (arrangement.elemSize()) {
12576 else => unreachable,
12577 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12578 .fcvtpu = .{
12579 .Rd = d.alias.encode(.{ .V = true }),
12580 .Rn = n.alias.encode(.{ .V = true }),
12581 .Q = arrangement.size(),
12582 },
12583 } } },
12584 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12585 .fcvtpu = .{
12586 .Rd = d.alias.encode(.{ .V = true }),
12587 .Rn = n.alias.encode(.{ .V = true }),
12588 .sz = arrangement.elemSz(),
12589 .Q = arrangement.size(),
12590 },
12591 } } },
12592 }
12593 },
12594 }
946912595 }
12596 /// C7.2.90 FCVTZS (vector, integer)
947012597 /// C7.2.92 FCVTZS (scalar, integer)
947112598 pub fn fcvtzs(d: Register, n: Register) Instruction {
9472 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9473 .fcvtzs = .{
9474 .Rd = d.alias.encode(.{}),
9475 .Rn = n.alias.encode(.{ .V = true }),
9476 .ftype = switch (n.format.scalar) {
12599 switch (d.format) {
12600 else => unreachable,
12601 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12602 .fcvtzs = .{
12603 .Rd = d.alias.encode(.{}),
12604 .Rn = n.alias.encode(.{ .V = true }),
12605 .ftype = .fromVectorSize(n.format.scalar),
12606 .sf = sf,
12607 },
12608 } } },
12609 .scalar => |elem_size| switch (n.format) {
12610 else => unreachable,
12611 .scalar => |ftype| {
12612 assert(ftype == elem_size);
12613 switch (elem_size) {
12614 else => unreachable,
12615 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12616 .fcvtzs = .{
12617 .Rd = d.alias.encode(.{ .V = true }),
12618 .Rn = n.alias.encode(.{ .V = true }),
12619 },
12620 } } },
12621 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12622 .fcvtzs = .{
12623 .Rd = d.alias.encode(.{ .V = true }),
12624 .Rn = n.alias.encode(.{ .V = true }),
12625 .sz = .fromVectorSize(elem_size),
12626 },
12627 } } },
12628 }
12629 },
12630 },
12631 .vector => |arrangement| {
12632 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12633 switch (arrangement.elemSize()) {
947712634 else => unreachable,
9478 .single => .single,
9479 .double => .double,
9480 .half => .half,
12635 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12636 .fcvtzs = .{
12637 .Rd = d.alias.encode(.{ .V = true }),
12638 .Rn = n.alias.encode(.{ .V = true }),
12639 .Q = arrangement.size(),
12640 },
12641 } } },
12642 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12643 .fcvtzs = .{
12644 .Rd = d.alias.encode(.{ .V = true }),
12645 .Rn = n.alias.encode(.{ .V = true }),
12646 .sz = arrangement.elemSz(),
12647 .Q = arrangement.size(),
12648 },
12649 } } },
12650 }
12651 },
12652 }
12653 }
12654 /// C7.2.94 FCVTZU (vector, integer)
12655 /// C7.2.96 FCVTZU (scalar, integer)
12656 pub fn fcvtzu(d: Register, n: Register) Instruction {
12657 switch (d.format) {
12658 else => unreachable,
12659 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12660 .fcvtzu = .{
12661 .Rd = d.alias.encode(.{}),
12662 .Rn = n.alias.encode(.{ .V = true }),
12663 .ftype = .fromVectorSize(n.format.scalar),
12664 .sf = sf,
12665 },
12666 } } },
12667 .scalar => |elem_size| switch (n.format) {
12668 else => unreachable,
12669 .scalar => |ftype| {
12670 assert(ftype == elem_size);
12671 switch (elem_size) {
12672 else => unreachable,
12673 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
12674 .fcvtzu = .{
12675 .Rd = d.alias.encode(.{ .V = true }),
12676 .Rn = n.alias.encode(.{ .V = true }),
12677 },
12678 } } },
12679 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
12680 .fcvtzu = .{
12681 .Rd = d.alias.encode(.{ .V = true }),
12682 .Rn = n.alias.encode(.{ .V = true }),
12683 .sz = .fromVectorSize(elem_size),
12684 },
12685 } } },
12686 }
948112687 },
9482 .sf = d.format.integer,
948312688 },
9484 } } };
9485 }
9486 /// C7.2.96 FCVTZU (scalar, integer)
9487 pub fn fcvtzu(d: Register, n: Register) Instruction {
9488 return .{ .data_processing_vector = .{ .convert_float_integer = .{
9489 .fcvtzu = .{
9490 .Rd = d.alias.encode(.{}),
9491 .Rn = n.alias.encode(.{ .V = true }),
9492 .ftype = switch (n.format.scalar) {
12689 .vector => |arrangement| {
12690 assert(arrangement != .@"1d" and n.format.vector == arrangement);
12691 switch (arrangement.elemSize()) {
949312692 else => unreachable,
9494 .single => .single,
9495 .double => .double,
9496 .half => .half,
9497 },
9498 .sf = d.format.integer,
12693 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12694 .fcvtzu = .{
12695 .Rd = d.alias.encode(.{ .V = true }),
12696 .Rn = n.alias.encode(.{ .V = true }),
12697 .Q = arrangement.size(),
12698 },
12699 } } },
12700 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12701 .fcvtzu = .{
12702 .Rd = d.alias.encode(.{ .V = true }),
12703 .Rn = n.alias.encode(.{ .V = true }),
12704 .sz = arrangement.elemSz(),
12705 .Q = arrangement.size(),
12706 },
12707 } } },
12708 }
949912709 },
9500 } } };
12710 }
950112711 }
950212712 /// C7.2.98 FDIV (scalar)
950312713 pub fn fdiv(d: Register, n: Register, m: Register) Instruction {
......@@ -9508,12 +12718,7 @@ pub const Instruction = packed union {
950812718 .Rd = d.alias.encode(.{ .V = true }),
950912719 .Rn = n.alias.encode(.{ .V = true }),
951012720 .Rm = m.alias.encode(.{ .V = true }),
9511 .ftype = switch (ftype) {
9512 else => unreachable,
9513 .single => .single,
9514 .double => .double,
9515 .half => .half,
9516 },
12721 .ftype = .fromVectorSize(ftype),
951712722 },
951812723 } } };
951912724 }
......@@ -9538,12 +12743,7 @@ pub const Instruction = packed union {
953812743 .Rn = n.alias.encode(.{ .V = true }),
953912744 .Rm = m.alias.encode(.{ .V = true }),
954012745 .Ra = a.alias.encode(.{ .V = true }),
9541 .ftype = switch (ftype) {
9542 else => unreachable,
9543 .single => .single,
9544 .double => .double,
9545 .half => .half,
9546 },
12746 .ftype = .fromVectorSize(ftype),
954712747 },
954812748 } } };
954912749 }
......@@ -9556,12 +12756,7 @@ pub const Instruction = packed union {
955612756 .Rd = d.alias.encode(.{ .V = true }),
955712757 .Rn = n.alias.encode(.{ .V = true }),
955812758 .Rm = m.alias.encode(.{ .V = true }),
9559 .ftype = switch (ftype) {
9560 else => unreachable,
9561 .single => .single,
9562 .double => .double,
9563 .half => .half,
9564 },
12759 .ftype = .fromVectorSize(ftype),
956512760 },
956612761 } } };
956712762 }
......@@ -9574,12 +12769,7 @@ pub const Instruction = packed union {
957412769 .Rd = d.alias.encode(.{ .V = true }),
957512770 .Rn = n.alias.encode(.{ .V = true }),
957612771 .Rm = m.alias.encode(.{ .V = true }),
9577 .ftype = switch (ftype) {
9578 else => unreachable,
9579 .single => .single,
9580 .double => .double,
9581 .half => .half,
9582 },
12772 .ftype = .fromVectorSize(ftype),
958312773 },
958412774 } } };
958512775 }
......@@ -9592,12 +12782,7 @@ pub const Instruction = packed union {
959212782 .Rd = d.alias.encode(.{ .V = true }),
959312783 .Rn = n.alias.encode(.{ .V = true }),
959412784 .Rm = m.alias.encode(.{ .V = true }),
9595 .ftype = switch (ftype) {
9596 else => unreachable,
9597 .single => .single,
9598 .double => .double,
9599 .half => .half,
9600 },
12785 .ftype = .fromVectorSize(ftype),
960112786 },
960212787 } } };
960312788 }
......@@ -9610,12 +12795,7 @@ pub const Instruction = packed union {
961012795 .Rd = d.alias.encode(.{ .V = true }),
961112796 .Rn = n.alias.encode(.{ .V = true }),
961212797 .Rm = m.alias.encode(.{ .V = true }),
9613 .ftype = switch (ftype) {
9614 else => unreachable,
9615 .single => .single,
9616 .double => .double,
9617 .half => .half,
9618 },
12798 .ftype = .fromVectorSize(ftype),
961912799 },
962012800 } } };
962112801 }
......@@ -9642,12 +12822,7 @@ pub const Instruction = packed union {
964212822 .fmov = .{
964312823 .Rd = d.alias.encode(.{ .V = true }),
964412824 .imm8 = imm,
9645 .ftype = switch (ftype) {
9646 else => unreachable,
9647 .single => .single,
9648 .double => .double,
9649 .half => .half,
9650 },
12825 .ftype = .fromVectorSize(ftype),
965112826 },
965212827 } } },
965312828 .vector => |arrangement| {
......@@ -9680,12 +12855,7 @@ pub const Instruction = packed union {
968012855 .Rn = n.alias.encode(.{ .V = true }),
968112856 .opcode = .float_to_integer,
968212857 .rmode = .@"0",
9683 .ftype = switch (ftype) {
9684 else => unreachable,
9685 .single => .single,
9686 .double => .double,
9687 .half => .half,
9688 },
12858 .ftype = .fromVectorSize(ftype),
968912859 .sf = sf,
969012860 },
969112861 } } };
......@@ -9723,12 +12893,7 @@ pub const Instruction = packed union {
972312893 .Rn = n.alias.encode(.{}),
972412894 .opcode = .integer_to_float,
972512895 .rmode = .@"0",
9726 .ftype = switch (ftype) {
9727 else => unreachable,
9728 .single => .single,
9729 .double => .double,
9730 .half => .half,
9731 },
12896 .ftype = .fromVectorSize(ftype),
973212897 .sf = sf,
973312898 },
973412899 } } };
......@@ -9739,12 +12904,7 @@ pub const Instruction = packed union {
973912904 .fmov = .{
974012905 .Rd = d.alias.encode(.{ .V = true }),
974112906 .Rn = n.alias.encode(.{ .V = true }),
9742 .ftype = switch (ftype) {
9743 else => unreachable,
9744 .single => .single,
9745 .double => .double,
9746 .half => .half,
9747 },
12907 .ftype = .fromVectorSize(ftype),
974812908 },
974912909 } } };
975012910 },
......@@ -9781,12 +12941,7 @@ pub const Instruction = packed union {
978112941 .Rn = n.alias.encode(.{ .V = true }),
978212942 .Rm = m.alias.encode(.{ .V = true }),
978312943 .Ra = a.alias.encode(.{ .V = true }),
9784 .ftype = switch (ftype) {
9785 else => unreachable,
9786 .single => .single,
9787 .double => .double,
9788 .half => .half,
9789 },
12944 .ftype = .fromVectorSize(ftype),
979012945 },
979112946 } } };
979212947 }
......@@ -9799,31 +12954,47 @@ pub const Instruction = packed union {
979912954 .Rd = d.alias.encode(.{ .V = true }),
980012955 .Rn = n.alias.encode(.{ .V = true }),
980112956 .Rm = m.alias.encode(.{ .V = true }),
9802 .ftype = switch (ftype) {
9803 else => unreachable,
9804 .single => .single,
9805 .double => .double,
9806 .half => .half,
9807 },
12957 .ftype = .fromVectorSize(ftype),
980812958 },
980912959 } } };
981012960 }
12961 /// C7.2.139 FNEG (vector)
981112962 /// C7.2.140 FNEG (scalar)
981212963 pub fn fneg(d: Register, n: Register) Instruction {
9813 const ftype = d.format.scalar;
9814 assert(n.format.scalar == ftype);
9815 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9816 .fneg = .{
9817 .Rd = d.alias.encode(.{ .V = true }),
9818 .Rn = n.alias.encode(.{ .V = true }),
9819 .ftype = switch (ftype) {
12964 switch (d.format) {
12965 else => unreachable,
12966 .vector => |arrangement| {
12967 assert(n.format.vector == arrangement);
12968 switch (arrangement.elemSize()) {
982012969 else => unreachable,
9821 .single => .single,
9822 .double => .double,
9823 .half => .half,
9824 },
12970 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
12971 .fneg = .{
12972 .Rd = d.alias.encode(.{ .V = true }),
12973 .Rn = n.alias.encode(.{ .V = true }),
12974 .Q = arrangement.size(),
12975 },
12976 } } },
12977 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
12978 .fneg = .{
12979 .Rd = d.alias.encode(.{ .V = true }),
12980 .Rn = n.alias.encode(.{ .V = true }),
12981 .sz = arrangement.elemSz(),
12982 .Q = arrangement.size(),
12983 },
12984 } } },
12985 }
982512986 },
9826 } } };
12987 .scalar => |ftype| {
12988 assert(n.format.scalar == ftype);
12989 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
12990 .fneg = .{
12991 .Rd = d.alias.encode(.{ .V = true }),
12992 .Rn = n.alias.encode(.{ .V = true }),
12993 .ftype = .fromVectorSize(ftype),
12994 },
12995 } } };
12996 },
12997 }
982712998 }
982812999 /// C7.2.141 FNMADD
982913000 pub fn fnmadd(d: Register, n: Register, m: Register, a: Register) Instruction {
......@@ -9835,12 +13006,7 @@ pub const Instruction = packed union {
983513006 .Rn = n.alias.encode(.{ .V = true }),
983613007 .Rm = m.alias.encode(.{ .V = true }),
983713008 .Ra = a.alias.encode(.{ .V = true }),
9838 .ftype = switch (ftype) {
9839 else => unreachable,
9840 .single => .single,
9841 .double => .double,
9842 .half => .half,
9843 },
13009 .ftype = .fromVectorSize(ftype),
984413010 },
984513011 } } };
984613012 }
......@@ -9854,12 +13020,7 @@ pub const Instruction = packed union {
985413020 .Rn = n.alias.encode(.{ .V = true }),
985513021 .Rm = m.alias.encode(.{ .V = true }),
985613022 .Ra = a.alias.encode(.{ .V = true }),
9857 .ftype = switch (ftype) {
9858 else => unreachable,
9859 .single => .single,
9860 .double => .double,
9861 .half => .half,
9862 },
13023 .ftype = .fromVectorSize(ftype),
986313024 },
986413025 } } };
986513026 }
......@@ -9872,150 +13033,313 @@ pub const Instruction = packed union {
987213033 .Rd = d.alias.encode(.{ .V = true }),
987313034 .Rn = n.alias.encode(.{ .V = true }),
987413035 .Rm = m.alias.encode(.{ .V = true }),
9875 .ftype = switch (ftype) {
9876 else => unreachable,
9877 .single => .single,
9878 .double => .double,
9879 .half => .half,
9880 },
13036 .ftype = .fromVectorSize(ftype),
988113037 },
988213038 } } };
988313039 }
13040 /// C7.2.155 FRINTA (vector)
988413041 /// C7.2.156 FRINTA (scalar)
988513042 pub fn frinta(d: Register, n: Register) Instruction {
9886 const ftype = d.format.scalar;
9887 assert(n.format.scalar == ftype);
9888 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9889 .frinta = .{
9890 .Rd = d.alias.encode(.{ .V = true }),
9891 .Rn = n.alias.encode(.{ .V = true }),
9892 .ftype = switch (ftype) {
13043 switch (d.format) {
13044 else => unreachable,
13045 .vector => |arrangement| {
13046 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13047 switch (arrangement.elemSize()) {
989313048 else => unreachable,
9894 .single => .single,
9895 .double => .double,
9896 .half => .half,
9897 },
13049 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13050 .frinta = .{
13051 .Rd = d.alias.encode(.{ .V = true }),
13052 .Rn = n.alias.encode(.{ .V = true }),
13053 .Q = arrangement.size(),
13054 },
13055 } } },
13056 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13057 .frinta = .{
13058 .Rd = d.alias.encode(.{ .V = true }),
13059 .Rn = n.alias.encode(.{ .V = true }),
13060 .sz = arrangement.elemSz(),
13061 .Q = arrangement.size(),
13062 },
13063 } } },
13064 }
989813065 },
9899 } } };
13066 .scalar => |ftype| {
13067 assert(n.format.scalar == ftype);
13068 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13069 .frinta = .{
13070 .Rd = d.alias.encode(.{ .V = true }),
13071 .Rn = n.alias.encode(.{ .V = true }),
13072 .ftype = .fromVectorSize(ftype),
13073 },
13074 } } };
13075 },
13076 }
990013077 }
13078 /// C7.2.157 FRINTI (vector)
990113079 /// C7.2.158 FRINTI (scalar)
990213080 pub fn frinti(d: Register, n: Register) Instruction {
9903 const ftype = d.format.scalar;
9904 assert(n.format.scalar == ftype);
9905 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9906 .frinti = .{
9907 .Rd = d.alias.encode(.{ .V = true }),
9908 .Rn = n.alias.encode(.{ .V = true }),
9909 .ftype = switch (ftype) {
13081 switch (d.format) {
13082 else => unreachable,
13083 .vector => |arrangement| {
13084 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13085 switch (arrangement.elemSize()) {
991013086 else => unreachable,
9911 .single => .single,
9912 .double => .double,
9913 .half => .half,
9914 },
13087 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13088 .frinti = .{
13089 .Rd = d.alias.encode(.{ .V = true }),
13090 .Rn = n.alias.encode(.{ .V = true }),
13091 .Q = arrangement.size(),
13092 },
13093 } } },
13094 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13095 .frinti = .{
13096 .Rd = d.alias.encode(.{ .V = true }),
13097 .Rn = n.alias.encode(.{ .V = true }),
13098 .sz = arrangement.elemSz(),
13099 .Q = arrangement.size(),
13100 },
13101 } } },
13102 }
991513103 },
9916 } } };
13104 .scalar => |ftype| {
13105 assert(n.format.scalar == ftype);
13106 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13107 .frinti = .{
13108 .Rd = d.alias.encode(.{ .V = true }),
13109 .Rn = n.alias.encode(.{ .V = true }),
13110 .ftype = .fromVectorSize(ftype),
13111 },
13112 } } };
13113 },
13114 }
991713115 }
13116 /// C7.2.159 FRINTM (vector)
991813117 /// C7.2.160 FRINTM (scalar)
991913118 pub fn frintm(d: Register, n: Register) Instruction {
9920 const ftype = d.format.scalar;
9921 assert(n.format.scalar == ftype);
9922 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9923 .frintm = .{
9924 .Rd = d.alias.encode(.{ .V = true }),
9925 .Rn = n.alias.encode(.{ .V = true }),
9926 .ftype = switch (ftype) {
13119 switch (d.format) {
13120 else => unreachable,
13121 .vector => |arrangement| {
13122 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13123 switch (arrangement.elemSize()) {
992713124 else => unreachable,
9928 .single => .single,
9929 .double => .double,
9930 .half => .half,
9931 },
13125 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13126 .frintm = .{
13127 .Rd = d.alias.encode(.{ .V = true }),
13128 .Rn = n.alias.encode(.{ .V = true }),
13129 .Q = arrangement.size(),
13130 },
13131 } } },
13132 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13133 .frintm = .{
13134 .Rd = d.alias.encode(.{ .V = true }),
13135 .Rn = n.alias.encode(.{ .V = true }),
13136 .sz = arrangement.elemSz(),
13137 .Q = arrangement.size(),
13138 },
13139 } } },
13140 }
993213141 },
9933 } } };
13142 .scalar => |ftype| {
13143 assert(n.format.scalar == ftype);
13144 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13145 .frintm = .{
13146 .Rd = d.alias.encode(.{ .V = true }),
13147 .Rn = n.alias.encode(.{ .V = true }),
13148 .ftype = .fromVectorSize(ftype),
13149 },
13150 } } };
13151 },
13152 }
993413153 }
13154 /// C7.2.161 FRINTN (vector)
993513155 /// C7.2.162 FRINTN (scalar)
993613156 pub fn frintn(d: Register, n: Register) Instruction {
9937 const ftype = d.format.scalar;
9938 assert(n.format.scalar == ftype);
9939 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9940 .frintn = .{
9941 .Rd = d.alias.encode(.{ .V = true }),
9942 .Rn = n.alias.encode(.{ .V = true }),
9943 .ftype = switch (ftype) {
13157 switch (d.format) {
13158 else => unreachable,
13159 .vector => |arrangement| {
13160 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13161 switch (arrangement.elemSize()) {
994413162 else => unreachable,
9945 .single => .single,
9946 .double => .double,
9947 .half => .half,
9948 },
13163 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13164 .frintn = .{
13165 .Rd = d.alias.encode(.{ .V = true }),
13166 .Rn = n.alias.encode(.{ .V = true }),
13167 .Q = arrangement.size(),
13168 },
13169 } } },
13170 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13171 .frintn = .{
13172 .Rd = d.alias.encode(.{ .V = true }),
13173 .Rn = n.alias.encode(.{ .V = true }),
13174 .sz = arrangement.elemSz(),
13175 .Q = arrangement.size(),
13176 },
13177 } } },
13178 }
994913179 },
9950 } } };
13180 .scalar => |ftype| {
13181 assert(n.format.scalar == ftype);
13182 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13183 .frintn = .{
13184 .Rd = d.alias.encode(.{ .V = true }),
13185 .Rn = n.alias.encode(.{ .V = true }),
13186 .ftype = .fromVectorSize(ftype),
13187 },
13188 } } };
13189 },
13190 }
995113191 }
13192 /// C7.2.163 FRINTP (vector)
995213193 /// C7.2.164 FRINTP (scalar)
995313194 pub fn frintp(d: Register, n: Register) Instruction {
9954 const ftype = d.format.scalar;
9955 assert(n.format.scalar == ftype);
9956 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9957 .frintp = .{
9958 .Rd = d.alias.encode(.{ .V = true }),
9959 .Rn = n.alias.encode(.{ .V = true }),
9960 .ftype = switch (ftype) {
13195 switch (d.format) {
13196 else => unreachable,
13197 .vector => |arrangement| {
13198 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13199 switch (arrangement.elemSize()) {
996113200 else => unreachable,
9962 .single => .single,
9963 .double => .double,
9964 .half => .half,
9965 },
13201 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13202 .frintp = .{
13203 .Rd = d.alias.encode(.{ .V = true }),
13204 .Rn = n.alias.encode(.{ .V = true }),
13205 .Q = arrangement.size(),
13206 },
13207 } } },
13208 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13209 .frintp = .{
13210 .Rd = d.alias.encode(.{ .V = true }),
13211 .Rn = n.alias.encode(.{ .V = true }),
13212 .sz = arrangement.elemSz(),
13213 .Q = arrangement.size(),
13214 },
13215 } } },
13216 }
996613217 },
9967 } } };
13218 .scalar => |ftype| {
13219 assert(n.format.scalar == ftype);
13220 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13221 .frintp = .{
13222 .Rd = d.alias.encode(.{ .V = true }),
13223 .Rn = n.alias.encode(.{ .V = true }),
13224 .ftype = .fromVectorSize(ftype),
13225 },
13226 } } };
13227 },
13228 }
996813229 }
13230 /// C7.2.165 FRINTX (vector)
996913231 /// C7.2.166 FRINTX (scalar)
997013232 pub fn frintx(d: Register, n: Register) Instruction {
9971 const ftype = d.format.scalar;
9972 assert(n.format.scalar == ftype);
9973 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9974 .frintx = .{
9975 .Rd = d.alias.encode(.{ .V = true }),
9976 .Rn = n.alias.encode(.{ .V = true }),
9977 .ftype = switch (ftype) {
13233 switch (d.format) {
13234 else => unreachable,
13235 .vector => |arrangement| {
13236 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13237 switch (arrangement.elemSize()) {
997813238 else => unreachable,
9979 .single => .single,
9980 .double => .double,
9981 .half => .half,
9982 },
13239 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13240 .frintx = .{
13241 .Rd = d.alias.encode(.{ .V = true }),
13242 .Rn = n.alias.encode(.{ .V = true }),
13243 .Q = arrangement.size(),
13244 },
13245 } } },
13246 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13247 .frintx = .{
13248 .Rd = d.alias.encode(.{ .V = true }),
13249 .Rn = n.alias.encode(.{ .V = true }),
13250 .sz = arrangement.elemSz(),
13251 .Q = arrangement.size(),
13252 },
13253 } } },
13254 }
998313255 },
9984 } } };
13256 .scalar => |ftype| {
13257 assert(n.format.scalar == ftype);
13258 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13259 .frintx = .{
13260 .Rd = d.alias.encode(.{ .V = true }),
13261 .Rn = n.alias.encode(.{ .V = true }),
13262 .ftype = .fromVectorSize(ftype),
13263 },
13264 } } };
13265 },
13266 }
998513267 }
13268 /// C7.2.167 FRINTZ (vector)
998613269 /// C7.2.168 FRINTZ (scalar)
998713270 pub fn frintz(d: Register, n: Register) Instruction {
9988 const ftype = d.format.scalar;
9989 assert(n.format.scalar == ftype);
9990 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
9991 .frintz = .{
9992 .Rd = d.alias.encode(.{ .V = true }),
9993 .Rn = n.alias.encode(.{ .V = true }),
9994 .ftype = switch (ftype) {
13271 switch (d.format) {
13272 else => unreachable,
13273 .vector => |arrangement| {
13274 assert(arrangement != .@"1d" and n.format.vector == arrangement);
13275 switch (arrangement.elemSize()) {
999513276 else => unreachable,
9996 .single => .single,
9997 .double => .double,
9998 .half => .half,
9999 },
13277 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13278 .frintz = .{
13279 .Rd = d.alias.encode(.{ .V = true }),
13280 .Rn = n.alias.encode(.{ .V = true }),
13281 .Q = arrangement.size(),
13282 },
13283 } } },
13284 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13285 .frintz = .{
13286 .Rd = d.alias.encode(.{ .V = true }),
13287 .Rn = n.alias.encode(.{ .V = true }),
13288 .sz = arrangement.elemSz(),
13289 .Q = arrangement.size(),
13290 },
13291 } } },
13292 }
1000013293 },
10001 } } };
13294 .scalar => |ftype| {
13295 assert(n.format.scalar == ftype);
13296 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13297 .frintz = .{
13298 .Rd = d.alias.encode(.{ .V = true }),
13299 .Rn = n.alias.encode(.{ .V = true }),
13300 .ftype = .fromVectorSize(ftype),
13301 },
13302 } } };
13303 },
13304 }
1000213305 }
13306 /// C7.2.171 FSQRT (vector)
1000313307 /// C7.2.172 FSQRT (scalar)
1000413308 pub fn fsqrt(d: Register, n: Register) Instruction {
10005 const ftype = d.format.scalar;
10006 assert(n.format.scalar == ftype);
10007 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
10008 .fsqrt = .{
10009 .Rd = d.alias.encode(.{ .V = true }),
10010 .Rn = n.alias.encode(.{ .V = true }),
10011 .ftype = switch (ftype) {
13309 switch (d.format) {
13310 else => unreachable,
13311 .vector => |arrangement| {
13312 assert(n.format.vector == arrangement);
13313 switch (arrangement.elemSize()) {
1001213314 else => unreachable,
10013 .single => .single,
10014 .double => .double,
10015 .half => .half,
10016 },
13315 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
13316 .fsqrt = .{
13317 .Rd = d.alias.encode(.{ .V = true }),
13318 .Rn = n.alias.encode(.{ .V = true }),
13319 .Q = arrangement.size(),
13320 },
13321 } } },
13322 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
13323 .fsqrt = .{
13324 .Rd = d.alias.encode(.{ .V = true }),
13325 .Rn = n.alias.encode(.{ .V = true }),
13326 .sz = arrangement.elemSz(),
13327 .Q = arrangement.size(),
13328 },
13329 } } },
13330 }
1001713331 },
10018 } } };
13332 .scalar => |ftype| {
13333 assert(n.format.scalar == ftype);
13334 return .{ .data_processing_vector = .{ .float_data_processing_one_source = .{
13335 .fsqrt = .{
13336 .Rd = d.alias.encode(.{ .V = true }),
13337 .Rn = n.alias.encode(.{ .V = true }),
13338 .ftype = .fromVectorSize(ftype),
13339 },
13340 } } };
13341 },
13342 }
1001913343 }
1002013344 /// C7.2.174 FSUB (scalar)
1002113345 pub fn fsub(d: Register, n: Register, m: Register) Instruction {
......@@ -10026,12 +13350,7 @@ pub const Instruction = packed union {
1002613350 .Rd = d.alias.encode(.{ .V = true }),
1002713351 .Rn = n.alias.encode(.{ .V = true }),
1002813352 .Rm = m.alias.encode(.{ .V = true }),
10029 .ftype = switch (ftype) {
10030 else => unreachable,
10031 .single => .single,
10032 .double => .double,
10033 .half => .half,
10034 },
13353 .ftype = .fromVectorSize(ftype),
1003513354 },
1003613355 } } };
1003713356 }
......@@ -11021,12 +14340,52 @@ pub const Instruction = packed union {
1102114340 },
1102214341 } } };
1102314342 }
14343 /// C7.2.209 NEG (vector)
14344 pub fn neg(d: Register, n: Register) Instruction {
14345 switch (d.format) {
14346 else => unreachable,
14347 .scalar => |elem_size| {
14348 assert(elem_size == .double and elem_size == n.format.scalar);
14349 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
14350 .neg = .{
14351 .Rd = d.alias.encode(.{ .V = true }),
14352 .Rn = n.alias.encode(.{ .V = true }),
14353 .size = .fromVectorSize(elem_size),
14354 },
14355 } } };
14356 },
14357 .vector => |arrangement| {
14358 assert(arrangement != .@"1d" and n.format.vector == arrangement);
14359 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14360 .neg = .{
14361 .Rd = d.alias.encode(.{ .V = true }),
14362 .Rn = n.alias.encode(.{ .V = true }),
14363 .size = arrangement.elemSize(),
14364 .Q = arrangement.size(),
14365 },
14366 } } };
14367 },
14368 }
14369 }
1102414370 /// C6.2.238 NOP
1102514371 pub fn nop() Instruction {
1102614372 return .{ .branch_exception_generating_system = .{ .hints = .{
1102714373 .nop = .{},
1102814374 } } };
1102914375 }
14376 /// C7.2.210 NOT
14377 pub fn not(d: Register, n: Register) Instruction {
14378 const arrangement = d.format.vector;
14379 assert(arrangement.elemSize() == .byte and n.format.vector == arrangement);
14380 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14381 .not = .{
14382 .Rd = d.alias.encode(.{ .V = true }),
14383 .Rn = n.alias.encode(.{ .V = true }),
14384 .size = arrangement.elemSize(),
14385 .Q = arrangement.size(),
14386 },
14387 } } };
14388 }
1103014389 /// C6.2.239 ORN (shifted register)
1103114390 /// C7.2.211 ORN (vector)
1103214391 pub fn orn(d: Register, n: Register, form: union(enum) {
......@@ -11343,21 +14702,63 @@ pub const Instruction = packed union {
1134314702 },
1134414703 } } };
1134514704 }
14705 /// C7.2.234 SCVTF (vector, integer)
1134614706 /// C7.2.236 SCVTF (scalar, integer)
1134714707 pub fn scvtf(d: Register, n: Register) Instruction {
11348 return .{ .data_processing_vector = .{ .convert_float_integer = .{
11349 .scvtf = .{
11350 .Rd = d.alias.encode(.{ .V = true }),
11351 .Rn = n.alias.encode(.{}),
11352 .ftype = switch (d.format.scalar) {
11353 else => unreachable,
11354 .single => .single,
11355 .double => .double,
11356 .half => .half,
14708 switch (d.format) {
14709 else => unreachable,
14710 .scalar => |ftype| switch (n.format) {
14711 else => unreachable,
14712 .scalar => |elem_size| {
14713 assert(ftype == elem_size);
14714 switch (ftype) {
14715 else => unreachable,
14716 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
14717 .scvtf = .{
14718 .Rd = d.alias.encode(.{ .V = true }),
14719 .Rn = n.alias.encode(.{ .V = true }),
14720 },
14721 } } },
14722 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
14723 .scvtf = .{
14724 .Rd = d.alias.encode(.{ .V = true }),
14725 .Rn = n.alias.encode(.{ .V = true }),
14726 .sz = .fromVectorSize(ftype),
14727 },
14728 } } },
14729 }
1135714730 },
11358 .sf = n.format.integer,
14731 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
14732 .scvtf = .{
14733 .Rd = d.alias.encode(.{ .V = true }),
14734 .Rn = n.alias.encode(.{}),
14735 .ftype = .fromVectorSize(ftype),
14736 .sf = sf,
14737 },
14738 } } },
1135914739 },
11360 } } };
14740 .vector => |arrangement| {
14741 assert(arrangement != .@"1d" and n.format.vector == arrangement);
14742 switch (arrangement.elemSize()) {
14743 else => unreachable,
14744 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
14745 .scvtf = .{
14746 .Rd = d.alias.encode(.{ .V = true }),
14747 .Rn = n.alias.encode(.{ .V = true }),
14748 .Q = arrangement.size(),
14749 },
14750 } } },
14751 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14752 .scvtf = .{
14753 .Rd = d.alias.encode(.{ .V = true }),
14754 .Rn = n.alias.encode(.{ .V = true }),
14755 .sz = arrangement.elemSz(),
14756 .Q = arrangement.size(),
14757 },
14758 } } },
14759 }
14760 },
14761 }
1136114762 }
1136214763 /// C6.2.270 SDIV
1136314764 pub fn sdiv(d: Register, n: Register, m: Register) Instruction {
......@@ -11448,6 +14849,60 @@ pub const Instruction = packed union {
1144814849 },
1144914850 } } };
1145014851 }
14852 /// C7.2.282 SQABS
14853 pub fn sqabs(d: Register, n: Register) Instruction {
14854 switch (d.format) {
14855 else => unreachable,
14856 .scalar => |elem_size| {
14857 assert(elem_size == n.format.scalar);
14858 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
14859 .sqabs = .{
14860 .Rd = d.alias.encode(.{ .V = true }),
14861 .Rn = n.alias.encode(.{ .V = true }),
14862 .size = .fromVectorSize(elem_size),
14863 },
14864 } } };
14865 },
14866 .vector => |arrangement| {
14867 assert(arrangement != .@"1d" and n.format.vector == arrangement);
14868 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14869 .sqabs = .{
14870 .Rd = d.alias.encode(.{ .V = true }),
14871 .Rn = n.alias.encode(.{ .V = true }),
14872 .size = arrangement.elemSize(),
14873 .Q = arrangement.size(),
14874 },
14875 } } };
14876 },
14877 }
14878 }
14879 /// C7.2.308 SQXTN
14880 pub fn sqxtn(d: Register, n: Register) Instruction {
14881 switch (d.format) {
14882 else => unreachable,
14883 .scalar => |elem_size| {
14884 assert(elem_size == n.format.scalar);
14885 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
14886 .sqxtn = .{
14887 .Rd = d.alias.encode(.{ .V = true }),
14888 .Rn = n.alias.encode(.{ .V = true }),
14889 .size = .fromVectorSize(elem_size),
14890 },
14891 } } };
14892 },
14893 .vector => |arrangement| {
14894 assert(arrangement != .@"1d" and n.format.vector == arrangement);
14895 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14896 .sqxtn = .{
14897 .Rd = d.alias.encode(.{ .V = true }),
14898 .Rn = n.alias.encode(.{ .V = true }),
14899 .size = arrangement.elemSize(),
14900 .Q = arrangement.size(),
14901 },
14902 } } };
14903 },
14904 }
14905 }
1145114906 /// C6.2.321 STP
1145214907 /// C7.2.330 STP (SIMD&FP)
1145314908 pub fn stp(t1: Register, t2: Register, form: union(enum) {
......@@ -11942,6 +15397,33 @@ pub const Instruction = packed union {
1194215397 } },
1194315398 }
1194415399 }
15400 /// C7.2.337 SUQADD
15401 pub fn suqadd(d: Register, n: Register) Instruction {
15402 switch (d.format) {
15403 else => unreachable,
15404 .scalar => |elem_size| {
15405 assert(elem_size == n.format.scalar);
15406 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
15407 .suqadd = .{
15408 .Rd = d.alias.encode(.{ .V = true }),
15409 .Rn = n.alias.encode(.{ .V = true }),
15410 .size = .fromVectorSize(elem_size),
15411 },
15412 } } };
15413 },
15414 .vector => |arrangement| {
15415 assert(arrangement != .@"1d" and n.format.vector == arrangement);
15416 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
15417 .suqadd = .{
15418 .Rd = d.alias.encode(.{ .V = true }),
15419 .Rn = n.alias.encode(.{ .V = true }),
15420 .size = arrangement.elemSize(),
15421 .Q = arrangement.size(),
15422 },
15423 } } };
15424 },
15425 }
15426 }
1194515427 /// C6.2.365 SVC
1194615428 pub fn svc(imm: u16) Instruction {
1194715429 return .{ .branch_exception_generating_system = .{ .exception_generating = .{
......@@ -12021,21 +15503,63 @@ pub const Instruction = packed union {
1202115503 },
1202215504 } } };
1202315505 }
15506 /// C7.2.353 UCVTF (vector, integer)
1202415507 /// C7.2.355 UCVTF (scalar, integer)
1202515508 pub fn ucvtf(d: Register, n: Register) Instruction {
12026 return .{ .data_processing_vector = .{ .convert_float_integer = .{
12027 .ucvtf = .{
12028 .Rd = d.alias.encode(.{ .V = true }),
12029 .Rn = n.alias.encode(.{}),
12030 .ftype = switch (d.format.scalar) {
12031 else => unreachable,
12032 .single => .single,
12033 .double => .double,
12034 .half => .half,
15509 switch (d.format) {
15510 else => unreachable,
15511 .scalar => |ftype| switch (n.format) {
15512 else => unreachable,
15513 .scalar => |elem_size| {
15514 assert(ftype == elem_size);
15515 switch (ftype) {
15516 else => unreachable,
15517 .half => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous_fp16 = .{
15518 .ucvtf = .{
15519 .Rd = d.alias.encode(.{ .V = true }),
15520 .Rn = n.alias.encode(.{ .V = true }),
15521 },
15522 } } },
15523 .single, .double => return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
15524 .ucvtf = .{
15525 .Rd = d.alias.encode(.{ .V = true }),
15526 .Rn = n.alias.encode(.{ .V = true }),
15527 .sz = .fromVectorSize(ftype),
15528 },
15529 } } },
15530 }
1203515531 },
12036 .sf = n.format.integer,
15532 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
15533 .ucvtf = .{
15534 .Rd = d.alias.encode(.{ .V = true }),
15535 .Rn = n.alias.encode(.{}),
15536 .ftype = .fromVectorSize(ftype),
15537 .sf = sf,
15538 },
15539 } } },
1203715540 },
12038 } } };
15541 .vector => |arrangement| {
15542 assert(arrangement != .@"1d" and n.format.vector == arrangement);
15543 switch (arrangement.elemSize()) {
15544 else => unreachable,
15545 .half => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous_fp16 = .{
15546 .ucvtf = .{
15547 .Rd = d.alias.encode(.{ .V = true }),
15548 .Rn = n.alias.encode(.{ .V = true }),
15549 .Q = arrangement.size(),
15550 },
15551 } } },
15552 .single, .double => return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
15553 .ucvtf = .{
15554 .Rd = d.alias.encode(.{ .V = true }),
15555 .Rn = n.alias.encode(.{ .V = true }),
15556 .sz = arrangement.elemSz(),
15557 .Q = arrangement.size(),
15558 },
15559 } } },
15560 }
15561 },
15562 }
1203915563 }
1204015564 /// C6.2.387 UDF
1204115565 pub fn udf(imm: u16) Instruction {
......@@ -12149,7 +15673,7 @@ pub const Instruction = packed union {
1214915673 }
1215015674
1215115675 comptime {
12152 @setEvalBranchQuota(68_000);
15676 @setEvalBranchQuota(110_000);
1215315677 verify(@typeName(Instruction), Instruction);
1215415678 }
1215515679 fn verify(name: []const u8, Type: type) void {
test/behavior/math.zig-3
......@@ -168,7 +168,6 @@ fn testOneCtz(comptime T: type, x: T) u32 {
168168}
169169
170170test "@ctz 128-bit integers" {
171 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
172171 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
173172 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
174173 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
......@@ -463,7 +462,6 @@ test "binary not big int <= 128 bits" {
463462}
464463
465464test "division" {
466 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
467465 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
468466 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
469467 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
......@@ -1819,7 +1817,6 @@ test "runtime int comparison to inf is comptime-known" {
18191817}
18201818
18211819test "float divide by zero" {
1822 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
18231820 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
18241821 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
18251822 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO