authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 01:44:26-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log40457a3696da015fe1396d6c84191b83731910db
treeb1e9791cbeca7d2aec7c3c995db07b95b9c06dff
parentf39ff6cc68ab7a0d8ef349d4d930118890c19b01

x86_64: implement integer vector bitwise operations

2 files changed, 25 insertions(+), 1 deletions(-)

src/arch/x86_64/CodeGen.zig+25
......@@ -6531,6 +6531,9 @@ fn genBinOp(
65316531 .sub,
65326532 .subwrap,
65336533 => if (self.hasFeature(.avx)) .{ .vp_b, .sub } else .{ .p_b, .sub },
6534 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6535 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6536 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
65346537 else => null,
65356538 },
65366539 17...32 => switch (air_tag) {
......@@ -6540,6 +6543,9 @@ fn genBinOp(
65406543 .sub,
65416544 .subwrap,
65426545 => if (self.hasFeature(.avx2)) .{ .vp_b, .sub } else null,
6546 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6547 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6548 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
65436549 else => null,
65446550 },
65456551 else => null,
......@@ -6555,6 +6561,9 @@ fn genBinOp(
65556561 .mul,
65566562 .mulwrap,
65576563 => if (self.hasFeature(.avx)) .{ .vp_w, .mull } else .{ .p_d, .mull },
6564 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6565 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6566 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
65586567 else => null,
65596568 },
65606569 9...16 => switch (air_tag) {
......@@ -6567,6 +6576,9 @@ fn genBinOp(
65676576 .mul,
65686577 .mulwrap,
65696578 => if (self.hasFeature(.avx2)) .{ .vp_w, .mull } else null,
6579 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6580 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6581 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
65706582 else => null,
65716583 },
65726584 else => null,
......@@ -6587,6 +6599,9 @@ fn genBinOp(
65876599 .{ .p_d, .mull }
65886600 else
65896601 null,
6602 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6603 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6604 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
65906605 else => null,
65916606 },
65926607 5...8 => switch (air_tag) {
......@@ -6599,6 +6614,9 @@ fn genBinOp(
65996614 .mul,
66006615 .mulwrap,
66016616 => if (self.hasFeature(.avx2)) .{ .vp_d, .mull } else null,
6617 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6618 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6619 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
66026620 else => null,
66036621 },
66046622 else => null,
......@@ -6611,6 +6629,9 @@ fn genBinOp(
66116629 .sub,
66126630 .subwrap,
66136631 => if (self.hasFeature(.avx)) .{ .vp_q, .sub } else .{ .p_q, .sub },
6632 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6633 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6634 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
66146635 else => null,
66156636 },
66166637 3...4 => switch (air_tag) {
......@@ -6620,6 +6641,9 @@ fn genBinOp(
66206641 .sub,
66216642 .subwrap,
66226643 => if (self.hasFeature(.avx2)) .{ .vp_q, .sub } else null,
6644 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6645 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6646 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
66236647 else => null,
66246648 },
66256649 else => null,
......@@ -6929,6 +6953,7 @@ fn genBinOp(
69296953 else => unreachable,
69306954 },
69316955 ),
6956 .bit_and, .bit_or, .xor => {},
69326957 .max, .min => {}, // TODO: unordered select
69336958 else => unreachable,
69346959 }
test/behavior/vector.zig-1
......@@ -120,7 +120,6 @@ test "vector float operators" {
120120
121121test "vector bit operators" {
122122 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
123 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
124123 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
125124 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
126125 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO