authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2026-04-02 01:49:00-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2026-04-02 14:29:40+02:00
log4059242f44e28dc2c8f9837c2033060974fd253f
tree690a3b58c275d0cfbda0af1ee54290dddac2f49b
parentdd10d3fb5219bb5683b90b4141b0f27eb02dd614

x86_64: use correct alias for register constraints stored in registers

Closes #31722

1 files changed, 13 insertions(+), 3 deletions(-)

src/codegen/x86_64/CodeGen.zig+13-3
...@@ -177226,9 +177226,19 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -177226,9 +177226,19 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {
177226 'x' => abi.RegisterClass.sse,177226 'x' => abi.RegisterClass.sse,
177227 else => unreachable,177227 else => unreachable,
177228 };177228 };
177229 if (input_mcv.isRegister() and177229 if (input_mcv.isRegister()) {
177230 rc.isSet(RegisterManager.indexOfRegIntoTracked(input_mcv.getReg().?).?))177230 const reg = input_mcv.getReg().?;
177231 break :arg input_mcv;177231 if (rc.isSet(RegisterManager.indexOfRegIntoTracked(reg).?)) {
177232 const alias = registerAlias(reg, @intCast(ty.abiSize(zcu)));
177233 break :arg switch (input_mcv) {
177234 else => unreachable,
177235 .register => .{ .register = alias },
177236 .register_offset => |reg_off| .{
177237 .register_offset = .{ .reg = alias, .off = reg_off.off },
177238 },
177239 };
177240 }
177241 }
177232 const reg = try self.register_manager.allocReg(null, rc);177242 const reg = try self.register_manager.allocReg(null, rc);
177233 try self.genSetReg(reg, ty, input_mcv, .{});177243 try self.genSetReg(reg, ty, input_mcv, .{});
177234 break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(zcu))) };177244 break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(zcu))) };