authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 06:11:47+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 06:13:00+02:00
log4251faf035cfda93beac8aab55f74eaccb513524
tree4d711069539e68ad5cedb717ab3064f5145246fa
parentb0ce4f0996e24ad62501be325da7e402bcb3498e
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

test-c-abi: skip some vector cases on arm regardless of float ABI

These cases only worked by accident when neon was enabled. The change to the arm baseline model from neon to vfp3d16 exposed these failures.

1 files changed, 6 insertions(+), 6 deletions(-)

test/c_abi/main.zig+6-6
...@@ -5032,7 +5032,7 @@ extern fn c_vector_6_u8(@Vector(6, u8), usize) void;...@@ -5032,7 +5032,7 @@ extern fn c_vector_6_u8(@Vector(6, u8), usize) void;
5032extern fn c_test_vector_6_u8() void;5032extern fn c_test_vector_6_u8() void;
50335033
5034test "@Vector(6, u8)" {5034test "@Vector(6, u8)" {
5035 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;5035 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5036 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5036 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5037 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;5037 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5038 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5038 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
...@@ -5110,7 +5110,7 @@ extern fn c_vector_12_u8(@Vector(12, u8), usize) void;...@@ -5110,7 +5110,7 @@ extern fn c_vector_12_u8(@Vector(12, u8), usize) void;
5110extern fn c_test_vector_12_u8() void;5110extern fn c_test_vector_12_u8() void;
51115111
5112test "@Vector(12, u8)" {5112test "@Vector(12, u8)" {
5113 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;5113 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5114 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5114 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5115 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;5115 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
51165116
...@@ -9176,7 +9176,7 @@ extern fn c_vector_3_u16(@Vector(3, u16), usize) void;...@@ -9176,7 +9176,7 @@ extern fn c_vector_3_u16(@Vector(3, u16), usize) void;
9176extern fn c_test_vector_3_u16() void;9176extern fn c_test_vector_3_u16() void;
91779177
9178test "@Vector(3, u16)" {9178test "@Vector(3, u16)" {
9179 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;9179 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9180 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9180 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9181 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9181 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9182 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9182 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
...@@ -9250,7 +9250,7 @@ extern fn c_vector_6_u16(@Vector(6, u16), usize) void;...@@ -9250,7 +9250,7 @@ extern fn c_vector_6_u16(@Vector(6, u16), usize) void;
9250extern fn c_test_vector_6_u16() void;9250extern fn c_test_vector_6_u16() void;
92519251
9252test "@Vector(6, u16)" {9252test "@Vector(6, u16)" {
9253 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;9253 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9254 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9254 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9255 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9255 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
92569256
...@@ -11439,7 +11439,7 @@ extern fn c_vector_3_u32(@Vector(3, u32), usize) void;...@@ -11439,7 +11439,7 @@ extern fn c_vector_3_u32(@Vector(3, u32), usize) void;
11439extern fn c_test_vector_3_u32() void;11439extern fn c_test_vector_3_u32() void;
1144011440
11441test "@Vector(3, u32)" {11441test "@Vector(3, u32)" {
11442 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;11442 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
11443 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11443 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11444 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;11444 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
1144511445
...@@ -13424,7 +13424,7 @@ extern fn c_vector_3_f32(@Vector(3, f32), usize) void;...@@ -13424,7 +13424,7 @@ extern fn c_vector_3_f32(@Vector(3, f32), usize) void;
13424extern fn c_test_vector_3_f32() void;13424extern fn c_test_vector_3_f32() void;
1342513425
13426test "@Vector(3, f32)" {13426test "@Vector(3, f32)" {
13427 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;13427 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
13428 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13428 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13429 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;13429 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
1343013430