| ... | @@ -5210,25 +5210,59 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { | ... | @@ -5210,25 +5210,59 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 5210 | return error.CodegenFail; | 5210 | return error.CodegenFail; |
| 5211 | } | 5211 | } |
| 5212 | | 5212 | |
| 5213 | usingnamespace switch (arch) { | 5213 | const Register = switch (arch) { |
| 5214 | .i386 => @import("codegen/x86.zig"), | 5214 | .i386 => @import("codegen/x86.zig").Register, |
| 5215 | .x86_64 => @import("codegen/x86_64.zig"), | 5215 | .x86_64 => @import("codegen/x86_64.zig").Register, |
| 5216 | .riscv64 => @import("codegen/riscv64.zig"), | 5216 | .riscv64 => @import("codegen/riscv64.zig").Register, |
| 5217 | .arm, .armeb => @import("codegen/arm.zig"), | 5217 | .arm, .armeb => @import("codegen/arm.zig").Register, |
| 5218 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig"), | 5218 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").Register, |
| 5219 | else => struct { | 5219 | else => enum { |
| 5220 | pub const Register = enum { | 5220 | dummy, |
| 5221 | dummy, | 5221 | |
| 5222 | | 5222 | pub fn allocIndex(self: Register) ?u4 { |
| 5223 | pub fn allocIndex(self: Register) ?u4 { | 5223 | _ = self; |
| 5224 | _ = self; | 5224 | return null; |
| 5225 | return null; | 5225 | } |
| 5226 | } | | |
| 5227 | }; | | |
| 5228 | pub const callee_preserved_regs = [_]Register{}; | | |
| 5229 | }, | 5226 | }, |
| 5230 | }; | 5227 | }; |
| 5231 | | 5228 | |
| | 5229 | const Instruction = switch (arch) { |
| | 5230 | .riscv64 => @import("codegen/riscv64.zig").Instruction, |
| | 5231 | .arm, .armeb => @import("codegen/arm.zig").Instruction, |
| | 5232 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").Instruction, |
| | 5233 | else => void, |
| | 5234 | }; |
| | 5235 | |
| | 5236 | const Condition = switch (arch) { |
| | 5237 | .arm, .armeb => @import("codegen/arm.zig").Condition, |
| | 5238 | else => void, |
| | 5239 | }; |
| | 5240 | |
| | 5241 | const callee_preserved_regs = switch (arch) { |
| | 5242 | .i386 => @import("codegen/x86.zig").callee_preserved_regs, |
| | 5243 | .x86_64 => @import("codegen/x86_64.zig").callee_preserved_regs, |
| | 5244 | .riscv64 => @import("codegen/riscv64.zig").callee_preserved_regs, |
| | 5245 | .arm, .armeb => @import("codegen/arm.zig").callee_preserved_regs, |
| | 5246 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").callee_preserved_regs, |
| | 5247 | else => [_]Register{}, |
| | 5248 | }; |
| | 5249 | |
| | 5250 | const c_abi_int_param_regs = switch (arch) { |
| | 5251 | .i386 => @import("codegen/x86.zig").c_abi_int_param_regs, |
| | 5252 | .x86_64 => @import("codegen/x86_64.zig").c_abi_int_param_regs, |
| | 5253 | .arm, .armeb => @import("codegen/arm.zig").c_abi_int_param_regs, |
| | 5254 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").c_abi_int_param_regs, |
| | 5255 | else => [_]Register{}, |
| | 5256 | }; |
| | 5257 | |
| | 5258 | const c_abi_int_return_regs = switch (arch) { |
| | 5259 | .i386 => @import("codegen/x86.zig").c_abi_int_return_regs, |
| | 5260 | .x86_64 => @import("codegen/x86_64.zig").c_abi_int_return_regs, |
| | 5261 | .arm, .armeb => @import("codegen/arm.zig").c_abi_int_return_regs, |
| | 5262 | .aarch64, .aarch64_be, .aarch64_32 => @import("codegen/aarch64.zig").c_abi_int_return_regs, |
| | 5263 | else => [_]Register{}, |
| | 5264 | }; |
| | 5265 | |
| 5232 | fn parseRegName(name: []const u8) ?Register { | 5266 | fn parseRegName(name: []const u8) ?Register { |
| 5233 | if (@hasDecl(Register, "parseRegName")) { | 5267 | if (@hasDecl(Register, "parseRegName")) { |
| 5234 | return Register.parseRegName(name); | 5268 | return Register.parseRegName(name); |