authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2021-04-02 18:57:49+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-04-02 14:46:30-07:00
log43d364afef7f0609f9d897c7ff129ba6b9b3cab0
treeeb4cf7dc62230a55b03f166ffbecd8c463ef97e9
parent12e25237309a0e358418e17ed1a71e123b89a7be

stage2 AArch64: Add ldrh and ldrb instructions

2 files changed, 75 insertions(+), 14 deletions(-)

src/codegen.zig+37
......@@ -3302,6 +3302,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
33023302 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(reg, .{ .register = .{ .rn = reg } }).toU32());
33033303 }
33043304 },
3305 .stack_offset => |unadjusted_off| {
3306 // TODO: maybe addressing from sp instead of fp
3307 const abi_size = ty.abiSize(self.target.*);
3308 const adj_off = unadjusted_off + abi_size;
3309
3310 const rn: Register = switch (arch) {
3311 .aarch64, .aarch64_be => .x29,
3312 .aarch64_32 => .w29,
3313 else => unreachable,
3314 };
3315
3316 const offset = if (math.cast(i9, adj_off)) |imm|
3317 Instruction.LoadStoreOffset.imm_post_index(-imm)
3318 else |_|
3319 Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, Type.initTag(.u64), MCValue{ .immediate = adj_off }));
3320
3321 switch (abi_size) {
3322 1, 2 => {
3323 const ldr = switch (abi_size) {
3324 1 => Instruction.ldrb,
3325 2 => Instruction.ldrh,
3326 else => unreachable, // unexpected abi size
3327 };
3328
3329 writeInt(u32, try self.code.addManyAsArray(4), ldr(reg, rn, .{
3330 .offset = offset,
3331 }).toU32());
3332 },
3333 4, 8 => {
3334 writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(reg, .{ .register = .{
3335 .rn = rn,
3336 .offset = offset,
3337 } }).toU32());
3338 },
3339 else => return self.fail(src, "TODO implement genSetReg other types abi_size={}", .{abi_size}),
3340 }
3341 },
33053342 else => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
33063343 },
33073344 .riscv64 => switch (mcv) {
src/codegen/aarch64.zig+38-14
......@@ -487,11 +487,17 @@ pub const Instruction = union(enum) {
487487 /// Which kind of load/store to perform
488488 const LoadStoreVariant = enum {
489489 /// 32-bit or 64-bit
490 normal,
491 /// 16-bit
492 half,
493 /// 8-bit
494 byte,
490 str,
491 /// 16-bit, zero-extended
492 strh,
493 /// 8-bit, zero-extended
494 strb,
495 /// 32-bit or 64-bit
496 ldr,
497 /// 16-bit, zero-extended
498 ldrh,
499 /// 8-bit, zero-extended
500 ldrb,
495501 };
496502
497503 fn loadStoreRegister(
......@@ -499,7 +505,6 @@ pub const Instruction = union(enum) {
499505 rn: Register,
500506 offset: LoadStoreOffset,
501507 variant: LoadStoreVariant,
502 load: bool,
503508 ) Instruction {
504509 const off = offset.toU12();
505510 const op1: u2 = blk: {
......@@ -512,7 +517,10 @@ pub const Instruction = union(enum) {
512517 }
513518 break :blk 0b00;
514519 };
515 const opc: u2 = if (load) 0b01 else 0b00;
520 const opc: u2 = switch (variant) {
521 .ldr, .ldrh, .ldrb => 0b01,
522 .str, .strh, .strb => 0b00,
523 };
516524 return Instruction{
517525 .LoadStoreRegister = .{
518526 .rt = rt.id(),
......@@ -523,13 +531,13 @@ pub const Instruction = union(enum) {
523531 .v = 0,
524532 .size = blk: {
525533 switch (variant) {
526 .normal => switch (rt.size()) {
534 .ldr, .str => switch (rt.size()) {
527535 32 => break :blk 0b10,
528536 64 => break :blk 0b11,
529537 else => unreachable, // unexpected register size
530538 },
531 .half => break :blk 0b01,
532 .byte => break :blk 0b00,
539 .ldrh, .strh => break :blk 0b01,
540 .ldrb, .strb => break :blk 0b00,
533541 }
534542 },
535543 },
......@@ -756,25 +764,33 @@ pub const Instruction = union(enum) {
756764
757765 pub fn ldr(rt: Register, args: LdrArgs) Instruction {
758766 switch (args) {
759 .register => |info| return loadStoreRegister(rt, info.rn, info.offset, .normal, true),
767 .register => |info| return loadStoreRegister(rt, info.rn, info.offset, .ldr),
760768 .literal => |literal| return loadLiteral(rt, literal),
761769 }
762770 }
763771
772 pub fn ldrh(rt: Register, rn: Register, args: StrArgs) Instruction {
773 return loadStoreRegister(rt, rn, args.offset, .ldrh);
774 }
775
776 pub fn ldrb(rt: Register, rn: Register, args: StrArgs) Instruction {
777 return loadStoreRegister(rt, rn, args.offset, .ldrb);
778 }
779
764780 pub const StrArgs = struct {
765781 offset: LoadStoreOffset = LoadStoreOffset.none,
766782 };
767783
768784 pub fn str(rt: Register, rn: Register, args: StrArgs) Instruction {
769 return loadStoreRegister(rt, rn, args.offset, .normal, false);
785 return loadStoreRegister(rt, rn, args.offset, .str);
770786 }
771787
772788 pub fn strh(rt: Register, rn: Register, args: StrArgs) Instruction {
773 return loadStoreRegister(rt, rn, args.offset, .half, false);
789 return loadStoreRegister(rt, rn, args.offset, .strh);
774790 }
775791
776792 pub fn strb(rt: Register, rn: Register, args: StrArgs) Instruction {
777 return loadStoreRegister(rt, rn, args.offset, .byte, false);
793 return loadStoreRegister(rt, rn, args.offset, .strb);
778794 }
779795
780796 // Load or store pair of registers
......@@ -1004,6 +1020,14 @@ test "serialize instructions" {
10041020 .inst = Instruction.ldr(.x2, .{ .literal = 0x1 }),
10051021 .expected = 0b01_011_0_00_0000000000000000001_00010,
10061022 },
1023 .{ // ldrh x7, [x4], #0xaa
1024 .inst = Instruction.ldrh(.x7, .x4, .{ .offset = Instruction.LoadStoreOffset.imm_post_index(0xaa) }),
1025 .expected = 0b01_111_0_00_01_0_010101010_01_00100_00111,
1026 },
1027 .{ // ldrb x9, [x15, #0xff]!
1028 .inst = Instruction.ldrb(.x9, .x15, .{ .offset = Instruction.LoadStoreOffset.imm_pre_index(0xff) }),
1029 .expected = 0b00_111_0_00_01_0_011111111_11_01111_01001,
1030 },
10071031 .{ // str x2, [x1]
10081032 .inst = Instruction.str(.x2, .x1, .{}),
10091033 .expected = 0b11_111_0_01_00_000000000000_00001_00010,