authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-09-26 16:08:39+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-09-26 16:20:24+02:00
log44c80fc6dcf91a3fb1bfaeb12b27087b2fcd9283
treee636497ba1ed3f12bf3f3a320f01befb614152f6
parent4c798bb0bd0043459f5b979ab3dfaee9a6f5ac97
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.builtin: sort VaList prongs a bit

1 files changed, 26 insertions(+), 13 deletions(-)

lib/std/builtin.zig+26-13
...@@ -897,32 +897,45 @@ pub const VaListXtensa = extern struct {...@@ -897,32 +897,45 @@ pub const VaListXtensa = extern struct {
897/// This data structure is used by the Zig language code generation and897/// This data structure is used by the Zig language code generation and
898/// therefore must be kept in sync with the compiler implementation.898/// therefore must be kept in sync with the compiler implementation.
899pub const VaList = switch (builtin.cpu.arch) {899pub const VaList = switch (builtin.cpu.arch) {
900 .amdgcn,
901 .powerpc64,
902 .powerpc64le,
903 .x86,
904 => *u8,
905 .avr,
906 .bpfel,
907 .bpfeb,
908 .loongarch32,
909 .loongarch64,
910 .mips,
911 .mipsel,
912 .mips64,
913 .mips64el,
914 .riscv32,
915 .riscv32be,
916 .riscv64,
917 .riscv64be,
918 .sparc,
919 .sparc64,
920 .spirv32,
921 .spirv64,
922 .wasm32,
923 .wasm64,
924 => *anyopaque,
900 .aarch64, .aarch64_be => switch (builtin.os.tag) {925 .aarch64, .aarch64_be => switch (builtin.os.tag) {
901 .windows => *u8,926 .driverkit, .ios, .macos, .tvos, .visionos, .watchos, .windows => *u8,
902 .ios, .macos, .tvos, .watchos, .visionos => *u8,
903 else => switch (builtin.zig_backend) {927 else => switch (builtin.zig_backend) {
904 else => VaListAarch64,928 else => VaListAarch64,
905 .stage2_llvm => @compileError("disabled due to miscompilations"),929 .stage2_llvm => @compileError("disabled due to miscompilations"),
906 },930 },
907 },931 },
908 .arm, .armeb, .thumb, .thumbeb => VaListArm,932 .arm, .armeb, .thumb, .thumbeb => VaListArm,
909 .amdgcn => *u8,
910 .avr => *anyopaque,
911 .bpfel, .bpfeb => *anyopaque,
912 .hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,933 .hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,
913 .loongarch32, .loongarch64 => *anyopaque,
914 .mips, .mipsel, .mips64, .mips64el => *anyopaque,
915 .riscv32, .riscv32be, .riscv64, .riscv64be => *anyopaque,
916 .powerpc, .powerpcle => switch (builtin.os.tag) {934 .powerpc, .powerpcle => switch (builtin.os.tag) {
917 .ios, .macos, .tvos, .watchos, .visionos, .aix => *u8,935 .ios, .macos, .tvos, .watchos, .visionos, .aix => *u8,
918 else => VaListPowerPc,936 else => VaListPowerPc,
919 },937 },
920 .powerpc64, .powerpc64le => *u8,
921 .sparc, .sparc64 => *anyopaque,
922 .spirv32, .spirv64 => *anyopaque,
923 .s390x => VaListS390x,938 .s390x => VaListS390x,
924 .wasm32, .wasm64 => *anyopaque,
925 .x86 => *u8,
926 .x86_64 => switch (builtin.os.tag) {939 .x86_64 => switch (builtin.os.tag) {
927 .windows => switch (builtin.zig_backend) {940 .windows => switch (builtin.zig_backend) {
928 else => *u8,941 else => *u8,