authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-02-23 12:39:58+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-02-23 21:57:59+01:00
log4683f94463cf7165bcaf88c8de73dd7ed5279c60
tree00b04a1395b44f898f5360ea149da286f294cc4f
parentacec06cfaf9a82ec8037a23993ff36fa72eb6e82
signature Commit is signed but in an unrecognized format.

stage2 AArch64: remove MIR load_memory instruction

This instruction now just represents loading from a hard-coded adrress after extracting the other use cases for load_memory into load_got and load_direct.

4 files changed, 20 insertions(+), 78 deletions(-)

src/arch/aarch64/CodeGen.zig+4-9
...@@ -3318,15 +3318,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3318,15 +3318,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3318 });3318 });
3319 },3319 },
3320 .memory => |addr| {3320 .memory => |addr| {
3321 _ = try self.addInst(.{3321 // The value is in memory at a hard-coded address.
3322 .tag = .load_memory,3322 // If the type is a pointer, it means the pointer address is at this memory location.
3323 .data = .{3323 try self.genSetReg(ty, reg, .{ .immediate = addr });
3324 .load_memory = .{3324 try self.genLdrRegister(reg, reg, ty.abiSize(self.target.*));
3325 .register = @enumToInt(reg),
3326 .addr = @intCast(u32, addr),
3327 },
3328 },
3329 });
3330 },3325 },
3331 .stack_offset => |unadjusted_off| {3326 .stack_offset => |unadjusted_off| {
3332 const abi_size = ty.abiSize(self.target.*);3327 const abi_size = ty.abiSize(self.target.*);
src/arch/aarch64/Emit.zig+12-61
...@@ -108,7 +108,6 @@ pub fn emitMir(...@@ -108,7 +108,6 @@ pub fn emitMir(
108108
109 .eor_shifted_register => try emit.mirLogicalShiftedRegister(inst),109 .eor_shifted_register => try emit.mirLogicalShiftedRegister(inst),
110110
111 .load_memory => try emit.mirLoadMemory(inst),
112 .load_memory_got => try emit.mirLoadMemoryPie(inst),111 .load_memory_got => try emit.mirLoadMemoryPie(inst),
113 .load_memory_direct => try emit.mirLoadMemoryPie(inst),112 .load_memory_direct => try emit.mirLoadMemoryPie(inst),
114113
...@@ -210,16 +209,6 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {...@@ -210,16 +209,6 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
210 .load_memory_got,209 .load_memory_got,
211 .load_memory_direct,210 .load_memory_direct,
212 => return 2 * 4,211 => return 2 * 4,
213 .load_memory => {
214 const load_memory = emit.mir.instructions.items(.data)[inst].load_memory;
215 const addr = load_memory.addr;
216
217 // movz, [movk, ...], ldr
218 if (addr <= math.maxInt(u16)) return 2 * 4;
219 if (addr <= math.maxInt(u32)) return 3 * 4;
220 if (addr <= math.maxInt(u48)) return 4 * 4;
221 return 5 * 4;
222 },
223 .pop_regs, .push_regs => {212 .pop_regs, .push_regs => {
224 const reg_list = emit.mir.instructions.items(.data)[inst].reg_list;213 const reg_list = emit.mir.instructions.items(.data)[inst].reg_list;
225 const number_of_regs = @popCount(u32, reg_list);214 const number_of_regs = @popCount(u32, reg_list);
...@@ -655,21 +644,6 @@ fn mirLogicalShiftedRegister(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -655,21 +644,6 @@ fn mirLogicalShiftedRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
655 }644 }
656}645}
657646
658fn mirLoadMemory(emit: *Emit, inst: Mir.Inst.Index) !void {
659 assert(emit.mir.instructions.items(.tag)[inst] == .load_memory);
660 const load_memory = emit.mir.instructions.items(.data)[inst].load_memory;
661 const reg = @intToEnum(Register, load_memory.register);
662 const addr = load_memory.addr;
663 // The value is in memory at a hard-coded address.
664 // If the type is a pointer, it means the pointer address is at this memory location.
665 try emit.moveImmediate(reg, addr);
666 try emit.writeInstruction(Instruction.ldr(
667 reg,
668 reg,
669 Instruction.LoadStoreOffset.none,
670 ));
671}
672
673fn mirLoadMemoryPie(emit: *Emit, inst: Mir.Inst.Index) !void {647fn mirLoadMemoryPie(emit: *Emit, inst: Mir.Inst.Index) !void {
674 const tag = emit.mir.instructions.items(.tag)[inst];648 const tag = emit.mir.instructions.items(.tag)[inst];
675 const payload = emit.mir.instructions.items(.data)[inst].payload;649 const payload = emit.mir.instructions.items(.data)[inst].payload;
...@@ -741,6 +715,7 @@ fn mirLoadStoreRegisterPair(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -741,6 +715,7 @@ fn mirLoadStoreRegisterPair(emit: *Emit, inst: Mir.Inst.Index) !void {
741fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {715fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {
742 const tag = emit.mir.instructions.items(.tag)[inst];716 const tag = emit.mir.instructions.items(.tag)[inst];
743 const load_store_stack = emit.mir.instructions.items(.data)[inst].load_store_stack;717 const load_store_stack = emit.mir.instructions.items(.data)[inst].load_store_stack;
718 const rt = load_store_stack.rt;
744719
745 const raw_offset = emit.stack_size - load_store_stack.offset;720 const raw_offset = emit.stack_size - load_store_stack.offset;
746 const offset = switch (tag) {721 const offset = switch (tag) {
...@@ -760,7 +735,7 @@ fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -760,7 +735,7 @@ fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {
760 }735 }
761 },736 },
762 .ldr_stack, .str_stack => blk: {737 .ldr_stack, .str_stack => blk: {
763 const alignment: u32 = switch (load_store_stack.rt.size()) {738 const alignment: u32 = switch (rt.size()) {
764 32 => 4,739 32 => 4,
765 64 => 8,740 64 => 8,
766 else => unreachable,741 else => unreachable,
...@@ -777,36 +752,12 @@ fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -777,36 +752,12 @@ fn mirLoadStoreStack(emit: *Emit, inst: Mir.Inst.Index) !void {
777 };752 };
778753
779 switch (tag) {754 switch (tag) {
780 .ldr_stack => try emit.writeInstruction(Instruction.ldr(755 .ldr_stack => try emit.writeInstruction(Instruction.ldr(rt, .sp, offset)),
781 load_store_stack.rt,756 .ldrb_stack => try emit.writeInstruction(Instruction.ldrb(rt, .sp, offset)),
782 Register.sp,757 .ldrh_stack => try emit.writeInstruction(Instruction.ldrh(rt, .sp, offset)),
783 offset,758 .str_stack => try emit.writeInstruction(Instruction.str(rt, .sp, offset)),
784 )),759 .strb_stack => try emit.writeInstruction(Instruction.strb(rt, .sp, offset)),
785 .ldrb_stack => try emit.writeInstruction(Instruction.ldrb(760 .strh_stack => try emit.writeInstruction(Instruction.strh(rt, .sp, offset)),
786 load_store_stack.rt,
787 Register.sp,
788 offset,
789 )),
790 .ldrh_stack => try emit.writeInstruction(Instruction.ldrh(
791 load_store_stack.rt,
792 Register.sp,
793 offset,
794 )),
795 .str_stack => try emit.writeInstruction(Instruction.str(
796 load_store_stack.rt,
797 Register.sp,
798 offset,
799 )),
800 .strb_stack => try emit.writeInstruction(Instruction.strb(
801 load_store_stack.rt,
802 Register.sp,
803 offset,
804 )),
805 .strh_stack => try emit.writeInstruction(Instruction.strh(
806 load_store_stack.rt,
807 Register.sp,
808 offset,
809 )),
810 else => unreachable,761 else => unreachable,
811 }762 }
812}763}
...@@ -914,7 +865,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -914,7 +865,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {
914 if (count == number_of_regs - 1) {865 if (count == number_of_regs - 1) {
915 try emit.writeInstruction(Instruction.ldr(866 try emit.writeInstruction(Instruction.ldr(
916 reg,867 reg,
917 Register.sp,868 .sp,
918 Instruction.LoadStoreOffset.imm_post_index(16),869 Instruction.LoadStoreOffset.imm_post_index(16),
919 ));870 ));
920 } else {871 } else {
...@@ -924,7 +875,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -924,7 +875,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {
924 try emit.writeInstruction(Instruction.ldp(875 try emit.writeInstruction(Instruction.ldp(
925 reg,876 reg,
926 other_reg,877 other_reg,
927 Register.sp,878 .sp,
928 Instruction.LoadStorePairOffset.post_index(16),879 Instruction.LoadStorePairOffset.post_index(16),
929 ));880 ));
930 }881 }
...@@ -944,7 +895,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -944,7 +895,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {
944 if (count == number_of_regs - 1) {895 if (count == number_of_regs - 1) {
945 try emit.writeInstruction(Instruction.str(896 try emit.writeInstruction(Instruction.str(
946 reg,897 reg,
947 Register.sp,898 .sp,
948 Instruction.LoadStoreOffset.imm_pre_index(-16),899 Instruction.LoadStoreOffset.imm_pre_index(-16),
949 ));900 ));
950 } else {901 } else {
...@@ -954,7 +905,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -954,7 +905,7 @@ fn mirPushPopRegs(emit: *Emit, inst: Mir.Inst.Index) !void {
954 try emit.writeInstruction(Instruction.stp(905 try emit.writeInstruction(Instruction.stp(
955 other_reg,906 other_reg,
956 reg,907 reg,
957 Register.sp,908 .sp,
958 Instruction.LoadStorePairOffset.pre_index(-16),909 Instruction.LoadStorePairOffset.pre_index(-16),
959 ));910 ));
960 }911 }
src/arch/aarch64/Mir.zig-4
...@@ -56,10 +56,6 @@ pub const Inst = struct {...@@ -56,10 +56,6 @@ pub const Inst = struct {
56 dbg_line,56 dbg_line,
57 /// Bitwise Exclusive OR (shifted register)57 /// Bitwise Exclusive OR (shifted register)
58 eor_shifted_register,58 eor_shifted_register,
59 /// Pseudo-instruction: Load memory
60 ///
61 /// Payload is `load_memory`
62 load_memory,
63 /// Payload is `LoadMemoryPie`59 /// Payload is `LoadMemoryPie`
64 load_memory_got,60 load_memory_got,
65 /// Payload is `LoadMemoryPie`61 /// Payload is `LoadMemoryPie`
src/arch/aarch64/bits.zig+4-4
...@@ -1486,19 +1486,19 @@ test "serialize instructions" {...@@ -1486,19 +1486,19 @@ test "serialize instructions" {
1486 .expected = 0b1_00_10000_1111111111111111110_00010,1486 .expected = 0b1_00_10000_1111111111111111110_00010,
1487 },1487 },
1488 .{ // stp x1, x2, [sp, #8]1488 .{ // stp x1, x2, [sp, #8]
1489 .inst = Instruction.stp(.x1, .x2, Register.sp, Instruction.LoadStorePairOffset.signed(8)),1489 .inst = Instruction.stp(.x1, .x2, .sp, Instruction.LoadStorePairOffset.signed(8)),
1490 .expected = 0b10_101_0_010_0_0000001_00010_11111_00001,1490 .expected = 0b10_101_0_010_0_0000001_00010_11111_00001,
1491 },1491 },
1492 .{ // ldp x1, x2, [sp, #8]1492 .{ // ldp x1, x2, [sp, #8]
1493 .inst = Instruction.ldp(.x1, .x2, Register.sp, Instruction.LoadStorePairOffset.signed(8)),1493 .inst = Instruction.ldp(.x1, .x2, .sp, Instruction.LoadStorePairOffset.signed(8)),
1494 .expected = 0b10_101_0_010_1_0000001_00010_11111_00001,1494 .expected = 0b10_101_0_010_1_0000001_00010_11111_00001,
1495 },1495 },
1496 .{ // stp x1, x2, [sp, #-16]!1496 .{ // stp x1, x2, [sp, #-16]!
1497 .inst = Instruction.stp(.x1, .x2, Register.sp, Instruction.LoadStorePairOffset.pre_index(-16)),1497 .inst = Instruction.stp(.x1, .x2, .sp, Instruction.LoadStorePairOffset.pre_index(-16)),
1498 .expected = 0b10_101_0_011_0_1111110_00010_11111_00001,1498 .expected = 0b10_101_0_011_0_1111110_00010_11111_00001,
1499 },1499 },
1500 .{ // ldp x1, x2, [sp], #161500 .{ // ldp x1, x2, [sp], #16
1501 .inst = Instruction.ldp(.x1, .x2, Register.sp, Instruction.LoadStorePairOffset.post_index(16)),1501 .inst = Instruction.ldp(.x1, .x2, .sp, Instruction.LoadStorePairOffset.post_index(16)),
1502 .expected = 0b10_101_0_001_1_0000010_00010_11111_00001,1502 .expected = 0b10_101_0_001_1_0000010_00010_11111_00001,
1503 },1503 },
1504 .{ // and x0, x4, x21504 .{ // and x0, x4, x2