| ... | @@ -10154,18 +10154,22 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -10154,18 +10154,22 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void { |
| 10154 | const dst_rc = regClassForType(dst_ty); | 10154 | const dst_rc = regClassForType(dst_ty); |
| 10155 | const src_rc = regClassForType(src_ty); | 10155 | const src_rc = regClassForType(src_ty); |
| 10156 | const src_mcv = try self.resolveInst(ty_op.operand); | 10156 | const src_mcv = try self.resolveInst(ty_op.operand); |
| 10157 | if (dst_rc.supersetOf(src_rc) and self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) | | |
| 10158 | break :result src_mcv; | | |
| 10159 | | 10157 | |
| 10160 | const src_lock = if (src_mcv.getReg()) |reg| self.register_manager.lockReg(reg) else null; | 10158 | const src_lock = if (src_mcv.getReg()) |reg| self.register_manager.lockReg(reg) else null; |
| 10161 | defer if (src_lock) |lock| self.register_manager.unlockReg(lock); | 10159 | defer if (src_lock) |lock| self.register_manager.unlockReg(lock); |
| 10162 | | 10160 | |
| 10163 | const dst_mcv = try self.allocRegOrMem(inst, true); | 10161 | const dst_mcv = if (dst_rc.supersetOf(src_rc) and |
| 10164 | try self.genCopy( | 10162 | self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) |
| 10165 | if (!dst_mcv.isMemory() or src_mcv.isMemory()) dst_ty else src_ty, | 10163 | src_mcv |
| 10166 | dst_mcv, | 10164 | else dst: { |
| 10167 | src_mcv, | 10165 | const dst_mcv = try self.allocRegOrMem(inst, true); |
| 10168 | ); | 10166 | try self.genCopy( |
| | 10167 | if (!dst_mcv.isMemory() or src_mcv.isMemory()) dst_ty else src_ty, |
| | 10168 | dst_mcv, |
| | 10169 | src_mcv, |
| | 10170 | ); |
| | 10171 | break :dst dst_mcv; |
| | 10172 | }; |
| 10169 | | 10173 | |
| 10170 | const dst_signedness = | 10174 | const dst_signedness = |
| 10171 | if (dst_ty.isAbiInt()) dst_ty.intInfo(self.target.*).signedness else .unsigned; | 10175 | if (dst_ty.isAbiInt()) dst_ty.intInfo(self.target.*).signedness else .unsigned; |