authorgravatar for kenta@lithdew.netKenta Iwasaki <kenta@lithdew.net> 2021-06-01 18:35:13+09:00
committergravatar for kenta@lithdew.netKenta Iwasaki <kenta@lithdew.net> 2021-06-01 18:35:13+09:00
log4909aa1da43d227ad85b2fe03a58ef1a8c12b769
treec39ff79de9b7dbee19dcec1f5f0d8ca589e8f99f
parentaad8491dbd98052e97b395ea572b186482d3b38f

os/bits: remove duplicate `sockaddr_storage` for dragonfly

5 files changed, 28 insertions(+), 37 deletions(-)

lib/std/atomic.zig+3-3
...@@ -19,7 +19,7 @@ test "std.atomic" {...@@ -19,7 +19,7 @@ test "std.atomic" {
19 _ = @import("atomic/Atomic.zig");19 _ = @import("atomic/Atomic.zig");
20}20}
2121
22pub fn fence(comptime ordering: Ordering) callconv(.Inline) void {22pub inline fn fence(comptime ordering: Ordering) void {
23 switch (ordering) {23 switch (ordering) {
24 .Acquire, .Release, .AcqRel, .SeqCst => {24 .Acquire, .Release, .AcqRel, .SeqCst => {
25 @fence(ordering);25 @fence(ordering);
...@@ -30,7 +30,7 @@ pub fn fence(comptime ordering: Ordering) callconv(.Inline) void {...@@ -30,7 +30,7 @@ pub fn fence(comptime ordering: Ordering) callconv(.Inline) void {
30 }30 }
31}31}
3232
33pub fn compilerFence(comptime ordering: Ordering) callconv(.Inline) void {33pub inline fn compilerFence(comptime ordering: Ordering) void {
34 switch (ordering) {34 switch (ordering) {
35 .Acquire, .Release, .AcqRel, .SeqCst => asm volatile ("" ::: "memory"),35 .Acquire, .Release, .AcqRel, .SeqCst => asm volatile ("" ::: "memory"),
36 else => @compileLog(ordering, " only applies to a given memory location"),36 else => @compileLog(ordering, " only applies to a given memory location"),
...@@ -45,7 +45,7 @@ test "fence/compilerFence" {...@@ -45,7 +45,7 @@ test "fence/compilerFence" {
45}45}
4646
47/// Signals to the processor that the caller is inside a busy-wait spin-loop.47/// Signals to the processor that the caller is inside a busy-wait spin-loop.
48pub fn spinLoopHint() callconv(.Inline) void {48pub inline fn spinLoopHint() void {
49 const hint_instruction = switch (target.cpu.arch) {49 const hint_instruction = switch (target.cpu.arch) {
50 // No-op instruction that can hint to save (or share with a hardware-thread) pipelining/power resources50 // No-op instruction that can hint to save (or share with a hardware-thread) pipelining/power resources
51 // https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html51 // https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
lib/std/atomic/Atomic.zig+22-22
...@@ -48,38 +48,38 @@ pub fn Atomic(comptime T: type) type {...@@ -48,38 +48,38 @@ pub fn Atomic(comptime T: type) type {
48 };48 };
49 }49 }
5050
51 pub fn swap(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {51 pub inline fn swap(self: *Self, value: T, comptime ordering: Ordering) T {
52 return self.rmw(.Xchg, value, ordering);52 return self.rmw(.Xchg, value, ordering);
53 }53 }
5454
55 pub fn compareAndSwap(55 pub inline fn compareAndSwap(
56 self: *Self,56 self: *Self,
57 compare: T,57 compare: T,
58 exchange: T,58 exchange: T,
59 comptime success: Ordering,59 comptime success: Ordering,
60 comptime failure: Ordering,60 comptime failure: Ordering,
61 ) callconv(.Inline) ?T {61 ) ?T {
62 return self.cmpxchg(true, compare, exchange, success, failure);62 return self.cmpxchg(true, compare, exchange, success, failure);
63 }63 }
6464
65 pub fn tryCompareAndSwap(65 pub inline fn tryCompareAndSwap(
66 self: *Self,66 self: *Self,
67 compare: T,67 compare: T,
68 exchange: T,68 exchange: T,
69 comptime success: Ordering,69 comptime success: Ordering,
70 comptime failure: Ordering,70 comptime failure: Ordering,
71 ) callconv(.Inline) ?T {71 ) ?T {
72 return self.cmpxchg(false, compare, exchange, success, failure);72 return self.cmpxchg(false, compare, exchange, success, failure);
73 }73 }
7474
75 fn cmpxchg(75 inline fn cmpxchg(
76 self: *Self,76 self: *Self,
77 comptime is_strong: bool,77 comptime is_strong: bool,
78 compare: T,78 compare: T,
79 exchange: T,79 exchange: T,
80 comptime success: Ordering,80 comptime success: Ordering,
81 comptime failure: Ordering,81 comptime failure: Ordering,
82 ) callconv(.Inline) ?T {82 ) ?T {
83 if (success == .Unordered or failure == .Unordered) {83 if (success == .Unordered or failure == .Unordered) {
84 @compileError(@tagName(Ordering.Unordered) ++ " is only allowed on atomic loads and stores");84 @compileError(@tagName(Ordering.Unordered) ++ " is only allowed on atomic loads and stores");
85 }85 }
...@@ -103,12 +103,12 @@ pub fn Atomic(comptime T: type) type {...@@ -103,12 +103,12 @@ pub fn Atomic(comptime T: type) type {
103 };103 };
104 }104 }
105105
106 fn rmw(106 inline fn rmw(
107 self: *Self,107 self: *Self,
108 comptime op: std.builtin.AtomicRmwOp,108 comptime op: std.builtin.AtomicRmwOp,
109 value: T,109 value: T,
110 comptime ordering: Ordering,110 comptime ordering: Ordering,
111 ) callconv(.Inline) T {111 ) T {
112 return @atomicRmw(T, &self.value, op, value, ordering);112 return @atomicRmw(T, &self.value, op, value, ordering);
113 }113 }
114114
...@@ -117,37 +117,37 @@ pub fn Atomic(comptime T: type) type {...@@ -117,37 +117,37 @@ pub fn Atomic(comptime T: type) type {
117 }117 }
118118
119 pub usingnamespace exportWhen(std.meta.trait.isNumber(T), struct {119 pub usingnamespace exportWhen(std.meta.trait.isNumber(T), struct {
120 pub fn fetchAdd(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {120 pub inline fn fetchAdd(self: *Self, value: T, comptime ordering: Ordering) T {
121 return self.rmw(.Add, value, ordering);121 return self.rmw(.Add, value, ordering);
122 }122 }
123123
124 pub fn fetchSub(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {124 pub inline fn fetchSub(self: *Self, value: T, comptime ordering: Ordering) T {
125 return self.rmw(.Sub, value, ordering);125 return self.rmw(.Sub, value, ordering);
126 }126 }
127127
128 pub fn fetchMin(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {128 pub inline fn fetchMin(self: *Self, value: T, comptime ordering: Ordering) T {
129 return self.rmw(.Min, value, ordering);129 return self.rmw(.Min, value, ordering);
130 }130 }
131131
132 pub fn fetchMax(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {132 pub inline fn fetchMax(self: *Self, value: T, comptime ordering: Ordering) T {
133 return self.rmw(.Max, value, ordering);133 return self.rmw(.Max, value, ordering);
134 }134 }
135 });135 });
136136
137 pub usingnamespace exportWhen(std.meta.trait.isIntegral(T), struct {137 pub usingnamespace exportWhen(std.meta.trait.isIntegral(T), struct {
138 pub fn fetchAnd(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {138 pub inline fn fetchAnd(self: *Self, value: T, comptime ordering: Ordering) T {
139 return self.rmw(.And, value, ordering);139 return self.rmw(.And, value, ordering);
140 }140 }
141141
142 pub fn fetchNand(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {142 pub inline fn fetchNand(self: *Self, value: T, comptime ordering: Ordering) T {
143 return self.rmw(.Nand, value, ordering);143 return self.rmw(.Nand, value, ordering);
144 }144 }
145145
146 pub fn fetchOr(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {146 pub inline fn fetchOr(self: *Self, value: T, comptime ordering: Ordering) T {
147 return self.rmw(.Or, value, ordering);147 return self.rmw(.Or, value, ordering);
148 }148 }
149149
150 pub fn fetchXor(self: *Self, value: T, comptime ordering: Ordering) callconv(.Inline) T {150 pub inline fn fetchXor(self: *Self, value: T, comptime ordering: Ordering) T {
151 return self.rmw(.Xor, value, ordering);151 return self.rmw(.Xor, value, ordering);
152 }152 }
153153
...@@ -158,24 +158,24 @@ pub fn Atomic(comptime T: type) type {...@@ -158,24 +158,24 @@ pub fn Atomic(comptime T: type) type {
158 Toggle,158 Toggle,
159 };159 };
160160
161 pub fn bitSet(self: *Self, bit: Bit, comptime ordering: Ordering) callconv(.Inline) u1 {161 pub inline fn bitSet(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
162 return bitRmw(self, .Set, bit, ordering);162 return bitRmw(self, .Set, bit, ordering);
163 }163 }
164164
165 pub fn bitReset(self: *Self, bit: Bit, comptime ordering: Ordering) callconv(.Inline) u1 {165 pub inline fn bitReset(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
166 return bitRmw(self, .Reset, bit, ordering);166 return bitRmw(self, .Reset, bit, ordering);
167 }167 }
168168
169 pub fn bitToggle(self: *Self, bit: Bit, comptime ordering: Ordering) callconv(.Inline) u1 {169 pub inline fn bitToggle(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
170 return bitRmw(self, .Toggle, bit, ordering);170 return bitRmw(self, .Toggle, bit, ordering);
171 }171 }
172172
173 fn bitRmw(173 inline fn bitRmw(
174 self: *Self,174 self: *Self,
175 comptime op: BitRmwOp,175 comptime op: BitRmwOp,
176 bit: Bit,176 bit: Bit,
177 comptime ordering: Ordering,177 comptime ordering: Ordering,
178 ) callconv(.Inline) u1 {178 ) u1 {
179 // x86 supports dedicated bitwise instructions179 // x86 supports dedicated bitwise instructions
180 if (comptime target.cpu.arch.isX86() and @sizeOf(T) >= 2 and @sizeOf(T) <= 8) {180 if (comptime target.cpu.arch.isX86() and @sizeOf(T) >= 2 and @sizeOf(T) <= 8) {
181 const instruction = switch (op) {181 const instruction = switch (op) {
lib/std/mem.zig+2-2
...@@ -1171,7 +1171,7 @@ test "mem.indexOf" {...@@ -1171,7 +1171,7 @@ test "mem.indexOf" {
1171test "mem.indexOf multibyte" {1171test "mem.indexOf multibyte" {
1172 {1172 {
1173 // make haystack and needle long enough to trigger boyer-moore-horspool algorithm1173 // make haystack and needle long enough to trigger boyer-moore-horspool algorithm
1174 const haystack = [1]u16{0} ** 100 ++ [_]u16 { 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee, 0x00ff };1174 const haystack = [1]u16{0} ** 100 ++ [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee, 0x00ff };
1175 const needle = [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee };1175 const needle = [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee };
1176 try testing.expectEqual(indexOfPos(u16, &haystack, 0, &needle), 100);1176 try testing.expectEqual(indexOfPos(u16, &haystack, 0, &needle), 100);
11771177
...@@ -1184,7 +1184,7 @@ test "mem.indexOf multibyte" {...@@ -1184,7 +1184,7 @@ test "mem.indexOf multibyte" {
11841184
1185 {1185 {
1186 // make haystack and needle long enough to trigger boyer-moore-horspool algorithm1186 // make haystack and needle long enough to trigger boyer-moore-horspool algorithm
1187 const haystack = [_]u16 { 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee, 0x00ff } ++ [1]u16{0} ** 100;1187 const haystack = [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee, 0x00ff } ++ [1]u16{0} ** 100;
1188 const needle = [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee };1188 const needle = [_]u16{ 0xbbaa, 0xccbb, 0xddcc, 0xeedd, 0xffee };
1189 try testing.expectEqual(lastIndexOf(u16, &haystack, &needle), 0);1189 try testing.expectEqual(lastIndexOf(u16, &haystack, &needle), 0);
11901190
lib/std/os/bits/dragonfly.zig-8
...@@ -696,14 +696,6 @@ pub const in_port_t = u16;...@@ -696,14 +696,6 @@ pub const in_port_t = u16;
696pub const sa_family_t = u8;696pub const sa_family_t = u8;
697pub const socklen_t = u32;697pub const socklen_t = u32;
698698
699pub const sockaddr_storage = extern struct {
700 ss_len: u8,
701 ss_family: sa_family_t,
702 __ss_pad1: [5]u8,
703 __ss_align: i64,
704 __ss_pad2: [112]u8,
705};
706
707pub const sockaddr_in = extern struct {699pub const sockaddr_in = extern struct {
708 len: u8 = @sizeOf(sockaddr_in),700 len: u8 = @sizeOf(sockaddr_in),
709 family: sa_family_t = AF_INET,701 family: sa_family_t = AF_INET,
lib/std/target.zig+1-2
...@@ -500,8 +500,7 @@ pub const Target = struct {...@@ -500,8 +500,7 @@ pub const Target = struct {
500 .haiku,500 .haiku,
501 .windows,501 .windows,
502 => return .gnu,502 => return .gnu,
503 .uefi,503 .uefi => return .msvc,
504 => return .msvc,
505 .linux,504 .linux,
506 .wasi,505 .wasi,
507 .emscripten,506 .emscripten,