authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2020-12-16 18:25:25+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2020-12-16 18:25:25+01:00
log4b62f1bd93abfa2ae5aec2240bfac9327035901b
tree7f5770a4b83716f3afa097ca481fd6be64e7b15a
parent1c40a4df094132db952157bf28253ed80646ea00

Update changes due to different CPU feature sets

llvm commit b2851aea80e5a8f0cfd6c3c5a56a6b00fb28c6b6

3 files changed, 9 insertions(+), 8 deletions(-)

lib/std/target.zig+5-5
...@@ -551,7 +551,7 @@ pub const Target = struct {...@@ -551,7 +551,7 @@ pub const Target = struct {
551 pub const Set = struct {551 pub const Set = struct {
552 ints: [usize_count]usize,552 ints: [usize_count]usize,
553553
554 pub const needed_bit_count = 168;554 pub const needed_bit_count = 192;
555 pub const byte_count = (needed_bit_count + 7) / 8;555 pub const byte_count = (needed_bit_count + 7) / 8;
556 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);556 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
557 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));557 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
...@@ -828,7 +828,7 @@ pub const Target = struct {...@@ -828,7 +828,7 @@ pub const Target = struct {
828 .amdgcn => ._NONE,828 .amdgcn => ._NONE,
829 .bpfel => ._BPF,829 .bpfel => ._BPF,
830 .bpfeb => ._BPF,830 .bpfeb => ._BPF,
831 .csky => ._CSKY,831 .csky => ._NONE,
832 .sparcv9 => ._SPARCV9,832 .sparcv9 => ._SPARCV9,
833 .s390x => ._S390,833 .s390x => ._S390,
834 .ve => ._NONE,834 .ve => ._NONE,
...@@ -1149,9 +1149,9 @@ pub const Target = struct {...@@ -1149,9 +1149,9 @@ pub const Target = struct {
11491149
1150 pub fn baseline(arch: Arch) *const Model {1150 pub fn baseline(arch: Arch) *const Model {
1151 return switch (arch) {1151 return switch (arch) {
1152 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,1152 // .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline, // TODO removed in LLVM 12
1153 .riscv32 => &riscv.cpu.baseline_rv32,1153 // .riscv32 => &riscv.cpu.baseline_rv32, // TODO removed in LLVM 12
1154 .riscv64 => &riscv.cpu.baseline_rv64,1154 // .riscv64 => &riscv.cpu.baseline_rv64, // TODO removed in LLVM 12
1155 .i386 => &x86.cpu.pentium4,1155 .i386 => &x86.cpu.pentium4,
1156 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,1156 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
11571157
src/codegen.zig+3-3
...@@ -1689,7 +1689,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1689,7 +1689,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
16891689
1690 // TODO: add Instruction.supportedOn1690 // TODO: add Instruction.supportedOn
1691 // function for ARM1691 // function for ARM
1692 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {1692 if (Target.arm.featureSetHas(self.target.cpu.features, .armv5t)) {
1693 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());1693 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
1694 } else {1694 } else {
1695 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());1695 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
...@@ -2625,7 +2625,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2625,7 +2625,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2625 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {2625 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
2626 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());2626 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());
2627 } else if (x <= math.maxInt(u16)) {2627 } else if (x <= math.maxInt(u16)) {
2628 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {2628 if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
2629 writeInt(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());2629 writeInt(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());
2630 } else {2630 } else {
2631 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());2631 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
...@@ -2634,7 +2634,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2634,7 +2634,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2634 } else {2634 } else {
2635 // TODO write constant to code and load2635 // TODO write constant to code and load
2636 // relative to pc2636 // relative to pc
2637 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {2637 if (Target.arm.featureSetHas(self.target.cpu.features, .armv7_a)) {
2638 // immediate: 0xaaaabbbb2638 // immediate: 0xaaaabbbb
2639 // movw reg, #0xbbbb2639 // movw reg, #0xbbbb
2640 // movt reg, #0xaaaa2640 // movt reg, #0xaaaa
src/target.zig+1
...@@ -240,6 +240,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -240,6 +240,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
240 .avr => .avr,240 .avr => .avr,
241 .bpfel => .bpfel,241 .bpfel => .bpfel,
242 .bpfeb => .bpfeb,242 .bpfeb => .bpfeb,
243 .csky => .csky,
243 .hexagon => .hexagon,244 .hexagon => .hexagon,
244 .mips => .mips,245 .mips => .mips,
245 .mipsel => .mipsel,246 .mipsel => .mipsel,