| ... | ... | @@ -23,7 +23,7 @@ const FeatureOverride = struct { |
| 23 | 23 | extra_deps: []const []const u8 = &.{}, |
| 24 | 24 | }; |
| 25 | 25 | |
| 26 | | const CpuOverride = struct { |
| 26 | const ModelOverride = struct { |
| 27 | 27 | llvm_name: []const u8, |
| 28 | 28 | /// If true, completely omit the CPU; as if it does not exist. |
| 29 | 29 | omit: bool = false, |
| ... | ... | @@ -33,7 +33,7 @@ const CpuOverride = struct { |
| 33 | 33 | extra_deps: []const []const u8 = &.{}, |
| 34 | 34 | }; |
| 35 | 35 | |
| 36 | | const Cpu = struct { |
| 36 | const Model = struct { |
| 37 | 37 | llvm_name: ?[]const u8, |
| 38 | 38 | zig_name: []const u8, |
| 39 | 39 | features: []const []const u8, |
| ... | ... | @@ -55,8 +55,8 @@ const ArchTarget = struct { |
| 55 | 55 | }, |
| 56 | 56 | feature_overrides: []const FeatureOverride = &.{}, |
| 57 | 57 | extra_features: []const Feature = &.{}, |
| 58 | | cpu_overrides: []const CpuOverride = &.{}, |
| 59 | | extra_cpus: []const Cpu = &.{}, |
| 58 | model_overrides: []const ModelOverride = &.{}, |
| 59 | extra_models: []const Model = &.{}, |
| 60 | 60 | branch_quota: ?usize = null, |
| 61 | 61 | }; |
| 62 | 62 | |
| ... | ... | @@ -442,7 +442,7 @@ const targets = [_]ArchTarget{ |
| 442 | 442 | .flatten = true, |
| 443 | 443 | }, |
| 444 | 444 | }, |
| 445 | | .cpu_overrides = &.{ |
| 445 | .model_overrides = &.{ |
| 446 | 446 | .{ |
| 447 | 447 | // Who thought this alias was a good idea? Upgrade your compiler and suddenly your |
| 448 | 448 | // programs SIGILL because this changed meaning. Brilliant. |
| ... | ... | @@ -450,7 +450,7 @@ const targets = [_]ArchTarget{ |
| 450 | 450 | .omit = true, |
| 451 | 451 | }, |
| 452 | 452 | }, |
| 453 | | .extra_cpus = &.{ |
| 453 | .extra_models = &.{ |
| 454 | 454 | .{ |
| 455 | 455 | .llvm_name = null, |
| 456 | 456 | .zig_name = "exynos_m1", |
| ... | ... | @@ -529,7 +529,7 @@ const targets = [_]ArchTarget{ |
| 529 | 529 | .deps = &.{}, |
| 530 | 530 | }, |
| 531 | 531 | }, |
| 532 | | .extra_cpus = &.{ |
| 532 | .extra_models = &.{ |
| 533 | 533 | .{ |
| 534 | 534 | .llvm_name = null, |
| 535 | 535 | .zig_name = "ev4", |
| ... | ... | @@ -1100,7 +1100,7 @@ const targets = [_]ArchTarget{ |
| 1100 | 1100 | .deps = &.{"strict_align"}, |
| 1101 | 1101 | }, |
| 1102 | 1102 | }, |
| 1103 | | .cpu_overrides = &.{ |
| 1103 | .model_overrides = &.{ |
| 1104 | 1104 | .{ |
| 1105 | 1105 | .llvm_name = "cortex-m4", |
| 1106 | 1106 | .omit_deps = &.{"vfp4d16sp"}, |
| ... | ... | @@ -1158,7 +1158,7 @@ const targets = [_]ArchTarget{ |
| 1158 | 1158 | .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, |
| 1159 | 1159 | }, |
| 1160 | 1160 | }, |
| 1161 | | .extra_cpus = &.{ |
| 1161 | .extra_models = &.{ |
| 1162 | 1162 | .{ |
| 1163 | 1163 | .llvm_name = "generic", |
| 1164 | 1164 | .zig_name = "baseline", |
| ... | ... | @@ -1318,7 +1318,7 @@ const targets = [_]ArchTarget{ |
| 1318 | 1318 | .deps = &.{ "max_2", "v1_1" }, |
| 1319 | 1319 | }, |
| 1320 | 1320 | }, |
| 1321 | | .extra_cpus = &.{ |
| 1321 | .extra_models = &.{ |
| 1322 | 1322 | .{ |
| 1323 | 1323 | .llvm_name = null, |
| 1324 | 1324 | .zig_name = "ts_1", |
| ... | ... | @@ -1454,7 +1454,7 @@ const targets = [_]ArchTarget{ |
| 1454 | 1454 | .deps = &.{"v3_2"}, |
| 1455 | 1455 | }, |
| 1456 | 1456 | }, |
| 1457 | | .extra_cpus = &.{ |
| 1457 | .extra_models = &.{ |
| 1458 | 1458 | .{ |
| 1459 | 1459 | .llvm_name = null, |
| 1460 | 1460 | .zig_name = "coolidge_v1", |
| ... | ... | @@ -1484,7 +1484,7 @@ const targets = [_]ArchTarget{ |
| 1484 | 1484 | .name = "LoongArch", |
| 1485 | 1485 | .td_name = "LoongArch", |
| 1486 | 1486 | }, |
| 1487 | | .cpu_overrides = &.{ |
| 1487 | .model_overrides = &.{ |
| 1488 | 1488 | .{ |
| 1489 | 1489 | .llvm_name = "generic", |
| 1490 | 1490 | .omit = true, |
| ... | ... | @@ -1502,7 +1502,7 @@ const targets = [_]ArchTarget{ |
| 1502 | 1502 | .omit = true, |
| 1503 | 1503 | }, |
| 1504 | 1504 | }, |
| 1505 | | .extra_cpus = &.{ |
| 1505 | .extra_models = &.{ |
| 1506 | 1506 | .{ |
| 1507 | 1507 | .llvm_name = null, |
| 1508 | 1508 | .zig_name = "generic_la64", |
| ... | ... | @@ -1581,7 +1581,7 @@ const targets = [_]ArchTarget{ |
| 1581 | 1581 | .deps = &.{}, |
| 1582 | 1582 | }, |
| 1583 | 1583 | }, |
| 1584 | | .extra_cpus = &.{ |
| 1584 | .extra_models = &.{ |
| 1585 | 1585 | .{ |
| 1586 | 1586 | .llvm_name = null, |
| 1587 | 1587 | .zig_name = "r3000a", |
| ... | ... | @@ -1633,13 +1633,13 @@ const targets = [_]ArchTarget{ |
| 1633 | 1633 | .omit = true, |
| 1634 | 1634 | }, |
| 1635 | 1635 | }, |
| 1636 | | .cpu_overrides = &.{ |
| 1636 | .model_overrides = &.{ |
| 1637 | 1637 | .{ |
| 1638 | 1638 | .llvm_name = "ppc32", |
| 1639 | 1639 | .omit = true, |
| 1640 | 1640 | }, |
| 1641 | 1641 | }, |
| 1642 | | .extra_cpus = &.{ |
| 1642 | .extra_models = &.{ |
| 1643 | 1643 | .{ |
| 1644 | 1644 | .llvm_name = null, |
| 1645 | 1645 | .zig_name = "cell", |
| ... | ... | @@ -1686,7 +1686,7 @@ const targets = [_]ArchTarget{ |
| 1686 | 1686 | .deps = &.{}, |
| 1687 | 1687 | }, |
| 1688 | 1688 | }, |
| 1689 | | .extra_cpus = &.{ |
| 1689 | .extra_models = &.{ |
| 1690 | 1690 | .{ |
| 1691 | 1691 | .llvm_name = null, |
| 1692 | 1692 | .zig_name = "p1", |
| ... | ... | @@ -1707,7 +1707,7 @@ const targets = [_]ArchTarget{ |
| 1707 | 1707 | }, |
| 1708 | 1708 | .branch_quota = 2000, |
| 1709 | 1709 | .extra_features = spirv_extra_features, |
| 1710 | | .extra_cpus = &.{ |
| 1710 | .extra_models = &.{ |
| 1711 | 1711 | .{ |
| 1712 | 1712 | .llvm_name = null, |
| 1713 | 1713 | .zig_name = "vulkan_v1_2", |
| ... | ... | @@ -1733,7 +1733,7 @@ const targets = [_]ArchTarget{ |
| 1733 | 1733 | .flatten = true, |
| 1734 | 1734 | }, |
| 1735 | 1735 | }, |
| 1736 | | .extra_cpus = &.{ |
| 1736 | .extra_models = &.{ |
| 1737 | 1737 | .{ |
| 1738 | 1738 | .llvm_name = null, |
| 1739 | 1739 | .zig_name = "baseline_rv32", |
| ... | ... | @@ -1773,13 +1773,13 @@ const targets = [_]ArchTarget{ |
| 1773 | 1773 | .deps = &.{}, |
| 1774 | 1774 | }, |
| 1775 | 1775 | }, |
| 1776 | | .cpu_overrides = &.{ |
| 1776 | .model_overrides = &.{ |
| 1777 | 1777 | .{ |
| 1778 | 1778 | .llvm_name = "generic", |
| 1779 | 1779 | .omit = true, |
| 1780 | 1780 | }, |
| 1781 | 1781 | }, |
| 1782 | | .extra_cpus = &.{ |
| 1782 | .extra_models = &.{ |
| 1783 | 1783 | .{ |
| 1784 | 1784 | .llvm_name = null, |
| 1785 | 1785 | .zig_name = "ve10", |
| ... | ... | @@ -1830,7 +1830,7 @@ const targets = [_]ArchTarget{ |
| 1830 | 1830 | .deps = &.{"bulk_memory_opt"}, |
| 1831 | 1831 | }, |
| 1832 | 1832 | }, |
| 1833 | | .cpu_overrides = &.{ |
| 1833 | .model_overrides = &.{ |
| 1834 | 1834 | .{ |
| 1835 | 1835 | .llvm_name = "bleeding-edge", |
| 1836 | 1836 | .omit = true, |
| ... | ... | @@ -1840,7 +1840,7 @@ const targets = [_]ArchTarget{ |
| 1840 | 1840 | .omit = true, |
| 1841 | 1841 | }, |
| 1842 | 1842 | }, |
| 1843 | | .extra_cpus = &.{ |
| 1843 | .extra_models = &.{ |
| 1844 | 1844 | .{ |
| 1845 | 1845 | .llvm_name = null, |
| 1846 | 1846 | .zig_name = "wasm_v1_0", |
| ... | ... | @@ -1951,7 +1951,7 @@ const targets = [_]ArchTarget{ |
| 1951 | 1951 | .deps = &.{}, |
| 1952 | 1952 | }, |
| 1953 | 1953 | }, |
| 1954 | | .cpu_overrides = &.{ |
| 1954 | .model_overrides = &.{ |
| 1955 | 1955 | .{ |
| 1956 | 1956 | .llvm_name = "amdfam10", |
| 1957 | 1957 | .extra_deps = &.{"3dnowa"}, |
| ... | ... | @@ -2291,7 +2291,7 @@ const targets = [_]ArchTarget{ |
| 2291 | 2291 | .omit = true, |
| 2292 | 2292 | }, |
| 2293 | 2293 | }, |
| 2294 | | .extra_cpus = &.{ |
| 2294 | .extra_models = &.{ |
| 2295 | 2295 | .{ |
| 2296 | 2296 | .llvm_name = null, |
| 2297 | 2297 | .zig_name = "i86", |
| ... | ... | @@ -2327,7 +2327,7 @@ const targets = [_]ArchTarget{ |
| 2327 | 2327 | .deps = &.{"xs3"}, |
| 2328 | 2328 | }, |
| 2329 | 2329 | }, |
| 2330 | | .cpu_overrides = &.{ |
| 2330 | .model_overrides = &.{ |
| 2331 | 2331 | .{ |
| 2332 | 2332 | .llvm_name = "generic", |
| 2333 | 2333 | .omit = true, |
| ... | ... | @@ -2337,7 +2337,7 @@ const targets = [_]ArchTarget{ |
| 2337 | 2337 | .omit = true, |
| 2338 | 2338 | }, |
| 2339 | 2339 | }, |
| 2340 | | .extra_cpus = &.{ |
| 2340 | .extra_models = &.{ |
| 2341 | 2341 | .{ |
| 2342 | 2342 | .llvm_name = null, |
| 2343 | 2343 | .zig_name = "xs1b", |
| ... | ... | @@ -2449,7 +2449,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2449 | 2449 | |
| 2450 | 2450 | var features_table = std.StringHashMap(Feature).init(arena); |
| 2451 | 2451 | var all_features = std.array_list.Managed(Feature).init(arena); |
| 2452 | | var all_cpus = std.array_list.Managed(Cpu).init(arena); |
| 2452 | var all_models = std.array_list.Managed(Model).init(arena); |
| 2453 | 2453 | |
| 2454 | 2454 | if (target.llvm) |llvm| { |
| 2455 | 2455 | const tblgen_progress = progress_node.start("running llvm-tblgen", 0); |
| ... | ... | @@ -2509,7 +2509,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2509 | 2509 | llvm: []const u8, |
| 2510 | 2510 | zig: []const u8, |
| 2511 | 2511 | }; |
| 2512 | | var cpu_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena); |
| 2512 | var model_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena); |
| 2513 | 2513 | |
| 2514 | 2514 | { |
| 2515 | 2515 | var it = root_map.iterator(); |
| ... | ... | @@ -2523,7 +2523,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2523 | 2523 | const llvm_alias = kv.value_ptr.object.get("Name").?.string; |
| 2524 | 2524 | const llvm_name = kv.value_ptr.object.get("Alias").?.string; |
| 2525 | 2525 | |
| 2526 | | const gop = try cpu_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name)); |
| 2526 | const gop = try model_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name)); |
| 2527 | 2527 | |
| 2528 | 2528 | if (!gop.found_existing) { |
| 2529 | 2529 | gop.value_ptr.* = .empty; |
| ... | ... | @@ -2634,16 +2634,16 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2634 | 2634 | var deps = std.array_list.Managed([]const u8).init(arena); |
| 2635 | 2635 | var omit_deps: []const []const u8 = &.{}; |
| 2636 | 2636 | var extra_deps: []const []const u8 = &.{}; |
| 2637 | | const omitted = for (target.cpu_overrides) |cpu_override| { |
| 2638 | | if (mem.eql(u8, llvm_name, cpu_override.llvm_name)) { |
| 2639 | | if (cpu_override.omit) { |
| 2637 | const omitted = for (target.model_overrides) |model_override| { |
| 2638 | if (mem.eql(u8, llvm_name, model_override.llvm_name)) { |
| 2639 | if (model_override.omit) { |
| 2640 | 2640 | break true; |
| 2641 | 2641 | } |
| 2642 | | if (cpu_override.zig_name) |override_name| { |
| 2642 | if (model_override.zig_name) |override_name| { |
| 2643 | 2643 | zig_name = override_name; |
| 2644 | 2644 | } |
| 2645 | | omit_deps = cpu_override.omit_deps; |
| 2646 | | extra_deps = cpu_override.extra_deps; |
| 2645 | omit_deps = model_override.omit_deps; |
| 2646 | extra_deps = model_override.extra_deps; |
| 2647 | 2647 | break false; |
| 2648 | 2648 | } |
| 2649 | 2649 | } else false; |
| ... | ... | @@ -2681,19 +2681,19 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2681 | 2681 | )) orelse continue; |
| 2682 | 2682 | try deps.append(feature_zig_name); |
| 2683 | 2683 | } |
| 2684 | | try all_cpus.append(.{ |
| 2684 | try all_models.append(.{ |
| 2685 | 2685 | .llvm_name = llvm_name, |
| 2686 | 2686 | .zig_name = zig_name, |
| 2687 | 2687 | .features = deps.items, |
| 2688 | 2688 | }); |
| 2689 | 2689 | |
| 2690 | | if (cpu_aliases.get(zig_name)) |aliases| { |
| 2690 | if (model_aliases.get(zig_name)) |aliases| { |
| 2691 | 2691 | alias_it: for (aliases.items) |alias| { |
| 2692 | | for (target.cpu_overrides) |cpu_override| { |
| 2693 | | if (mem.eql(u8, alias.llvm, cpu_override.llvm_name) and cpu_override.omit) continue :alias_it; |
| 2692 | for (target.model_overrides) |model_override| { |
| 2693 | if (mem.eql(u8, alias.llvm, model_override.llvm_name) and model_override.omit) continue :alias_it; |
| 2694 | 2694 | } |
| 2695 | 2695 | |
| 2696 | | try all_cpus.append(.{ |
| 2696 | try all_models.append(.{ |
| 2697 | 2697 | .llvm_name = alias.llvm, |
| 2698 | 2698 | .zig_name = alias.zig, |
| 2699 | 2699 | .features = deps.items, |
| ... | ... | @@ -2711,11 +2711,11 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2711 | 2711 | try features_table.put(extra_feature.zig_name, extra_feature); |
| 2712 | 2712 | try all_features.append(extra_feature); |
| 2713 | 2713 | } |
| 2714 | | for (target.extra_cpus) |extra_cpu| { |
| 2715 | | try all_cpus.append(extra_cpu); |
| 2714 | for (target.extra_models) |extra_model| { |
| 2715 | try all_models.append(extra_model); |
| 2716 | 2716 | } |
| 2717 | 2717 | mem.sort(Feature, all_features.items, {}, featureLessThan); |
| 2718 | | mem.sort(Cpu, all_cpus.items, {}, cpuLessThan); |
| 2718 | mem.sort(Model, all_models.items, {}, modelLessThan); |
| 2719 | 2719 | |
| 2720 | 2720 | const render_progress = progress_node.start("rendering Zig code", 0); |
| 2721 | 2721 | |
| ... | ... | @@ -2838,29 +2838,29 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2838 | 2838 | \\pub const cpu = struct { |
| 2839 | 2839 | \\ |
| 2840 | 2840 | ); |
| 2841 | | for (all_cpus.items) |cpu| { |
| 2841 | for (all_models.items) |model| { |
| 2842 | 2842 | var deps_set = std.StringHashMap(void).init(arena); |
| 2843 | | for (cpu.features) |feature_zig_name| { |
| 2843 | for (model.features) |feature_zig_name| { |
| 2844 | 2844 | try putDep(&deps_set, features_table, feature_zig_name); |
| 2845 | 2845 | } |
| 2846 | 2846 | try pruneFeatures(arena, features_table, &deps_set); |
| 2847 | | var cpu_features = std.array_list.Managed([]const u8).init(arena); |
| 2847 | var model_features = std.array_list.Managed([]const u8).init(arena); |
| 2848 | 2848 | { |
| 2849 | 2849 | var it = deps_set.keyIterator(); |
| 2850 | 2850 | while (it.next()) |key| { |
| 2851 | | try cpu_features.append(key.*); |
| 2851 | try model_features.append(key.*); |
| 2852 | 2852 | } |
| 2853 | 2853 | } |
| 2854 | | mem.sort([]const u8, cpu_features.items, {}, asciiLessThan); |
| 2855 | | if (cpu.llvm_name) |llvm_name| { |
| 2854 | mem.sort([]const u8, model_features.items, {}, asciiLessThan); |
| 2855 | if (model.llvm_name) |llvm_name| { |
| 2856 | 2856 | try w.print( |
| 2857 | 2857 | \\ pub const {f}: CpuModel = .{{ |
| 2858 | 2858 | \\ .name = "{f}", |
| 2859 | 2859 | \\ .llvm_name = "{f}", |
| 2860 | 2860 | \\ .features = featureSet(&[_]Feature{{ |
| 2861 | 2861 | , .{ |
| 2862 | | std.zig.fmtId(cpu.zig_name), |
| 2863 | | std.zig.fmtString(cpu.zig_name), |
| 2862 | std.zig.fmtId(model.zig_name), |
| 2863 | std.zig.fmtString(model.zig_name), |
| 2864 | 2864 | std.zig.fmtString(llvm_name), |
| 2865 | 2865 | }); |
| 2866 | 2866 | } else { |
| ... | ... | @@ -2870,11 +2870,11 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2870 | 2870 | \\ .llvm_name = null, |
| 2871 | 2871 | \\ .features = featureSet(&[_]Feature{{ |
| 2872 | 2872 | , .{ |
| 2873 | | std.zig.fmtId(cpu.zig_name), |
| 2874 | | std.zig.fmtString(cpu.zig_name), |
| 2873 | std.zig.fmtId(model.zig_name), |
| 2874 | std.zig.fmtString(model.zig_name), |
| 2875 | 2875 | }); |
| 2876 | 2876 | } |
| 2877 | | if (cpu_features.items.len == 0) { |
| 2877 | if (model_features.items.len == 0) { |
| 2878 | 2878 | try w.writeAll( |
| 2879 | 2879 | \\}), |
| 2880 | 2880 | \\ }; |
| ... | ... | @@ -2882,7 +2882,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { |
| 2882 | 2882 | ); |
| 2883 | 2883 | } else { |
| 2884 | 2884 | try w.writeAll("\n"); |
| 2885 | | for (cpu_features.items) |feature_zig_name| { |
| 2885 | for (model_features.items) |feature_zig_name| { |
| 2886 | 2886 | try w.print(" .{f},\n", .{std.zig.fmtIdPU(feature_zig_name)}); |
| 2887 | 2887 | } |
| 2888 | 2888 | try w.writeAll( |
| ... | ... | @@ -2920,7 +2920,7 @@ fn featureLessThan(_: void, a: Feature, b: Feature) bool { |
| 2920 | 2920 | return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name); |
| 2921 | 2921 | } |
| 2922 | 2922 | |
| 2923 | | fn cpuLessThan(_: void, a: Cpu, b: Cpu) bool { |
| 2923 | fn modelLessThan(_: void, a: Model, b: Model) bool { |
| 2924 | 2924 | return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name); |
| 2925 | 2925 | } |
| 2926 | 2926 | |
Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 04:34:02+02:00