authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-04-28 20:39:38-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-01 19:22:52-04:00
log4ec49da5f6a6a8e77cdb66b8f814718bf11fffef
tree38e53fbeadbffa706bff35209613a090bcbd5201
parent7c9891d7b7d09060630693231702f27669dd0dc9

x86_64: implement a bunch of floating point stuff

7 files changed, 486 insertions(+), 116 deletions(-)

src/arch/x86_64/CodeGen.zig+358-80
...@@ -1297,9 +1297,10 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {...@@ -1297,9 +1297,10 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
1297 .ceil,1297 .ceil,
1298 .round,1298 .round,
1299 .trunc_float,1299 .trunc_float,
1300 .neg,
1301 => try self.airUnaryMath(inst),1300 => try self.airUnaryMath(inst),
13021301
1302 .neg => try self.airNeg(inst),
1303
1303 .add_with_overflow => try self.airAddSubWithOverflow(inst),1304 .add_with_overflow => try self.airAddSubWithOverflow(inst),
1304 .sub_with_overflow => try self.airAddSubWithOverflow(inst),1305 .sub_with_overflow => try self.airAddSubWithOverflow(inst),
1305 .mul_with_overflow => try self.airMulWithOverflow(inst),1306 .mul_with_overflow => try self.airMulWithOverflow(inst),
...@@ -1881,7 +1882,7 @@ pub fn spillRegisters(self: *Self, registers: []const Register) !void {...@@ -1881,7 +1882,7 @@ pub fn spillRegisters(self: *Self, registers: []const Register) !void {
1881/// allocated. A second call to `copyToTmpRegister` may return the same register.1882/// allocated. A second call to `copyToTmpRegister` may return the same register.
1882/// This can have a side effect of spilling instructions to the stack to free up a register.1883/// This can have a side effect of spilling instructions to the stack to free up a register.
1883fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {1884fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
1884 const reg: Register = try self.register_manager.allocReg(null, try self.regClassForType(ty));1885 const reg = try self.register_manager.allocReg(null, try self.regClassForType(ty));
1885 try self.genSetReg(reg, ty, mcv);1886 try self.genSetReg(reg, ty, mcv);
1886 return reg;1887 return reg;
1887}1888}
...@@ -1924,16 +1925,48 @@ fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {...@@ -1924,16 +1925,48 @@ fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {
19241925
1925fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {1926fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
1926 const ty_op = self.air.instructions.items(.data)[inst].ty_op;1927 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
1927 _ = ty_op;1928 const dst_ty = self.air.typeOfIndex(inst);
1928 return self.fail("TODO implement airFptrunc for {}", .{self.target.cpu.arch});1929 const src_ty = self.air.typeOf(ty_op.operand);
1929 // return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });1930 if (dst_ty.floatBits(self.target.*) != 32 or src_ty.floatBits(self.target.*) != 64 or
1931 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
1932 return self.fail("TODO implement airFptrunc from {} to {}", .{
1933 src_ty.fmt(self.bin_file.options.module.?),
1934 dst_ty.fmt(self.bin_file.options.module.?),
1935 });
1936
1937 const src_mcv = try self.resolveInst(ty_op.operand);
1938 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
1939 src_mcv
1940 else
1941 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
1942 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
1943 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
1944
1945 try self.genBinOpMir(.cvtsd2ss, src_ty, dst_mcv, src_mcv);
1946 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
1930}1947}
19311948
1932fn airFpext(self: *Self, inst: Air.Inst.Index) !void {1949fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
1933 const ty_op = self.air.instructions.items(.data)[inst].ty_op;1950 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
1934 _ = ty_op;1951 const dst_ty = self.air.typeOfIndex(inst);
1935 return self.fail("TODO implement airFpext for {}", .{self.target.cpu.arch});1952 const src_ty = self.air.typeOf(ty_op.operand);
1936 // return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });1953 if (dst_ty.floatBits(self.target.*) != 64 or src_ty.floatBits(self.target.*) != 32 or
1954 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
1955 return self.fail("TODO implement airFpext from {} to {}", .{
1956 src_ty.fmt(self.bin_file.options.module.?),
1957 dst_ty.fmt(self.bin_file.options.module.?),
1958 });
1959
1960 const src_mcv = try self.resolveInst(ty_op.operand);
1961 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
1962 src_mcv
1963 else
1964 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
1965 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
1966 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
1967
1968 try self.genBinOpMir(.cvtss2sd, src_ty, dst_mcv, src_mcv);
1969 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
1937}1970}
19381971
1939fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {1972fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
...@@ -3953,10 +3986,65 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {...@@ -3953,10 +3986,65 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
3953 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });3986 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
3954}3987}
39553988
3989fn airNeg(self: *Self, inst: Air.Inst.Index) !void {
3990 const un_op = self.air.instructions.items(.data)[inst].un_op;
3991 const ty = self.air.typeOf(un_op);
3992 const ty_bits = ty.floatBits(self.target.*);
3993
3994 var arena = std.heap.ArenaAllocator.init(self.gpa);
3995 defer arena.deinit();
3996
3997 const ExpectedContents = union {
3998 f16: Value.Payload.Float_16,
3999 f32: Value.Payload.Float_32,
4000 f64: Value.Payload.Float_64,
4001 f80: Value.Payload.Float_80,
4002 f128: Value.Payload.Float_128,
4003 };
4004 var stack align(@alignOf(ExpectedContents)) =
4005 std.heap.stackFallback(@sizeOf(ExpectedContents), arena.allocator());
4006
4007 var vec_pl = Type.Payload.Array{
4008 .base = .{ .tag = .vector },
4009 .data = .{
4010 .len = @divExact(128, ty_bits),
4011 .elem_type = ty,
4012 },
4013 };
4014 const vec_ty = Type.initPayload(&vec_pl.base);
4015
4016 var sign_pl = Value.Payload.SubValue{
4017 .base = .{ .tag = .repeated },
4018 .data = try Value.floatToValue(-0.0, stack.get(), ty, self.target.*),
4019 };
4020 const sign_val = Value.initPayload(&sign_pl.base);
4021
4022 const sign_mcv = try self.genTypedValue(.{ .ty = vec_ty, .val = sign_val });
4023
4024 const src_mcv = try self.resolveInst(un_op);
4025 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4026 src_mcv
4027 else
4028 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
4029 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
4030 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
4031
4032 try self.genBinOpMir(switch (ty_bits) {
4033 32 => .xorps,
4034 64 => .xorpd,
4035 else => return self.fail("TODO implement airNeg for {}", .{
4036 ty.fmt(self.bin_file.options.module.?),
4037 }),
4038 }, vec_ty, dst_mcv, sign_mcv);
4039 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
4040}
4041
3956fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {4042fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {
3957 const un_op = self.air.instructions.items(.data)[inst].un_op;4043 const un_op = self.air.instructions.items(.data)[inst].un_op;
3958 _ = un_op;4044 _ = un_op;
3959 return self.fail("TODO implement airUnaryMath for {}", .{self.target.cpu.arch});4045 return self.fail("TODO implement airUnaryMath for {}", .{
4046 self.air.instructions.items(.tag)[inst],
4047 });
3960 //return self.finishAir(inst, result, .{ un_op, .none, .none });4048 //return self.finishAir(inst, result, .{ un_op, .none, .none });
3961}4049}
39624050
...@@ -4109,7 +4197,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro...@@ -4109,7 +4197,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro
4109fn airLoad(self: *Self, inst: Air.Inst.Index) !void {4197fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
4110 const ty_op = self.air.instructions.items(.data)[inst].ty_op;4198 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
4111 const elem_ty = self.air.typeOfIndex(inst);4199 const elem_ty = self.air.typeOfIndex(inst);
4112 const elem_size = elem_ty.abiSize(self.target.*);
4113 const result: MCValue = result: {4200 const result: MCValue = result: {
4114 if (!elem_ty.hasRuntimeBitsIgnoreComptime()) break :result .none;4201 if (!elem_ty.hasRuntimeBitsIgnoreComptime()) break :result .none;
41154202
...@@ -4117,14 +4204,20 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {...@@ -4117,14 +4204,20 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
4117 const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rdi, .rsi, .rcx });4204 const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rdi, .rsi, .rcx });
4118 defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);4205 defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
41194206
4207 const ptr_ty = self.air.typeOf(ty_op.operand);
4208 const elem_size = elem_ty.abiSize(self.target.*);
4209
4210 const elem_rc = try self.regClassForType(elem_ty);
4211 const ptr_rc = try self.regClassForType(ptr_ty);
4212
4120 const ptr_mcv = try self.resolveInst(ty_op.operand);4213 const ptr_mcv = try self.resolveInst(ty_op.operand);
4121 const dst_mcv = if (elem_size <= 8 and self.reuseOperand(inst, ty_op.operand, 0, ptr_mcv))4214 const dst_mcv = if (elem_size <= 8 and elem_rc.supersetOf(ptr_rc) and
4215 self.reuseOperand(inst, ty_op.operand, 0, ptr_mcv))
4122 // The MCValue that holds the pointer can be re-used as the value.4216 // The MCValue that holds the pointer can be re-used as the value.
4123 ptr_mcv4217 ptr_mcv
4124 else4218 else
4125 try self.allocRegOrMem(inst, true);4219 try self.allocRegOrMem(inst, true);
41264220
4127 const ptr_ty = self.air.typeOf(ty_op.operand);
4128 if (ptr_ty.ptrInfo().data.host_size > 0) {4221 if (ptr_ty.ptrInfo().data.host_size > 0) {
4129 try self.packedLoad(dst_mcv, ptr_ty, ptr_mcv);4222 try self.packedLoad(dst_mcv, ptr_ty, ptr_mcv);
4130 } else {4223 } else {
...@@ -4346,17 +4439,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -4346,17 +4439,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
43464439
4347 switch (src_mcv) {4440 switch (src_mcv) {
4348 .load_frame => |frame_addr| {4441 .load_frame => |frame_addr| {
4349 const field_abi_size = @intCast(u32, field_ty.abiSize(self.target.*));4442 if (field_off % 8 == 0) {
4350 const limb_abi_size = @min(field_abi_size, 8);4443 const off_mcv =
4351 const limb_abi_bits = limb_abi_size * 8;4444 src_mcv.address().offset(@intCast(i32, @divExact(field_off, 8))).deref();
4352 const field_byte_off = @intCast(i32, field_off / limb_abi_bits * limb_abi_size);
4353 const field_bit_off = field_off % limb_abi_bits;
4354
4355 if (field_bit_off == 0) {
4356 const off_mcv = MCValue{ .load_frame = .{
4357 .index = frame_addr.index,
4358 .off = frame_addr.off + field_byte_off,
4359 } };
4360 if (self.reuseOperand(inst, operand, 0, src_mcv)) break :result off_mcv;4445 if (self.reuseOperand(inst, operand, 0, src_mcv)) break :result off_mcv;
43614446
4362 const dst_mcv = try self.allocRegOrMem(inst, true);4447 const dst_mcv = try self.allocRegOrMem(inst, true);
...@@ -4364,6 +4449,12 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -4364,6 +4449,12 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
4364 break :result dst_mcv;4449 break :result dst_mcv;
4365 }4450 }
43664451
4452 const field_abi_size = @intCast(u32, field_ty.abiSize(self.target.*));
4453 const limb_abi_size = @min(field_abi_size, 8);
4454 const limb_abi_bits = limb_abi_size * 8;
4455 const field_byte_off = @intCast(i32, field_off / limb_abi_bits * limb_abi_size);
4456 const field_bit_off = field_off % limb_abi_bits;
4457
4367 if (field_abi_size > 8) {4458 if (field_abi_size > 8) {
4368 return self.fail("TODO implement struct_field_val with large packed field", .{});4459 return self.fail("TODO implement struct_field_val with large packed field", .{});
4369 }4460 }
...@@ -5181,24 +5272,69 @@ fn genBinOp(...@@ -5181,24 +5272,69 @@ fn genBinOp(
5181 switch (tag) {5272 switch (tag) {
5182 .add,5273 .add,
5183 .addwrap,5274 .addwrap,
5184 => try self.genBinOpMir(switch (lhs_ty.tag()) {5275 => try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {
5185 else => .add,5276 else => .add,
5186 .f32 => .addss,5277 .Float => switch (lhs_ty.floatBits(self.target.*)) {
5187 .f64 => .addsd,5278 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
5279 .addss
5280 else
5281 return self.fail("TODO implement genBinOp for {s} {} without sse", .{
5282 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5283 }),
5284 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
5285 .addsd
5286 else
5287 return self.fail("TODO implement genBinOp for {s} {} without sse2", .{
5288 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5289 }),
5290 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5291 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5292 }),
5293 },
5188 }, lhs_ty, dst_mcv, src_mcv),5294 }, lhs_ty, dst_mcv, src_mcv),
51895295
5190 .sub,5296 .sub,
5191 .subwrap,5297 .subwrap,
5192 => try self.genBinOpMir(switch (lhs_ty.tag()) {5298 => try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {
5193 else => .sub,5299 else => .sub,
5194 .f32 => .subss,5300 .Float => switch (lhs_ty.floatBits(self.target.*)) {
5195 .f64 => .subsd,5301 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
5302 .subss
5303 else
5304 return self.fail("TODO implement genBinOp for {s} {} without sse", .{
5305 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5306 }),
5307 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
5308 .subsd
5309 else
5310 return self.fail("TODO implement genBinOp for {s} {} without sse2", .{
5311 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5312 }),
5313 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5314 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5315 }),
5316 },
5196 }, lhs_ty, dst_mcv, src_mcv),5317 }, lhs_ty, dst_mcv, src_mcv),
51975318
5198 .mul => try self.genBinOpMir(switch (lhs_ty.tag()) {5319 .mul => try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {
5199 .f32 => .mulss,
5200 .f64 => .mulsd,
5201 else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),5320 else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),
5321 .Float => switch (lhs_ty.floatBits(self.target.*)) {
5322 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
5323 .mulss
5324 else
5325 return self.fail("TODO implement genBinOp for {s} {} without sse", .{
5326 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5327 }),
5328 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
5329 .mulsd
5330 else
5331 return self.fail("TODO implement genBinOp for {s} {} without sse2", .{
5332 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5333 }),
5334 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5335 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5336 }),
5337 },
5202 }, lhs_ty, dst_mcv, src_mcv),5338 }, lhs_ty, dst_mcv, src_mcv),
52035339
5204 .div_float,5340 .div_float,
...@@ -5206,12 +5342,27 @@ fn genBinOp(...@@ -5206,12 +5342,27 @@ fn genBinOp(
5206 .div_trunc,5342 .div_trunc,
5207 .div_floor,5343 .div_floor,
5208 => {5344 => {
5209 try self.genBinOpMir(switch (lhs_ty.tag()) {5345 try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {
5210 .f32 => .divss,
5211 .f64 => .divsd,
5212 else => return self.fail("TODO implement genBinOp for {s} {}", .{5346 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5213 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),5347 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5214 }),5348 }),
5349 .Float => switch (lhs_ty.floatBits(self.target.*)) {
5350 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
5351 .divss
5352 else
5353 return self.fail("TODO implement genBinOp for {s} {} without sse", .{
5354 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5355 }),
5356 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
5357 .divsd
5358 else
5359 return self.fail("TODO implement genBinOp for {s} {} without sse2", .{
5360 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5361 }),
5362 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5363 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5364 }),
5365 },
5215 }, lhs_ty, dst_mcv, src_mcv);5366 }, lhs_ty, dst_mcv, src_mcv);
5216 switch (tag) {5367 switch (tag) {
5217 .div_float,5368 .div_float,
...@@ -5222,16 +5373,18 @@ fn genBinOp(...@@ -5222,16 +5373,18 @@ fn genBinOp(
5222 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse4_1)) {5373 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse4_1)) {
5223 const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));5374 const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));
5224 const dst_alias = registerAlias(dst_mcv.register, abi_size);5375 const dst_alias = registerAlias(dst_mcv.register, abi_size);
5225 try self.asmRegisterRegisterImmediate(switch (lhs_ty.tag()) {5376 try self.asmRegisterRegisterImmediate(switch (lhs_ty.floatBits(self.target.*)) {
5226 .f32 => .roundss,5377 32 => .roundss,
5227 .f64 => .roundsd,5378 64 => .roundsd,
5228 else => unreachable,5379 else => unreachable,
5229 }, dst_alias, dst_alias, Immediate.u(switch (tag) {5380 }, dst_alias, dst_alias, Immediate.u(switch (tag) {
5230 .div_trunc => 0b1_0_11,5381 .div_trunc => 0b1_0_11,
5231 .div_floor => 0b1_0_01,5382 .div_floor => 0b1_0_01,
5232 else => unreachable,5383 else => unreachable,
5233 }));5384 }));
5234 } else return self.fail("TODO implement round without sse4_1", .{}),5385 } else return self.fail("TODO implement genBinOp for {s} {} without sse4_1", .{
5386 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5387 }),
5235 else => unreachable,5388 else => unreachable,
5236 }5389 }
5237 },5390 },
...@@ -5453,39 +5606,68 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s...@@ -5453,39 +5606,68 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
5453 )),5606 )),
5454 else => unreachable,5607 else => unreachable,
5455 },5608 },
5456 .register_offset,
5457 .eflags,5609 .eflags,
5610 .register_offset,
5458 .memory,5611 .memory,
5612 .indirect,
5459 .load_direct,5613 .load_direct,
5460 .lea_direct,5614 .lea_direct,
5461 .load_got,5615 .load_got,
5462 .lea_got,5616 .lea_got,
5463 .load_tlv,5617 .load_tlv,
5464 .lea_tlv,5618 .lea_tlv,
5619 .load_frame,
5465 .lea_frame,5620 .lea_frame,
5466 => {5621 => {
5467 assert(abi_size <= 8);5622 blk: {
5623 return self.asmRegisterMemory(
5624 mir_tag,
5625 registerAlias(dst_reg, abi_size),
5626 Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (src_mcv) {
5627 .memory => |addr| .{
5628 .base = .{ .reg = .ds },
5629 .disp = math.cast(i32, addr) orelse break :blk,
5630 },
5631 .indirect => |reg_off| .{
5632 .base = .{ .reg = reg_off.reg },
5633 .disp = reg_off.off,
5634 },
5635 .load_frame => |frame_addr| .{
5636 .base = .{ .frame = frame_addr.index },
5637 .disp = frame_addr.off,
5638 },
5639 else => break :blk,
5640 }),
5641 );
5642 }
5643
5468 const dst_reg_lock = self.register_manager.lockReg(dst_reg);5644 const dst_reg_lock = self.register_manager.lockReg(dst_reg);
5469 defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);5645 defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
54705646
5471 const reg = try self.copyToTmpRegister(ty, src_mcv);5647 switch (src_mcv) {
5472 return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = reg });5648 .eflags,
5473 },5649 .register_offset,
5474 .indirect, .load_frame => try self.asmRegisterMemory(5650 .lea_direct,
5475 mir_tag,5651 .lea_got,
5476 registerAlias(dst_reg, abi_size),5652 .lea_tlv,
5477 Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (src_mcv) {5653 .lea_frame,
5478 .indirect => |reg_off| .{5654 => {
5479 .base = .{ .reg = reg_off.reg },5655 const reg = try self.copyToTmpRegister(ty, src_mcv);
5480 .disp = reg_off.off,5656 return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = reg });
5481 },5657 },
5482 .load_frame => |frame_addr| .{5658 .memory,
5483 .base = .{ .frame = frame_addr.index },5659 .load_direct,
5484 .disp = frame_addr.off,5660 .load_got,
5661 .load_tlv,
5662 => {
5663 const addr_reg = try self.copyToTmpRegister(ty, src_mcv.address());
5664 return self.genBinOpMir(mir_tag, ty, dst_mcv, .{
5665 .indirect = .{ .reg = addr_reg },
5666 });
5485 },5667 },
5486 else => unreachable,5668 else => unreachable,
5487 }),5669 }
5488 ),5670 },
5489 }5671 }
5490 },5672 },
5491 .memory, .indirect, .load_got, .load_direct, .load_tlv, .load_frame => {5673 .memory, .indirect, .load_got, .load_direct, .load_tlv, .load_frame => {
...@@ -6175,10 +6357,25 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {...@@ -6175,10 +6357,25 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
6175 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);6357 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
61766358
6177 const src_mcv = if (flipped) lhs_mcv else rhs_mcv;6359 const src_mcv = if (flipped) lhs_mcv else rhs_mcv;
6178 try self.genBinOpMir(switch (ty.tag()) {6360 try self.genBinOpMir(switch (ty.zigTypeTag()) {
6179 else => .cmp,6361 else => .cmp,
6180 .f32 => .ucomiss,6362 .Float => switch (ty.floatBits(self.target.*)) {
6181 .f64 => .ucomisd,6363 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
6364 .ucomiss
6365 else
6366 return self.fail("TODO implement airCmp for {} without sse", .{
6367 ty.fmt(self.bin_file.options.module.?),
6368 }),
6369 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
6370 .ucomisd
6371 else
6372 return self.fail("TODO implement airCmp for {} without sse2", .{
6373 ty.fmt(self.bin_file.options.module.?),
6374 }),
6375 else => return self.fail("TODO implement airCmp for {}", .{
6376 ty.fmt(self.bin_file.options.module.?),
6377 }),
6378 },
6182 }, ty, dst_mcv, src_mcv);6379 }, ty, dst_mcv, src_mcv);
61836380
6184 const signedness = if (ty.isAbiInt()) ty.intInfo(self.target.*).signedness else .unsigned;6381 const signedness = if (ty.isAbiInt()) ty.intInfo(self.target.*).signedness else .unsigned;
...@@ -7608,7 +7805,8 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {...@@ -7608,7 +7805,8 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {
7608 const dst_rc = try self.regClassForType(dst_ty);7805 const dst_rc = try self.regClassForType(dst_ty);
7609 const src_rc = try self.regClassForType(src_ty);7806 const src_rc = try self.regClassForType(src_ty);
7610 const operand = try self.resolveInst(ty_op.operand);7807 const operand = try self.resolveInst(ty_op.operand);
7611 if (dst_rc.eql(src_rc) and self.reuseOperand(inst, ty_op.operand, 0, operand)) break :result operand;7808 if (dst_rc.supersetOf(src_rc) and self.reuseOperand(inst, ty_op.operand, 0, operand))
7809 break :result operand;
76127810
7613 const operand_lock = switch (operand) {7811 const operand_lock = switch (operand) {
7614 .register => |reg| self.register_manager.lockReg(reg),7812 .register => |reg| self.register_manager.lockReg(reg),
...@@ -7648,9 +7846,59 @@ fn airArrayToSlice(self: *Self, inst: Air.Inst.Index) !void {...@@ -7648,9 +7846,59 @@ fn airArrayToSlice(self: *Self, inst: Air.Inst.Index) !void {
76487846
7649fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {7847fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {
7650 const ty_op = self.air.instructions.items(.data)[inst].ty_op;7848 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
7651 _ = ty_op;7849
7652 return self.fail("TODO implement airIntToFloat for {}", .{self.target.cpu.arch});7850 const src_ty = self.air.typeOf(ty_op.operand);
7653 //return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });7851 const src_bits = @intCast(u32, src_ty.bitSize(self.target.*));
7852 const src_signedness =
7853 if (src_ty.isAbiInt()) src_ty.intInfo(self.target.*).signedness else .unsigned;
7854 const dst_ty = self.air.typeOfIndex(inst);
7855
7856 const src_size = std.math.divCeil(u32, @max(switch (src_signedness) {
7857 .signed => src_bits,
7858 .unsigned => src_bits + 1,
7859 }, 32), 8) catch unreachable;
7860 if (src_size > 8) return self.fail("TODO implement airIntToFloat from {} to {}", .{
7861 src_ty.fmt(self.bin_file.options.module.?),
7862 dst_ty.fmt(self.bin_file.options.module.?),
7863 });
7864
7865 const src_mcv = try self.resolveInst(ty_op.operand);
7866 const src_reg = switch (src_mcv) {
7867 .register => |reg| reg,
7868 else => try self.copyToTmpRegister(src_ty, src_mcv),
7869 };
7870 const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
7871 defer self.register_manager.unlockReg(src_lock);
7872
7873 if (src_bits < src_size * 8) try self.truncateRegister(src_ty, src_reg);
7874
7875 const dst_reg = try self.register_manager.allocReg(inst, try self.regClassForType(dst_ty));
7876 const dst_mcv = MCValue{ .register = dst_reg };
7877 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
7878 defer self.register_manager.unlockReg(dst_lock);
7879
7880 try self.asmRegisterRegister(switch (dst_ty.floatBits(self.target.*)) {
7881 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
7882 .cvtsi2ss
7883 else
7884 return self.fail("TODO implement airIntToFloat from {} to {} without sse", .{
7885 src_ty.fmt(self.bin_file.options.module.?),
7886 dst_ty.fmt(self.bin_file.options.module.?),
7887 }),
7888 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
7889 .cvtsi2sd
7890 else
7891 return self.fail("TODO implement airIntToFloat from {} to {} without sse2", .{
7892 src_ty.fmt(self.bin_file.options.module.?),
7893 dst_ty.fmt(self.bin_file.options.module.?),
7894 }),
7895 else => return self.fail("TODO implement airIntToFloat from {} to {}", .{
7896 src_ty.fmt(self.bin_file.options.module.?),
7897 dst_ty.fmt(self.bin_file.options.module.?),
7898 }),
7899 }, dst_reg.to128(), registerAlias(src_reg, src_size));
7900
7901 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
7654}7902}
76557903
7656fn airFloatToInt(self: *Self, inst: Air.Inst.Index) !void {7904fn airFloatToInt(self: *Self, inst: Air.Inst.Index) !void {
...@@ -8717,6 +8965,7 @@ fn resolveCallingConventionValues(...@@ -8717,6 +8965,7 @@ fn resolveCallingConventionValues(
8717 },8965 },
8718 .C => {8966 .C => {
8719 var param_reg_i: usize = 0;8967 var param_reg_i: usize = 0;
8968 var param_sse_reg_i: usize = 0;
8720 result.stack_align = 16;8969 result.stack_align = 16;
87218970
8722 switch (self.target.os.tag) {8971 switch (self.target.os.tag) {
...@@ -8734,26 +8983,39 @@ fn resolveCallingConventionValues(...@@ -8734,26 +8983,39 @@ fn resolveCallingConventionValues(
8734 // TODO: is this even possible for C calling convention?8983 // TODO: is this even possible for C calling convention?
8735 result.return_value = InstTracking.init(.none);8984 result.return_value = InstTracking.init(.none);
8736 } else {8985 } else {
8737 const ret_reg = abi.getCAbiIntReturnRegs(self.target.*)[0];8986 const classes = switch (self.target.os.tag) {
8738 const ret_ty_size = @intCast(u31, ret_ty.abiSize(self.target.*));8987 .windows => &[1]abi.Class{abi.classifyWindows(ret_ty, self.target.*)},
8739 if (ret_ty_size <= 8) {8988 else => mem.sliceTo(&abi.classifySystemV(ret_ty, self.target.*, .ret), .none),
8740 const aliased_reg = registerAlias(ret_reg, ret_ty_size);8989 };
8741 result.return_value = .{ .short = .{ .register = aliased_reg }, .long = .none };8990 if (classes.len > 1) {
8742 } else {8991 return self.fail("TODO handle multiple classes per type", .{});
8743 const ret_indirect_reg = abi.getCAbiIntParamRegs(self.target.*)[param_reg_i];
8744 param_reg_i += 1;
8745 result.return_value = .{
8746 .short = .{ .indirect = .{ .reg = ret_reg } },
8747 .long = .{ .indirect = .{ .reg = ret_indirect_reg } },
8748 };
8749 }8992 }
8993 const ret_reg = abi.getCAbiIntReturnRegs(self.target.*)[0];
8994 result.return_value = switch (classes[0]) {
8995 .integer => InstTracking.init(.{ .register = registerAlias(
8996 ret_reg,
8997 @intCast(u32, ret_ty.abiSize(self.target.*)),
8998 ) }),
8999 .float, .sse => InstTracking.init(.{ .register = .xmm0 }),
9000 .memory => ret: {
9001 const ret_indirect_reg = abi.getCAbiIntParamRegs(self.target.*)[param_reg_i];
9002 param_reg_i += 1;
9003 break :ret .{
9004 .short = .{ .indirect = .{ .reg = ret_reg } },
9005 .long = .{ .indirect = .{ .reg = ret_indirect_reg } },
9006 };
9007 },
9008 else => |class| return self.fail("TODO handle calling convention class {s}", .{
9009 @tagName(class),
9010 }),
9011 };
8750 }9012 }
87519013
8752 // Input params9014 // Input params
8753 for (param_types, result.args) |ty, *arg| {9015 for (param_types, result.args) |ty, *arg| {
8754 assert(ty.hasRuntimeBitsIgnoreComptime());9016 assert(ty.hasRuntimeBitsIgnoreComptime());
87559017
8756 const classes: []const abi.Class = switch (self.target.os.tag) {9018 const classes = switch (self.target.os.tag) {
8757 .windows => &[1]abi.Class{abi.classifyWindows(ty, self.target.*)},9019 .windows => &[1]abi.Class{abi.classifyWindows(ty, self.target.*)},
8758 else => mem.sliceTo(&abi.classifySystemV(ty, self.target.*, .arg), .none),9020 else => mem.sliceTo(&abi.classifySystemV(ty, self.target.*, .arg), .none),
8759 };9021 };
...@@ -8761,13 +9023,29 @@ fn resolveCallingConventionValues(...@@ -8761,13 +9023,29 @@ fn resolveCallingConventionValues(
8761 return self.fail("TODO handle multiple classes per type", .{});9023 return self.fail("TODO handle multiple classes per type", .{});
8762 }9024 }
8763 switch (classes[0]) {9025 switch (classes[0]) {
8764 .integer => blk: {9026 .integer => if (param_reg_i < abi.getCAbiIntParamRegs(self.target.*).len) {
8765 if (param_reg_i >= abi.getCAbiIntParamRegs(self.target.*).len) break :blk;9027 arg.* = .{ .register = abi.getCAbiIntParamRegs(self.target.*)[param_reg_i] };
8766 const param_reg = abi.getCAbiIntParamRegs(self.target.*)[param_reg_i];
8767 param_reg_i += 1;9028 param_reg_i += 1;
8768 arg.* = .{ .register = param_reg };
8769 continue;9029 continue;
8770 },9030 },
9031 .float, .sse => switch (self.target.os.tag) {
9032 .windows => if (param_reg_i < 4) {
9033 arg.* = .{ .register = @intToEnum(
9034 Register,
9035 @enumToInt(Register.xmm0) + param_reg_i,
9036 ) };
9037 param_reg_i += 1;
9038 continue;
9039 },
9040 else => if (param_sse_reg_i < 8) {
9041 arg.* = .{ .register = @intToEnum(
9042 Register,
9043 @enumToInt(Register.xmm0) + param_sse_reg_i,
9044 ) };
9045 param_sse_reg_i += 1;
9046 continue;
9047 },
9048 },
8771 .memory => {}, // fallthrough9049 .memory => {}, // fallthrough
8772 else => |class| return self.fail("TODO handle calling convention class {s}", .{9050 else => |class| return self.fail("TODO handle calling convention class {s}", .{
8773 @tagName(class),9051 @tagName(class),
src/arch/x86_64/Encoding.zig+16-11
...@@ -58,7 +58,7 @@ pub fn findByMnemonic(...@@ -58,7 +58,7 @@ pub fn findByMnemonic(
58 next: for (mnemonic_to_encodings_map[@enumToInt(mnemonic)]) |data| {58 next: for (mnemonic_to_encodings_map[@enumToInt(mnemonic)]) |data| {
59 switch (data.mode) {59 switch (data.mode) {
60 .rex => if (!rex_required) continue,60 .rex => if (!rex_required) continue,
61 .long, .sse2_long => {},61 .long, .sse_long, .sse2_long => {},
62 else => if (rex_required) continue,62 else => if (rex_required) continue,
63 }63 }
64 for (input_ops, data.ops) |input_op, data_op|64 for (input_ops, data.ops) |input_op, data_op|
...@@ -90,7 +90,7 @@ pub fn findByOpcode(opc: []const u8, prefixes: struct {...@@ -90,7 +90,7 @@ pub fn findByOpcode(opc: []const u8, prefixes: struct {
90 if (prefixes.rex.w) {90 if (prefixes.rex.w) {
91 switch (data.mode) {91 switch (data.mode) {
92 .short, .fpu, .sse, .sse2, .sse4_1, .none => continue,92 .short, .fpu, .sse, .sse2, .sse4_1, .none => continue,
93 .long, .sse2_long, .rex => {},93 .long, .sse_long, .sse2_long, .rex => {},
94 }94 }
95 } else if (prefixes.rex.present and !prefixes.rex.isSet()) {95 } else if (prefixes.rex.present and !prefixes.rex.isSet()) {
96 switch (data.mode) {96 switch (data.mode) {
...@@ -138,7 +138,7 @@ pub fn modRmExt(encoding: Encoding) u3 {...@@ -138,7 +138,7 @@ pub fn modRmExt(encoding: Encoding) u3 {
138pub fn operandBitSize(encoding: Encoding) u64 {138pub fn operandBitSize(encoding: Encoding) u64 {
139 switch (encoding.data.mode) {139 switch (encoding.data.mode) {
140 .short => return 16,140 .short => return 16,
141 .long, .sse2_long => return 64,141 .long, .sse_long, .sse2_long => return 64,
142 else => {},142 else => {},
143 }143 }
144 const bit_size: u64 = switch (encoding.data.op_en) {144 const bit_size: u64 = switch (encoding.data.op_en) {
...@@ -163,7 +163,7 @@ pub fn format(...@@ -163,7 +163,7 @@ pub fn format(
163 _ = options;163 _ = options;
164 _ = fmt;164 _ = fmt;
165 switch (encoding.data.mode) {165 switch (encoding.data.mode) {
166 .long, .sse2_long => try writer.writeAll("REX.W + "),166 .long, .sse_long, .sse2_long => try writer.writeAll("REX.W + "),
167 else => {},167 else => {},
168 }168 }
169169
...@@ -269,21 +269,25 @@ pub const Mnemonic = enum {...@@ -269,21 +269,25 @@ pub const Mnemonic = enum {
269 // SSE269 // SSE
270 addss,270 addss,
271 cmpss,271 cmpss,
272 cvtsi2ss,
272 divss,273 divss,
273 maxss, minss,274 maxss, minss,
274 movss,275 movss,
275 mulss,276 mulss,
276 subss,277 subss,
277 ucomiss,278 ucomiss,
279 xorps,
278 // SSE2280 // SSE2
279 addsd,281 addsd,
280 //cmpsd,282 //cmpsd,
283 cvtsd2ss, cvtsi2sd, cvtss2sd,
281 divsd,284 divsd,
282 maxsd, minsd,285 maxsd, minsd,
283 movq, //movd, movsd,286 movq, //movd, movsd,
284 mulsd,287 mulsd,
285 subsd,288 subsd,
286 ucomisd,289 ucomisd,
290 xorpd,
287 // SSE4.1291 // SSE4.1
288 roundss,292 roundss,
289 roundsd,293 roundsd,
...@@ -318,7 +322,7 @@ pub const Op = enum {...@@ -318,7 +322,7 @@ pub const Op = enum {
318 m,322 m,
319 moffs,323 moffs,
320 sreg,324 sreg,
321 xmm, xmm_m32, xmm_m64,325 xmm, xmm_m32, xmm_m64, xmm_m128,
322 // zig fmt: on326 // zig fmt: on
323327
324 pub fn fromOperand(operand: Instruction.Operand) Op {328 pub fn fromOperand(operand: Instruction.Operand) Op {
...@@ -400,7 +404,7 @@ pub const Op = enum {...@@ -400,7 +404,7 @@ pub const Op = enum {
400 .imm32, .imm32s, .eax, .r32, .m32, .rm32, .rel32, .xmm_m32 => 32,404 .imm32, .imm32s, .eax, .r32, .m32, .rm32, .rel32, .xmm_m32 => 32,
401 .imm64, .rax, .r64, .m64, .rm64, .xmm_m64 => 64,405 .imm64, .rax, .r64, .m64, .rm64, .xmm_m64 => 64,
402 .m80 => 80,406 .m80 => 80,
403 .m128, .xmm => 128,407 .m128, .xmm, .xmm_m128 => 128,
404 };408 };
405 }409 }
406410
...@@ -423,8 +427,8 @@ pub const Op = enum {...@@ -423,8 +427,8 @@ pub const Op = enum {
423 .al, .ax, .eax, .rax,427 .al, .ax, .eax, .rax,
424 .r8, .r16, .r32, .r64,428 .r8, .r16, .r32, .r64,
425 .rm8, .rm16, .rm32, .rm64,429 .rm8, .rm16, .rm32, .rm64,
426 .xmm, .xmm_m32, .xmm_m64,430 .xmm, .xmm_m32, .xmm_m64, .xmm_m128,
427 => true,431 => true,
428 else => false,432 else => false,
429 };433 };
430 // zig fmt: on434 // zig fmt: on
...@@ -449,7 +453,7 @@ pub const Op = enum {...@@ -449,7 +453,7 @@ pub const Op = enum {
449 .rm8, .rm16, .rm32, .rm64,453 .rm8, .rm16, .rm32, .rm64,
450 .m8, .m16, .m32, .m64, .m80, .m128,454 .m8, .m16, .m32, .m64, .m80, .m128,
451 .m,455 .m,
452 .xmm_m32, .xmm_m64,456 .xmm_m32, .xmm_m64, .xmm_m128,
453 => true,457 => true,
454 else => false,458 else => false,
455 };459 };
...@@ -470,13 +474,13 @@ pub const Op = enum {...@@ -470,13 +474,13 @@ pub const Op = enum {
470 .r8, .r16, .r32, .r64 => .general_purpose,474 .r8, .r16, .r32, .r64 => .general_purpose,
471 .rm8, .rm16, .rm32, .rm64 => .general_purpose,475 .rm8, .rm16, .rm32, .rm64 => .general_purpose,
472 .sreg => .segment,476 .sreg => .segment,
473 .xmm, .xmm_m32, .xmm_m64 => .floating_point,477 .xmm, .xmm_m32, .xmm_m64, .xmm_m128 => .floating_point,
474 };478 };
475 }479 }
476480
477 pub fn isFloatingPointRegister(op: Op) bool {481 pub fn isFloatingPointRegister(op: Op) bool {
478 return switch (op) {482 return switch (op) {
479 .xmm, .xmm_m32, .xmm_m64 => true,483 .xmm, .xmm_m32, .xmm_m64, .xmm_m128 => true,
480 else => false,484 else => false,
481 };485 };
482 }486 }
...@@ -535,6 +539,7 @@ pub const Mode = enum {...@@ -535,6 +539,7 @@ pub const Mode = enum {
535 rex,539 rex,
536 long,540 long,
537 sse,541 sse,
542 sse_long,
538 sse2,543 sse2,
539 sse2_long,544 sse2_long,
540 sse4_1,545 sse4_1,
src/arch/x86_64/Lower.zig+6
...@@ -95,6 +95,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {...@@ -95,6 +95,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
9595
96 .addss,96 .addss,
97 .cmpss,97 .cmpss,
98 .cvtsi2ss,
98 .divss,99 .divss,
99 .maxss,100 .maxss,
100 .minss,101 .minss,
...@@ -103,8 +104,12 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {...@@ -103,8 +104,12 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
103 .roundss,104 .roundss,
104 .subss,105 .subss,
105 .ucomiss,106 .ucomiss,
107 .xorps,
106 .addsd,108 .addsd,
107 .cmpsd,109 .cmpsd,
110 .cvtsd2ss,
111 .cvtsi2sd,
112 .cvtss2sd,
108 .divsd,113 .divsd,
109 .maxsd,114 .maxsd,
110 .minsd,115 .minsd,
...@@ -113,6 +118,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {...@@ -113,6 +118,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
113 .roundsd,118 .roundsd,
114 .subsd,119 .subsd,
115 .ucomisd,120 .ucomisd,
121 .xorpd,
116 => try lower.mirGeneric(inst),122 => try lower.mirGeneric(inst),
117123
118 .cmps,124 .cmps,
src/arch/x86_64/Mir.zig+12
...@@ -170,6 +170,8 @@ pub const Inst = struct {...@@ -170,6 +170,8 @@ pub const Inst = struct {
170 addss,170 addss,
171 /// Compare scalar single-precision floating-point values171 /// Compare scalar single-precision floating-point values
172 cmpss,172 cmpss,
173 /// Convert doubleword integer to scalar single-precision floating-point value
174 cvtsi2ss,
173 /// Divide scalar single-precision floating-point values175 /// Divide scalar single-precision floating-point values
174 divss,176 divss,
175 /// Return maximum single-precision floating-point value177 /// Return maximum single-precision floating-point value
...@@ -186,10 +188,18 @@ pub const Inst = struct {...@@ -186,10 +188,18 @@ pub const Inst = struct {
186 subss,188 subss,
187 /// Unordered compare scalar single-precision floating-point values189 /// Unordered compare scalar single-precision floating-point values
188 ucomiss,190 ucomiss,
191 /// Bitwise logical xor of packed single precision floating-point values
192 xorps,
189 /// Add double precision floating point values193 /// Add double precision floating point values
190 addsd,194 addsd,
191 /// Compare scalar double-precision floating-point values195 /// Compare scalar double-precision floating-point values
192 cmpsd,196 cmpsd,
197 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
198 cvtsd2ss,
199 /// Convert doubleword integer to scalar double-precision floating-point value
200 cvtsi2sd,
201 /// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
202 cvtss2sd,
193 /// Divide scalar double-precision floating-point values203 /// Divide scalar double-precision floating-point values
194 divsd,204 divsd,
195 /// Return maximum double-precision floating-point value205 /// Return maximum double-precision floating-point value
...@@ -206,6 +216,8 @@ pub const Inst = struct {...@@ -206,6 +216,8 @@ pub const Inst = struct {
206 subsd,216 subsd,
207 /// Unordered compare scalar double-precision floating-point values217 /// Unordered compare scalar double-precision floating-point values
208 ucomisd,218 ucomisd,
219 /// Bitwise logical xor of packed double precision floating-point values
220 xorpd,
209221
210 /// Compare string operands222 /// Compare string operands
211 cmps,223 cmps,
src/arch/x86_64/encoder.zig+1-1
...@@ -323,7 +323,7 @@ pub const Instruction = struct {...@@ -323,7 +323,7 @@ pub const Instruction = struct {
323 var rex = Rex{};323 var rex = Rex{};
324 rex.present = inst.encoding.data.mode == .rex;324 rex.present = inst.encoding.data.mode == .rex;
325 switch (inst.encoding.data.mode) {325 switch (inst.encoding.data.mode) {
326 .long, .sse2_long => rex.w = true,326 .long, .sse_long, .sse2_long => rex.w = true,
327 else => {},327 else => {},
328 }328 }
329329
src/arch/x86_64/encodings.zig+14
...@@ -834,6 +834,9 @@ pub const table = [_]Entry{...@@ -834,6 +834,9 @@ pub const table = [_]Entry{
834834
835 .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse },835 .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse },
836836
837 .{ .cvtsi2ss, .rm, &.{ .xmm, .rm32 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse },
838 .{ .cvtsi2ss, .rm, &.{ .xmm, .rm64 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse_long },
839
837 .{ .divss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5e }, 0, .sse },840 .{ .divss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5e }, 0, .sse },
838841
839 .{ .maxss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5f }, 0, .sse },842 .{ .maxss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5f }, 0, .sse },
...@@ -849,11 +852,20 @@ pub const table = [_]Entry{...@@ -849,11 +852,20 @@ pub const table = [_]Entry{
849852
850 .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse },853 .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse },
851854
855 .{ .xorps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .sse },
856
852 // SSE2857 // SSE2
853 .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 },858 .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 },
854859
855 .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 },860 .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 },
856861
862 .{ .cvtsd2ss, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .sse2 },
863
864 .{ .cvtsi2sd, .rm, &.{ .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .sse2 },
865 .{ .cvtsi2sd, .rm, &.{ .xmm, .rm64 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .sse2_long },
866
867 .{ .cvtss2sd, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5a }, 0, .sse2 },
868
857 .{ .divsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5e }, 0, .sse2 },869 .{ .divsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5e }, 0, .sse2 },
858870
859 .{ .maxsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5f }, 0, .sse2 },871 .{ .maxsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5f }, 0, .sse2 },
...@@ -878,6 +890,8 @@ pub const table = [_]Entry{...@@ -878,6 +890,8 @@ pub const table = [_]Entry{
878890
879 .{ .ucomisd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x2e }, 0, .sse2 },891 .{ .ucomisd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x2e }, 0, .sse2 },
880892
893 .{ .xorpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .sse2 },
894
881 // SSE4.1895 // SSE4.1
882 .{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .sse4_1 },896 .{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .sse4_1 },
883 .{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .sse4_1 },897 .{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .sse4_1 },
src/codegen.zig+79-24
...@@ -291,6 +291,20 @@ pub fn generateSymbol(...@@ -291,6 +291,20 @@ pub fn generateSymbol(
291 },291 },
292 },292 },
293 .Pointer => switch (typed_value.val.tag()) {293 .Pointer => switch (typed_value.val.tag()) {
294 .null_value => {
295 switch (target.cpu.arch.ptrBitWidth()) {
296 32 => {
297 mem.writeInt(u32, try code.addManyAsArray(4), 0, endian);
298 if (typed_value.ty.isSlice()) try code.appendNTimes(0xaa, 4);
299 },
300 64 => {
301 mem.writeInt(u64, try code.addManyAsArray(8), 0, endian);
302 if (typed_value.ty.isSlice()) try code.appendNTimes(0xaa, 8);
303 },
304 else => unreachable,
305 }
306 return Result.ok;
307 },
294 .zero, .one, .int_u64, .int_big_positive => {308 .zero, .one, .int_u64, .int_big_positive => {
295 switch (target.cpu.arch.ptrBitWidth()) {309 switch (target.cpu.arch.ptrBitWidth()) {
296 32 => {310 32 => {
...@@ -397,30 +411,15 @@ pub fn generateSymbol(...@@ -397,30 +411,15 @@ pub fn generateSymbol(
397 },411 },
398 }412 }
399 },413 },
400 .elem_ptr => {414 .elem_ptr => return lowerParentPtr(
401 const elem_ptr = typed_value.val.castTag(.elem_ptr).?.data;415 bin_file,
402 const elem_size = typed_value.ty.childType().abiSize(target);416 src_loc,
403 const addend = @intCast(u32, elem_ptr.index * elem_size);417 typed_value,
404 const array_ptr = elem_ptr.array_ptr;418 typed_value.val,
405419 code,
406 switch (array_ptr.tag()) {420 debug_output,
407 .decl_ref => {421 reloc_info,
408 const decl_index = array_ptr.castTag(.decl_ref).?.data;422 ),
409 return lowerDeclRef(bin_file, src_loc, typed_value, decl_index, code, debug_output, .{
410 .parent_atom_index = reloc_info.parent_atom_index,
411 .addend = (reloc_info.addend orelse 0) + addend,
412 });
413 },
414 else => return Result{
415 .fail = try ErrorMsg.create(
416 bin_file.allocator,
417 src_loc,
418 "TODO implement generateSymbol for pointer type value: '{s}'",
419 .{@tagName(typed_value.val.tag())},
420 ),
421 },
422 }
423 },
424 else => return Result{423 else => return Result{
425 .fail = try ErrorMsg.create(424 .fail = try ErrorMsg.create(
426 bin_file.allocator,425 bin_file.allocator,
...@@ -838,9 +837,62 @@ pub fn generateSymbol(...@@ -838,9 +837,62 @@ pub fn generateSymbol(
838 }837 }
839}838}
840839
840fn lowerParentPtr(
841 bin_file: *link.File,
842 src_loc: Module.SrcLoc,
843 typed_value: TypedValue,
844 parent_ptr: Value,
845 code: *std.ArrayList(u8),
846 debug_output: DebugInfoOutput,
847 reloc_info: RelocInfo,
848) CodeGenError!Result {
849 const target = bin_file.options.target;
850
851 switch (parent_ptr.tag()) {
852 .elem_ptr => {
853 const elem_ptr = parent_ptr.castTag(.elem_ptr).?.data;
854 return lowerParentPtr(
855 bin_file,
856 src_loc,
857 typed_value,
858 elem_ptr.array_ptr,
859 code,
860 debug_output,
861 reloc_info.offset(@intCast(u32, elem_ptr.index * elem_ptr.elem_ty.abiSize(target))),
862 );
863 },
864 .decl_ref => {
865 const decl_index = parent_ptr.castTag(.decl_ref).?.data;
866 return lowerDeclRef(
867 bin_file,
868 src_loc,
869 typed_value,
870 decl_index,
871 code,
872 debug_output,
873 reloc_info,
874 );
875 },
876 else => |t| {
877 return Result{
878 .fail = try ErrorMsg.create(
879 bin_file.allocator,
880 src_loc,
881 "TODO implement lowerParentPtr for type '{s}'",
882 .{@tagName(t)},
883 ),
884 };
885 },
886 }
887}
888
841const RelocInfo = struct {889const RelocInfo = struct {
842 parent_atom_index: u32,890 parent_atom_index: u32,
843 addend: ?u32 = null,891 addend: ?u32 = null,
892
893 fn offset(ri: RelocInfo, addend: u32) RelocInfo {
894 return .{ .parent_atom_index = ri.parent_atom_index, .addend = (ri.addend orelse 0) + addend };
895 }
844};896};
845897
846fn lowerDeclRef(898fn lowerDeclRef(
...@@ -1095,6 +1147,9 @@ pub fn genTypedValue(...@@ -1095,6 +1147,9 @@ pub fn genTypedValue(
1095 .Slice => {},1147 .Slice => {},
1096 else => {1148 else => {
1097 switch (typed_value.val.tag()) {1149 switch (typed_value.val.tag()) {
1150 .null_value => {
1151 return GenResult.mcv(.{ .immediate = 0 });
1152 },
1098 .int_u64 => {1153 .int_u64 => {
1099 return GenResult.mcv(.{ .immediate = typed_value.val.toUnsignedInt(target) });1154 return GenResult.mcv(.{ .immediate = typed_value.val.toUnsignedInt(target) });
1100 },1155 },