authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-10-17 01:50:36+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-10-26 21:59:59+02:00
log51dc4b05494e5b6ddf32ce38cca70b1af54b091d
treeb62388c641bc9e0c1296fc02c60688c9a77d47a1
parent8062bdba9aa2dd5c4f63106a952df5d75c4f4ccb
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Use ppc64 as the generic CPU model for powerpc64le.

ppc64le remains the baseline CPU model. Note that there's nothing about little endian, 64-bit PowerPC that requires the features in the ppc64le model; the reason it exists is that 64-bit PowerPC wasn't really used in little endian mode prior to those features being commonplace. That makes the ppc64le model a good baseline model, but not the right choice for a generic model.

1 files changed, 3 insertions(+), 4 deletions(-)

lib/std/Target.zig+3-4
...@@ -1811,10 +1811,8 @@ pub const Cpu = struct {...@@ -1811,10 +1811,8 @@ pub const Cpu = struct {
1811 .mips, .mipsel => &mips.cpu.mips32,1811 .mips, .mipsel => &mips.cpu.mips32,
1812 .mips64, .mips64el => &mips.cpu.mips64,1812 .mips64, .mips64el => &mips.cpu.mips64,
1813 .msp430 => &msp430.cpu.generic,1813 .msp430 => &msp430.cpu.generic,
1814 .powerpc => &powerpc.cpu.ppc,1814 .powerpc, .powerpcle => &powerpc.cpu.ppc,
1815 .powerpcle => &powerpc.cpu.ppc,1815 .powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
1816 .powerpc64 => &powerpc.cpu.ppc64,
1817 .powerpc64le => &powerpc.cpu.ppc64le,
1818 .propeller1 => &propeller.cpu.generic,1816 .propeller1 => &propeller.cpu.generic,
1819 .propeller2 => &propeller.cpu.generic,1817 .propeller2 => &propeller.cpu.generic,
1820 .amdgcn => &amdgpu.cpu.generic,1818 .amdgcn => &amdgpu.cpu.generic,
...@@ -1861,6 +1859,7 @@ pub const Cpu = struct {...@@ -1861,6 +1859,7 @@ pub const Cpu = struct {
1861 .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model.1859 .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model.
1862 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.1860 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
1863 .loongarch64 => &loongarch.cpu.loongarch64,1861 .loongarch64 => &loongarch.cpu.loongarch64,
1862 .powerpc64le => &powerpc.cpu.ppc64le,
1864 .riscv32 => &riscv.cpu.baseline_rv32,1863 .riscv32 => &riscv.cpu.baseline_rv32,
1865 .riscv64 => &riscv.cpu.baseline_rv64,1864 .riscv64 => &riscv.cpu.baseline_rv64,
1866 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,1865 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,