authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-05-02 02:07:28-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-06-13 02:19:40-07:00
log55b28c7e4438b3b8404a0fd703aad45db9dfe2ff
treecda0f8217e49b044c41fa587e56a640d4de5668c
parentc457f35da565e589071db9e55d0866f35cd095dc
signaturelock-open Commit is signed but in an unrecognized format.

riscv: PRO member function calls

this is enough progress for us to be able to call `stdout.write`!

2 files changed, 291 insertions(+), 79 deletions(-)

src/arch/riscv64/CodeGen.zig+290-73
......@@ -932,6 +932,25 @@ fn gen(self: *Self) !void {
932932 const backpatch_fp_add = try self.addPseudo(.pseudo_dead);
933933 const backpatch_spill_callee_preserved_regs = try self.addPseudo(.pseudo_dead);
934934
935 switch (self.ret_mcv.long) {
936 .none, .unreach => {},
937 .indirect => {
938 // The address where to store the return value for the caller is in a
939 // register which the callee is free to clobber. Therefore, we purposely
940 // spill it to stack immediately.
941 const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(Type.usize, mod));
942 try self.genSetMem(
943 .{ .frame = frame_index },
944 0,
945 Type.usize,
946 self.ret_mcv.long.address().offset(-self.ret_mcv.short.indirect.off),
947 );
948 self.ret_mcv.long = .{ .load_frame = .{ .index = frame_index } };
949 tracking_log.debug("spill {} to {}", .{ self.ret_mcv.long, frame_index });
950 },
951 else => unreachable,
952 }
953
935954 try self.genBody(self.air.getMainBody());
936955
937956 for (self.exitlude_jump_relocs.items) |jmp_reloc| {
......@@ -1306,12 +1325,13 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
13061325 var it = self.register_manager.free_registers.iterator(.{ .kind = .unset });
13071326 while (it.next()) |index| {
13081327 const tracked_inst = self.register_manager.registers[index];
1328 tracking_log.debug("tracked inst: {}", .{tracked_inst});
13091329 const tracking = self.getResolvedInstValue(tracked_inst);
13101330 for (tracking.getRegs()) |reg| {
13111331 if (RegisterManager.indexOfRegIntoTracked(reg).? == index) break;
1312 } else return self.fail(
1313 \\%{} takes up these regs: {any}, however those regs don't use it
1314 , .{ index, tracking.getRegs() });
1332 } else return std.debug.panic(
1333 \\%{} takes up these regs: {any}, however these regs {any}, don't use it
1334 , .{ tracked_inst, tracking.getRegs(), RegisterManager.regAtTrackedIndex(@intCast(index)) });
13151335 }
13161336 }
13171337 }
......@@ -1540,7 +1560,7 @@ fn symbolIndex(self: *Self) !u32 {
15401560 const atom_index = try elf_file.zigObjectPtr().?.getOrCreateMetadataForDecl(elf_file, decl_index);
15411561 break :blk atom_index;
15421562 },
1543 else => return self.fail("TODO genSetReg load_symbol for {s}", .{@tagName(self.bin_file.tag)}),
1563 else => return self.fail("TODO symbolIndex {s}", .{@tagName(self.bin_file.tag)}),
15441564 };
15451565}
15461566
......@@ -1961,7 +1981,7 @@ fn binOp(
19611981 switch (lhs_ty.zigTypeTag(zcu)) {
19621982 .Float => return self.fail("TODO binary operations on floats", .{}),
19631983 .Vector => return self.fail("TODO binary operations on vectors", .{}),
1964 .Int, .Enum => {
1984 .Int, .Enum, .ErrorSet => {
19651985 assert(lhs_ty.eql(rhs_ty, zcu));
19661986 const int_info = lhs_ty.intInfo(zcu);
19671987 if (int_info.bits <= 64) {
......@@ -2304,8 +2324,127 @@ fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
23042324}
23052325
23062326fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
2307 _ = inst;
2308 return self.fail("TODO implement airSubWithOverflow for {}", .{self.target.cpu.arch});
2327 const zcu = self.bin_file.comp.module.?;
2328 const ty_pl = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_pl;
2329 const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
2330
2331 const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else result: {
2332 const lhs = try self.resolveInst(extra.lhs);
2333 const rhs = try self.resolveInst(extra.rhs);
2334 const lhs_ty = self.typeOf(extra.lhs);
2335 const rhs_ty = self.typeOf(extra.rhs);
2336
2337 const int_info = lhs_ty.intInfo(zcu);
2338
2339 if (!math.isPowerOfTwo(int_info.bits) or !(int_info.bits >= 8)) {
2340 return self.fail("TODO: airSubWithOverflow non-power of 2 and less than 8 bits", .{});
2341 }
2342
2343 const tuple_ty = self.typeOfIndex(inst);
2344 const result_mcv = try self.allocRegOrMem(inst, false);
2345 const offset = result_mcv.load_frame;
2346
2347 const lhs_reg, const lhs_lock = blk: {
2348 if (lhs == .register) break :blk .{ lhs.register, null };
2349
2350 const lhs_reg, const lhs_lock = try self.allocReg();
2351 try self.genSetReg(lhs_ty, lhs_reg, lhs);
2352 break :blk .{ lhs_reg, lhs_lock };
2353 };
2354 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
2355
2356 const rhs_reg, const rhs_lock = blk: {
2357 if (rhs == .register) break :blk .{ rhs.register, null };
2358
2359 const rhs_reg, const rhs_lock = try self.allocReg();
2360 try self.genSetReg(rhs_ty, rhs_reg, rhs);
2361 break :blk .{ rhs_reg, rhs_lock };
2362 };
2363 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
2364
2365 const dest_reg, const dest_lock = try self.allocReg();
2366 defer self.register_manager.unlockReg(dest_lock);
2367
2368 switch (int_info.signedness) {
2369 .unsigned => return self.fail("TODO: airSubWithOverflow unsigned", .{}),
2370 .signed => {
2371 switch (int_info.bits) {
2372 64 => {
2373 // result
2374 _ = try self.addInst(.{
2375 .tag = .sub,
2376 .ops = .rrr,
2377 .data = .{ .r_type = .{
2378 .rd = dest_reg,
2379 .rs1 = lhs_reg,
2380 .rs2 = rhs_reg,
2381 } },
2382 });
2383
2384 try self.genSetMem(
2385 .{ .frame = offset.index },
2386 offset.off + @as(i32, @intCast(tuple_ty.structFieldOffset(0, zcu))),
2387 lhs_ty,
2388 .{ .register = dest_reg },
2389 );
2390
2391 // overflow check
2392 const overflow_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = 0 });
2393
2394 _ = try self.addInst(.{
2395 .tag = .slt,
2396 .ops = .rrr,
2397 .data = .{ .r_type = .{
2398 .rd = overflow_reg,
2399 .rs1 = overflow_reg,
2400 .rs2 = rhs_reg,
2401 } },
2402 });
2403
2404 _ = try self.addInst(.{
2405 .tag = .slt,
2406 .ops = .rrr,
2407 .data = .{ .r_type = .{
2408 .rd = rhs_reg,
2409 .rs1 = rhs_reg,
2410 .rs2 = lhs_reg,
2411 } },
2412 });
2413
2414 _ = try self.addInst(.{
2415 .tag = .xor,
2416 .ops = .rrr,
2417 .data = .{ .r_type = .{
2418 .rd = lhs_reg,
2419 .rs1 = overflow_reg,
2420 .rs2 = rhs_reg,
2421 } },
2422 });
2423
2424 const overflow_mcv = try self.binOp(
2425 .cmp_neq,
2426 .{ .register = overflow_reg },
2427 Type.usize,
2428 .{ .register = rhs_reg },
2429 Type.usize,
2430 );
2431
2432 try self.genSetMem(
2433 .{ .frame = offset.index },
2434 offset.off + @as(i32, @intCast(tuple_ty.structFieldOffset(1, zcu))),
2435 Type.u1,
2436 overflow_mcv,
2437 );
2438
2439 break :result result_mcv;
2440 },
2441 else => |int_bits| return self.fail("TODO: airSubWithOverflow signed {}", .{int_bits}),
2442 }
2443 },
2444 }
2445 };
2446
2447 return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
23092448}
23102449
23112450fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
......@@ -2644,8 +2783,25 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void {
26442783
26452784/// T to E!T
26462785fn airWrapErrUnionPayload(self: *Self, inst: Air.Inst.Index) !void {
2786 const zcu = self.bin_file.comp.module.?;
26472787 const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
2648 const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else return self.fail("TODO implement wrap errunion payload for {}", .{self.target.cpu.arch});
2788
2789 const eu_ty = ty_op.ty.toType();
2790 const pl_ty = eu_ty.errorUnionPayload(zcu);
2791 const err_ty = eu_ty.errorUnionSet(zcu);
2792 const operand = try self.resolveInst(ty_op.operand);
2793
2794 const result: MCValue = result: {
2795 if (!pl_ty.hasRuntimeBitsIgnoreComptime(zcu)) break :result .{ .immediate = 0 };
2796
2797 const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, zcu));
2798 const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, zcu));
2799 const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, zcu));
2800 try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, operand);
2801 try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, .{ .immediate = 0 });
2802 break :result .{ .load_frame = .{ .index = frame_index } };
2803 };
2804
26492805 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
26502806}
26512807
......@@ -3361,8 +3517,6 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
33613517 .rs1 = dst_reg,
33623518 } },
33633519 });
3364
3365 return self.fail("TODO: airStructFieldVal register with field_off > 0", .{});
33663520 }
33673521
33683522 break :result if (field_off == 0) dst_mcv else try self.copyToNewRegister(inst, dst_mcv);
......@@ -3444,7 +3598,6 @@ fn genArgDbgInfo(self: Self, inst: Air.Inst.Index, mcv: MCValue) !void {
34443598}
34453599
34463600fn airArg(self: *Self, inst: Air.Inst.Index) !void {
3447 const zcu = self.bin_file.comp.module.?;
34483601 var arg_index = self.arg_index;
34493602
34503603 // we skip over args that have no bits
......@@ -3453,31 +3606,10 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
34533606
34543607 const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else result: {
34553608 const src_mcv = self.args[arg_index];
3456
34573609 const arg_ty = self.typeOfIndex(inst);
34583610
3459 const dst_mcv = switch (src_mcv) {
3460 .register => dst: {
3461 const frame = try self.allocFrameIndex(FrameAlloc.init(.{
3462 .size = Type.usize.abiSize(zcu),
3463 .alignment = Type.usize.abiAlignment(zcu),
3464 }));
3465 const dst_mcv: MCValue = .{ .load_frame = .{ .index = frame } };
3466 try self.genCopy(Type.usize, dst_mcv, src_mcv);
3467 break :dst dst_mcv;
3468 },
3469 .register_pair => dst: {
3470 const frame = try self.allocFrameIndex(FrameAlloc.init(.{
3471 .size = Type.usize.abiSize(zcu) * 2,
3472 .alignment = Type.usize.abiAlignment(zcu),
3473 }));
3474 const dst_mcv: MCValue = .{ .load_frame = .{ .index = frame } };
3475 try self.genCopy(arg_ty, dst_mcv, src_mcv);
3476 break :dst dst_mcv;
3477 },
3478 .load_frame => src_mcv,
3479 else => return self.fail("TODO: airArg {s}", .{@tagName(src_mcv)}),
3480 };
3611 const dst_mcv = try self.allocRegOrMem(inst, false);
3612 try self.genCopy(arg_ty, dst_mcv, src_mcv);
34813613
34823614 try self.genArgDbgInfo(inst, src_mcv);
34833615 break :result dst_mcv;
......@@ -3612,7 +3744,68 @@ fn genCall(
36123744 stack_frame_align.* = stack_frame_align.max(needed_call_frame.abi_align);
36133745 }
36143746
3615 for (call_info.args, 0..) |mc_arg, arg_i| try self.genCopy(arg_tys[arg_i], mc_arg, args[arg_i]);
3747 var reg_locks = std.ArrayList(?RegisterLock).init(allocator);
3748 defer reg_locks.deinit();
3749 try reg_locks.ensureTotalCapacity(8);
3750 defer for (reg_locks.items) |reg_lock| if (reg_lock) |lock| self.register_manager.unlockReg(lock);
3751
3752 const frame_indices = try allocator.alloc(FrameIndex, args.len);
3753 defer allocator.free(frame_indices);
3754
3755 switch (call_info.return_value.long) {
3756 .none, .unreach => {},
3757 .indirect => |reg_off| try self.register_manager.getReg(reg_off.reg, null),
3758 else => unreachable,
3759 }
3760 for (call_info.args, args, arg_tys, frame_indices) |dst_arg, src_arg, arg_ty, *frame_index| {
3761 switch (dst_arg) {
3762 .none => {},
3763 .register => |reg| {
3764 try self.register_manager.getReg(reg, null);
3765 try reg_locks.append(self.register_manager.lockReg(reg));
3766 },
3767 .register_pair => |regs| {
3768 for (regs) |reg| try self.register_manager.getReg(reg, null);
3769 try reg_locks.appendSlice(&self.register_manager.lockRegs(2, regs));
3770 },
3771 .indirect => |reg_off| {
3772 frame_index.* = try self.allocFrameIndex(FrameAlloc.initType(arg_ty, zcu));
3773 try self.genSetMem(.{ .frame = frame_index.* }, 0, arg_ty, src_arg);
3774 try self.register_manager.getReg(reg_off.reg, null);
3775 try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
3776 },
3777 else => return self.fail("TODO: genCall set arg {s}", .{@tagName(dst_arg)}),
3778 }
3779 }
3780
3781 switch (call_info.return_value.long) {
3782 .none, .unreach => {},
3783 .indirect => |reg_off| {
3784 const ret_ty = Type.fromInterned(fn_info.return_type);
3785 const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(ret_ty, zcu));
3786 try self.genSetReg(Type.usize, reg_off.reg, .{
3787 .lea_frame = .{ .index = frame_index, .off = -reg_off.off },
3788 });
3789 call_info.return_value.short = .{ .load_frame = .{ .index = frame_index } };
3790 try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
3791 },
3792 else => unreachable,
3793 }
3794
3795 for (call_info.args, arg_tys, args, frame_indices) |dst_arg, arg_ty, src_arg, frame_index| {
3796 switch (dst_arg) {
3797 .register_pair => try self.genCopy(arg_ty, dst_arg, src_arg),
3798 .register => |dst_reg| try self.genSetReg(
3799 arg_ty,
3800 dst_reg,
3801 src_arg,
3802 ),
3803 .indirect => |reg_off| try self.genSetReg(Type.usize, reg_off.reg, .{
3804 .lea_frame = .{ .index = frame_index, .off = -reg_off.off },
3805 }),
3806 else => return self.fail("TODO: genCall actual set {s}", .{@tagName(dst_arg)}),
3807 }
3808 }
36163809
36173810 // Due to incremental compilation, how function calls are generated depends
36183811 // on linking.
......@@ -3715,9 +3908,10 @@ fn airRet(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
37153908 defer self.register_manager.unlockReg(lock);
37163909
37173910 try self.genSetReg(Type.usize, reg_off.reg, self.ret_mcv.long);
3718 try self.genCopy(
3911 try self.genSetMem(
3912 .{ .reg = reg_off.reg },
3913 reg_off.off,
37193914 ret_ty,
3720 .{ .register_offset = reg_off },
37213915 .{ .air_ref = un_op },
37223916 );
37233917 },
......@@ -3745,6 +3939,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
37453939 switch (self.ret_mcv.short) {
37463940 .none => {},
37473941 .register, .register_pair => try self.load(self.ret_mcv.short, ptr, ptr_ty),
3942 .indirect => |reg_off| try self.genSetReg(ptr_ty, reg_off.reg, ptr),
37483943 else => unreachable,
37493944 }
37503945 self.ret_mcv.liveOut(self, inst);
......@@ -4058,7 +4253,7 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)
40584253
40594254 _ = maybe_inst;
40604255
4061 const err_off = errUnionErrorOffset(eu_ty.errorUnionPayload(zcu), zcu);
4256 const err_off: u31 = @intCast(errUnionErrorOffset(eu_ty.errorUnionPayload(zcu), zcu));
40624257
40634258 switch (eu_mcv) {
40644259 .register => |reg| {
......@@ -4081,15 +4276,25 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)
40814276 );
40824277 }
40834278
4084 return_mcv = try self.binOp(
4279 return try self.binOp(
40854280 .cmp_neq,
40864281 return_mcv,
40874282 Type.u16,
40884283 .{ .immediate = 0 },
40894284 Type.u16,
40904285 );
4091
4092 return return_mcv;
4286 },
4287 .load_frame => |frame_addr| {
4288 return self.binOp(
4289 .cmp_neq,
4290 .{ .load_frame = .{
4291 .index = frame_addr.index,
4292 .off = frame_addr.off + err_off,
4293 } },
4294 Type.anyerror,
4295 .{ .immediate = 0 },
4296 Type.anyerror,
4297 );
40934298 },
40944299 else => return self.fail("TODO implement isErr for {}", .{eu_mcv}),
40954300 }
......@@ -4839,7 +5044,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
48395044 const zcu = self.bin_file.comp.module.?;
48405045 const abi_size: u32 = @intCast(ty.abiSize(zcu));
48415046
4842 if (abi_size > 8) return self.fail("tried to set reg with size {}", .{abi_size});
5047 if (abi_size > 8) return std.debug.panic("tried to set reg with size {}", .{abi_size});
48435048
48445049 switch (src_mcv) {
48455050 .dead => unreachable,
......@@ -4924,7 +5129,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
49245129 if (src_reg.id() == reg.id())
49255130 return;
49265131
4927 // mov reg, src_reg
5132 // mv reg, src_reg
49285133 _ = try self.addInst(.{
49295134 .tag = .pseudo,
49305135 .ops = .pseudo_mv,
......@@ -4934,20 +5139,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
49345139 } },
49355140 });
49365141 },
4937 .register_pair => |pair| try self.genSetReg(ty, reg, .{ .register = pair[0] }),
4938 .memory => |addr| {
4939 try self.genSetReg(ty, reg, .{ .immediate = addr });
4940
4941 _ = try self.addInst(.{
4942 .tag = .ld,
4943 .ops = .rri,
4944 .data = .{ .i_type = .{
4945 .rd = reg,
4946 .rs1 = reg,
4947 .imm12 = Immediate.s(0),
4948 } },
4949 });
4950 },
5142 .register_pair => return self.fail("genSetReg should we allow reg -> reg_pair?", .{}),
49515143 .load_frame => |frame| {
49525144 _ = try self.addInst(.{
49535145 .tag = .pseudo,
......@@ -4966,28 +5158,49 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
49665158 } },
49675159 });
49685160 },
4969 .lea_frame => |frame| {
5161 .memory => |addr| {
5162 try self.genSetReg(ty, reg, .{ .immediate = addr });
5163
5164 _ = try self.addInst(.{
5165 .tag = .ld,
5166 .ops = .rri,
5167 .data = .{ .i_type = .{
5168 .rd = reg,
5169 .rs1 = reg,
5170 .imm12 = Immediate.s(0),
5171 } },
5172 });
5173 },
5174 .lea_frame, .register_offset => {
49705175 _ = try self.addInst(.{
49715176 .tag = .pseudo,
49725177 .ops = .pseudo_lea_rm,
49735178 .data = .{ .rm = .{
49745179 .r = reg,
4975 .m = .{
4976 .base = .{ .frame = frame.index },
4977 .mod = .{
4978 .rm = .{
4979 .size = self.memSize(ty),
4980 .disp = frame.off,
5180 .m = switch (src_mcv) {
5181 .register_offset => |reg_off| .{
5182 .base = .{ .reg = reg_off.reg },
5183 .mod = .{
5184 .rm = .{
5185 .size = self.memSize(ty),
5186 .disp = reg_off.off,
5187 },
5188 },
5189 },
5190 .lea_frame => |frame| .{
5191 .base = .{ .frame = frame.index },
5192 .mod = .{
5193 .rm = .{
5194 .size = self.memSize(ty),
5195 .disp = frame.off,
5196 },
49815197 },
49825198 },
5199 else => unreachable,
49835200 },
49845201 } },
49855202 });
49865203 },
4987 .load_symbol => {
4988 try self.genSetReg(ty, reg, src_mcv.address());
4989 try self.genSetReg(ty, reg, .{ .indirect = .{ .reg = reg } });
4990 },
49915204 .indirect => |reg_off| {
49925205 const load_tag: Mir.Inst.Tag = switch (abi_size) {
49935206 1 => .lb,
......@@ -5022,6 +5235,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
50225235 }) },
50235236 });
50245237 },
5238 .load_symbol => {
5239 try self.genSetReg(ty, reg, src_mcv.address());
5240 try self.genSetReg(ty, reg, .{ .indirect = .{ .reg = reg } });
5241 },
50255242 .air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
50265243 else => return self.fail("TODO: genSetReg {s}", .{@tagName(src_mcv)}),
50275244 }
......@@ -5052,7 +5269,6 @@ fn genSetMem(
50525269 src_mcv,
50535270 .{ .immediate = abi_size },
50545271 ),
5055
50565272 .register_offset,
50575273 .memory,
50585274 .indirect,
......@@ -5100,14 +5316,15 @@ fn genSetMem(
51005316 _ = try self.addInst(.{
51015317 .tag = .pseudo,
51025318 .ops = .pseudo_store_rm,
5103 .data = .{
5104 .rm = .{ .r = reg, .m = .{
5319 .data = .{ .rm = .{
5320 .r = reg,
5321 .m = .{
51055322 .base = .{ .frame = frame_index },
51065323 .mod = .{ .rm = .{
51075324 .size = Memory.Size.fromByteSize(src_size),
51085325 } },
5109 } },
5110 },
5326 },
5327 } },
51115328 });
51125329 try self.genSetMem(base, disp, ty, frame_mcv);
51135330 try self.freeValue(frame_mcv);
src/arch/riscv64/abi.zig+1-6
......@@ -149,12 +149,7 @@ pub fn classifySystem(ty: Type, zcu: *Module) [8]Class {
149149 // anyerror!void can fit into one register
150150 if (payload_bits == 0) return result;
151151
152 if (payload_bits <= 64) {
153 result[1] = .integer;
154 return result;
155 }
156
157 std.debug.panic("TODO: classifySystem ErrorUnion > 64 bit payload", .{});
152 return memory_class;
158153 },
159154 .Struct => {
160155 const layout = ty.containerLayout(zcu);