| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-01-19 20:43:42+01:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-04-25 21:54:47+02:00 |
| log | 593f45ee021f5310d6979f435fa4b6fcfaa5dabf |
| tree | 062c56950908035606361a7bcb0aa328bbf1f1ec |
| parent | 9e1e54d32449dadeb21bc2ce0fe9d246c466ebf0 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
llvm: switch most targets to using half and fp128 IR types
As of LLVM 22, most backends can (finally) handle legalization of these types as
necessary, so we don't need to do it ourselves anymore.
closes https://github.com/ziglang/zig/issues/236742 files changed, 1 insertions(+), 41 deletions(-)
src- codegen
lib/compiler_rt.zig+1-22
| ... | ... | @@ -447,29 +447,8 @@ pub const gnu_f16_abi = switch (builtin.cpu.arch) { |
| 447 | 447 | |
| 448 | 448 | pub const want_sparc_abi = builtin.cpu.arch.isSPARC(); |
| 449 | 449 | |
| 450 | /// This seems to mostly correspond to `clang::TargetInfo::HasFloat16`. | |
| 451 | 450 | pub fn F16T(comptime OtherType: type) type { |
| 452 | 451 | return switch (builtin.cpu.arch) { |
| 453 | .amdgcn, | |
| 454 | .arm, | |
| 455 | .armeb, | |
| 456 | .thumb, | |
| 457 | .thumbeb, | |
| 458 | .aarch64, | |
| 459 | .aarch64_be, | |
| 460 | .hexagon, | |
| 461 | .loongarch32, | |
| 462 | .loongarch64, | |
| 463 | .nvptx, | |
| 464 | .nvptx64, | |
| 465 | .riscv32, | |
| 466 | .riscv32be, | |
| 467 | .riscv64, | |
| 468 | .riscv64be, | |
| 469 | .s390x, | |
| 470 | .spirv32, | |
| 471 | .spirv64, | |
| 472 | => f16, | |
| 473 | 452 | .x86, .x86_64 => if (builtin.target.os.tag.isDarwin()) switch (OtherType) { |
| 474 | 453 | // Starting with LLVM 16, Darwin uses different abi for f16 |
| 475 | 454 | // depending on the type of the other return/argument..??? |
| ... | ... | @@ -477,7 +456,7 @@ pub fn F16T(comptime OtherType: type) type { |
| 477 | 456 | f80, f128 => f16, |
| 478 | 457 | else => unreachable, |
| 479 | 458 | } else f16, |
| 480 | else => u16, | |
| 459 | else => f16, | |
| 481 | 460 | }; |
| 482 | 461 | } |
| 483 | 462 |
src/codegen/llvm.zig-19
| ... | ... | @@ -4646,20 +4646,6 @@ fn toLlvmGlobalAddressSpace(wanted_address_space: std.builtin.AddressSpace, targ |
| 4646 | 4646 | /// or if it produces miscompilations. |
| 4647 | 4647 | pub fn backendSupportsF16(target: *const std.Target) bool { |
| 4648 | 4648 | return switch (target.cpu.arch) { |
| 4649 | // https://github.com/llvm/llvm-project/issues/97981 | |
| 4650 | .csky, | |
| 4651 | // https://github.com/llvm/llvm-project/issues/97981 | |
| 4652 | .powerpc, | |
| 4653 | .powerpcle, | |
| 4654 | .powerpc64, | |
| 4655 | .powerpc64le, | |
| 4656 | // https://github.com/llvm/llvm-project/issues/97981 | |
| 4657 | .wasm32, | |
| 4658 | .wasm64, | |
| 4659 | // https://github.com/llvm/llvm-project/issues/97981 | |
| 4660 | .sparc, | |
| 4661 | .sparc64, | |
| 4662 | => false, | |
| 4663 | 4649 | .arm, |
| 4664 | 4650 | .armeb, |
| 4665 | 4651 | .thumb, |
| ... | ... | @@ -4686,11 +4672,6 @@ pub fn backendSupportsF128(target: *const std.Target) bool { |
| 4686 | 4672 | return switch (target.cpu.arch) { |
| 4687 | 4673 | // https://github.com/llvm/llvm-project/issues/121122 |
| 4688 | 4674 | .amdgcn, |
| 4689 | // Test failures all over the place. | |
| 4690 | .mips64, | |
| 4691 | .mips64el, | |
| 4692 | // https://github.com/llvm/llvm-project/issues/41838 | |
| 4693 | .sparc, | |
| 4694 | 4675 | => false, |
| 4695 | 4676 | .arm, |
| 4696 | 4677 | .armeb, |