authorgravatar for luuk@degram.devLuuk de Gram <luuk@degram.dev> 2022-12-05 21:25:32+01:00
committergravatar for luuk@degram.devLuuk de Gram <luuk@degram.dev> 2022-12-12 17:41:56+01:00
log5a6b6992d887ffee1ea64b4f778c5c07ecbaf270
treed3bed0ee1d09a41343ef10b6ccac9aa4ff54d762
parent4832677c3bce61725c67306c4683921296abdff9
signaturelock-open Commit is signed but in an unrecognized format.

std: Add Wasm SIMD opcodes and value type

This adds the opcodes for both the simd128 and relaxed-simd features. Those instructions are required by the self-hosted WebAssembly backend. Additionally, this also adds the new `v128` Valtype which is required to represent a 128bit simd value. SIMD values that do not have exactly 128 bits will be represented differently.

1 files changed, 272 insertions(+), 0 deletions(-)

lib/std/wasm.zig+272
...@@ -237,6 +237,277 @@ pub const PrefixedOpcode = enum(u8) {...@@ -237,6 +237,277 @@ pub const PrefixedOpcode = enum(u8) {
237 _,237 _,
238};238};
239239
240/// Simd opcodes that require a prefix `0xFD`.
241/// Each opcode represents a varuint32, meaning
242/// they are encoded as leb128 in binary.
243pub const SimdOpcode = enum(u32) {
244 v128_load = 0x00,
245 v128_load8x8_s = 0x01,
246 v128_load8x8_u = 0x02,
247 v128_load16x4_s = 0x03,
248 v128_load16x4_u = 0x04,
249 v128_load32x2_s = 0x05,
250 v128_load32x2_u = 0x06,
251 v128_load8_splat = 0x07,
252 v128_load16_splat = 0x08,
253 v128_load32_splat = 0x09,
254 v128_load64_splat = 0x0A,
255 v128_store = 0x0B,
256 v128_const = 0x0C,
257 i8x16_shuffle = 0x0D,
258 i8x16_swizzle = 0x0E,
259 @"8x16_splat" = 0x0F,
260 i16x8_splat = 0x10,
261 i32x4_splat = 0x11,
262 i64x2_splat = 0x12,
263 f32x4_splat = 0x13,
264 f64x2_splat = 0x14,
265 @"8x16_extract_lane_s" = 0x15,
266 i8x16_extract_lane_u = 0x16,
267 i8x16_replace_lane = 0x17,
268 i16x8_extract_lane_s = 0x18,
269 i16x8_extract_lane_u = 0x19,
270 i16x8_replace_lane = 0x1A,
271 i32x4_extract_lane = 0x1B,
272 i32x4_replace_lane = 0x1C,
273 i64x2_extract_lane = 0x1D,
274 i64x2_replace_lane = 0x1E,
275 f32x4_extract_lane = 0x1F,
276 f32x4_replace_lane = 0x20,
277 f64x2_extract_lane = 0x21,
278 f64x2_replace_lane = 0x22,
279 i8x16_eq = 0x23,
280 i16x8_eq = 0x2D,
281 i32x4_eq = 0x37,
282 i8x16_ne = 0x24,
283 i16x8_ne = 0x2E,
284 i32x4_ne = 0x38,
285 i8x16_lt_s = 0x25,
286 i16x8_lt_s = 0x2F,
287 i32x4_lt_s = 0x39,
288 i8x16_lt_u = 0x26,
289 i16x8_lt_u = 0x30,
290 i32x4_lt_u = 0x3A,
291 i8x16_gt_s = 0x27,
292 i16x8_gt_s = 0x31,
293 i32x4_gt_s = 0x3B,
294 i8x16_gt_u = 0x28,
295 i16x8_gt_u = 0x32,
296 i32x4_gt_u = 0x3C,
297 i8x16_le_s = 0x29,
298 i16x8_le_s = 0x33,
299 i32x4_le_s = 0x3D,
300 i8x16_le_u = 0x2A,
301 i16x8_le_u = 0x34,
302 i32x4_le_u = 0x3E,
303 i8x16_ge_s = 0x2B,
304 i16x8_ge_s = 0x35,
305 i32x4_ge_s = 0x3F,
306 i8x16_ge_u = 0x2C,
307 i16x8_ge_u = 0x36,
308 i32x4_ge_u = 0x40,
309 f32x4_eq = 0x41,
310 f64x2_eq = 0x47,
311 f32x4_ne = 0x42,
312 f64x2_ne = 0x48,
313 f32x4_lt = 0x43,
314 f64x2_lt = 0x49,
315 f32x4_gt = 0x44,
316 f64x2_gt = 0x4A,
317 f32x4_le = 0x45,
318 f64x2_le = 0x4B,
319 f32x4_ge = 0x46,
320 f64x2_ge = 0x4C,
321 v128_not = 0x4D,
322 v128_and = 0x4E,
323 v128_andnot = 0x4F,
324 v128_or = 0x50,
325 v128_xor = 0x51,
326 v128_bitselect = 0x52,
327 v128_any_true = 0x53,
328 v128_load8_lane = 0x54,
329 v128_load16_lane = 0x55,
330 v128_load32_lane = 0x56,
331 v128_load64_lane = 0x57,
332 v128_store8_lane = 0x58,
333 v128_store16_lane = 0x59,
334 v128_store32_lane = 0x5A,
335 v128_store64_lane = 0x5B,
336 v128_load32_zero = 0x5C,
337 v128_load64_zero = 0x5D,
338 f32x4_demote_f64x2_zero = 0x5E,
339 f64x2_promote_low_f32x4 = 0x5F,
340 i8x16_abs = 0x60,
341 i16x8_abs = 0x80,
342 i32x4_abs = 0xA0,
343 i64x2_abs = 0xC0,
344 i8x16_neg = 0x61,
345 i16x8_neg = 0x81,
346 i32x4_neg = 0xA1,
347 i64x2_neg = 0xC1,
348 i8x16_popcnt = 0x62,
349 i16x8_q15mulr_sat_s = 0x82,
350 i8x16_all_true = 0x63,
351 i16x8_all_true = 0x83,
352 i32x4_all_true = 0xA3,
353 i64x2_all_true = 0xC3,
354 i8x16_bitmask = 0x64,
355 i16x8_bitmask = 0x84,
356 i32x4_bitmask = 0xA4,
357 i64x2_bitmask = 0xC4,
358 i8x16_narrow_i16x8_s = 0x65,
359 i16x8_narrow_i32x4_s = 0x85,
360 i8x16_narrow_i16x8_u = 0x66,
361 i16x8_narrow_i32x4_u = 0x86,
362 f32x4_ceil = 0x67,
363 i16x8_extend_low_i8x16_s = 0x87,
364 i32x4_extend_low_i16x8_s = 0xA7,
365 i64x2_extend_low_i32x4_s = 0xC7,
366 f32x4_floor = 0x68,
367 i16x8_extend_high_i8x16_s = 0x88,
368 i32x4_extend_high_i16x8_s = 0xA8,
369 i64x2_extend_high_i32x4_s = 0xC8,
370 f32x4_trunc = 0x69,
371 i16x8_extend_low_i8x16_u = 0x89,
372 i32x4_extend_low_i16x8_u = 0xA9,
373 i64x2_extend_low_i32x4_u = 0xC9,
374 f32x4_nearest = 0x6A,
375 i16x8_extend_high_i8x16_u = 0x8A,
376 i32x4_extend_high_i16x8_u = 0xAA,
377 i64x2_extend_high_i32x4_u = 0xCA,
378 i8x16_shl = 0x6B,
379 i16x8_shl = 0x8B,
380 i32x4_shl = 0xAB,
381 i64x2_shl = 0xCB,
382 i8x16_shr_s = 0x6C,
383 i16x8_shr_s = 0x8C,
384 i32x4_shr_s = 0xAC,
385 i64x2_shr_s = 0xCC,
386 i8x16_shr_u = 0x6D,
387 i16x8_shr_u = 0x8D,
388 i32x4_shr_u = 0xAD,
389 i64x2_shr_u = 0xCD,
390 i8x16_add = 0x6E,
391 i16x8_add = 0x8E,
392 i32x4_add = 0xAE,
393 i64x2_add = 0xCE,
394 i8x16_add_sat_s = 0x6F,
395 i16x8_add_sat_s = 0x8F,
396 i8x16_add_sat_u = 0x70,
397 i16x8_add_sat_u = 0x90,
398 i8x16_sub = 0x71,
399 i16x8_sub = 0x91,
400 i32x4_sub = 0xB1,
401 i64x2_sub = 0xD1,
402 i8x16_sub_sat_s = 0x72,
403 i16x8_sub_sat_s = 0x92,
404 i8x16_sub_sat_u = 0x73,
405 i16x8_sub_sat_u = 0x93,
406 f64x2_ceil = 0x74,
407 f64x2_nearest = 0x94,
408 f64x2_floor = 0x75,
409 i16x8_mul = 0x95,
410 i32x4_mul = 0xB5,
411 i64x2_mul = 0xD5,
412 i8x16_min_s = 0x76,
413 i16x8_min_s = 0x96,
414 i32x4_min_s = 0xB6,
415 i64x2_eq = 0xD6,
416 i8x16_min_u = 0x77,
417 i16x8_min_u = 0x97,
418 i32x4_min_u = 0xB7,
419 i64x2_ne = 0xD7,
420 i8x16_max_s = 0x78,
421 i16x8_max_s = 0x98,
422 i32x4_max_s = 0xB8,
423 i64x2_lt_s = 0xD8,
424 i8x16_max_u = 0x79,
425 i16x8_max_u = 0x99,
426 i32x4_max_u = 0xB9,
427 i64x2_gt_s = 0xD9,
428 f64x2_trunc = 0x7A,
429 i32x4_dot_i16x8_s = 0xBA,
430 i64x2_le_s = 0xDA,
431 i8x16_avgr_u = 0x7B,
432 i16x8_avgr_u = 0x9B,
433 i64x2_ge_s = 0xDB,
434 i16x8_extadd_pairwise_i8x16_s = 0x7C,
435 i16x8_extmul_low_i8x16_s = 0x9C,
436 i32x4_extmul_low_i16x8_s = 0xBC,
437 i64x2_extmul_low_i32x4_s = 0xDC,
438 i16x8_extadd_pairwise_i8x16_u = 0x7D,
439 i16x8_extmul_high_i8x16_s = 0x9D,
440 i32x4_extmul_high_i16x8_s = 0xBD,
441 i64x2_extmul_high_i32x4_s = 0xDD,
442 i32x4_extadd_pairwise_i16x8_s = 0x7E,
443 i16x8_extmul_low_i8x16_u = 0x9E,
444 i32x4_extmul_low_i16x8_u = 0xBE,
445 i64x2_extmul_low_i32x4_u = 0xDE,
446 i32x4_extadd_pairwise_i16x8_u = 0x7F,
447 i16x8_extmul_high_i8x16_u = 0x9F,
448 i32x4_extmul_high_i16x8_u = 0xBF,
449 i64x2_extmul_high_i32x4_u = 0xDF,
450 f32x4_abs = 0xE0,
451 f64x2_abs = 0xEC,
452 f32x4_neg = 0xE1,
453 f64x2_neg = 0xED,
454 f32x4_sqrt = 0xE3,
455 f64x2_sqrt = 0xEF,
456 f32x4_add = 0xE4,
457 f64x2_add = 0xF0,
458 f32x4_sub = 0xE5,
459 f64x2_sub = 0xF1,
460 f32x4_mul = 0xE6,
461 f64x2_mul = 0xF2,
462 f32x4_div = 0xE7,
463 f64x2_div = 0xF3,
464 f32x4_min = 0xE8,
465 f64x2_min = 0xF4,
466 f32x4_max = 0xE9,
467 f64x2_max = 0xF5,
468 f32x4_pmin = 0xEA,
469 f64x2_pmin = 0xF6,
470 f32x4_pmax = 0xEB,
471 f64x2_pmax = 0xF7,
472 i32x4_trunc_sat_f32x4_s = 0xF8,
473 i32x4_trunc_sat_f32x4_u = 0xF9,
474 f32x4_convert_i32x4_s = 0xFA,
475 f32x4_convert_i32x4_u = 0xFB,
476 i32x4_trunc_sat_f64x2_s_zero = 0xFC,
477 i32x4_trunc_sat_f64x2_u_zero = 0xFD,
478 f64x2_convert_low_i32x4_s = 0xFE,
479 f64x2_convert_low_i32x4_u = 0xFF,
480
481 // relaxed-simd opcodes
482 i8x16_relaxed_swizzle = 0x100,
483 i32x4_relaxed_trunc_f32x4_s = 0x101,
484 i32x4_relaxed_trunc_f32x4_u = 0x102,
485 i32x4_relaxed_trunc_f64x2_s_zero = 0x103,
486 i32x4_relaxed_trunc_f64x2_u_zero = 0x104,
487 f32x4_relaxed_madd = 0x105,
488 f32x4_relaxed_nmadd = 0x106,
489 f64x2_relaxed_madd = 0x107,
490 f64x2_relaxed_nmadd = 0x108,
491 i8x16_relaxed_laneselect = 0x109,
492 i16x8_relaxed_laneselect = 0x10a,
493 i32x4_relaxed_laneselect = 0x10b,
494 i64x2_relaxed_laneselect = 0x10c,
495 f32x4_relaxed_min = 0x10d,
496 f32x4_relaxed_max = 0x10e,
497 f64x2_relaxed_min = 0x10f,
498 f64x2_relaxed_max = 0x110,
499 i16x8_relaxed_q15mulr_s = 0x111,
500 i16x8_relaxed_dot_i8x16_i7x16_s = 0x112,
501 i32x4_relaxed_dot_i8x16_i7x16_add_s = 0x113,
502 f32x4_relaxed_dot_bf16x8_add_f32x4 = 0x114,
503};
504
505/// Returns the integer value of an `SimdOpcode`. Used by the Zig compiler
506/// to write instructions to the wasm binary file
507pub fn simdOpcode(op: SimdOpcode) u32 {
508 return @enumToInt(op);
509}
510
240/// Enum representing all Wasm value types as per spec:511/// Enum representing all Wasm value types as per spec:
241/// https://webassembly.github.io/spec/core/binary/types.html512/// https://webassembly.github.io/spec/core/binary/types.html
242pub const Valtype = enum(u8) {513pub const Valtype = enum(u8) {
...@@ -244,6 +515,7 @@ pub const Valtype = enum(u8) {...@@ -244,6 +515,7 @@ pub const Valtype = enum(u8) {
244 i64 = 0x7E,515 i64 = 0x7E,
245 f32 = 0x7D,516 f32 = 0x7D,
246 f64 = 0x7C,517 f64 = 0x7C,
518 v128 = 0x7B,
247};519};
248520
249/// Returns the integer value of a `Valtype`521/// Returns the integer value of a `Valtype`