| ... | ... | @@ -1,6 +1,7 @@ |
| 1 | 1 | const std = @import("std"); |
| 2 | 2 | const builtin = @import("builtin"); |
| 3 | | const arch = builtin.cpu.arch; |
| 3 | const cpu = builtin.cpu; |
| 4 | const arch = cpu.arch; |
| 4 | 5 | |
| 5 | 6 | const linkage: std.builtin.GlobalLinkage = if (builtin.is_test) .Internal else .Weak; |
| 6 | 7 | |
| ... | ... | @@ -27,9 +28,7 @@ const largest_atomic_size = switch (arch) { |
| 27 | 28 | // On SPARC systems that lacks CAS and/or swap instructions, the only |
| 28 | 29 | // available atomic operation is a test-and-set (`ldstub`), so we force |
| 29 | 30 | // every atomic memory access to go through the lock. |
| 30 | | // XXX: Check the presence of CAS/swap instructions and set this parameter |
| 31 | | // accordingly. |
| 32 | | .sparc, .sparcel, .sparcv9 => 0, |
| 31 | .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0, |
| 33 | 32 | |
| 34 | 33 | // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b |
| 35 | 34 | // and set this parameter accordingly. |
Koakuma <koachan@protonmail.com> 2022-04-15 19:40:36+07:00
lib