authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-27 11:44:11+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-29 09:41:24+02:00
log5b68595255d844764d7a4c1869992c8d666d6960
treefe0a8e5acda1bd8371935096302972ff804358f2
parent390c7d84b24355ba3346ec1214a0a8de8a7c5df3
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.atomic: Define specialized cache_line values for more architectures.

1 files changed, 41 insertions(+), 6 deletions(-)

lib/std/atomic.zig+41-6
......@@ -429,26 +429,61 @@ pub const cache_line = switch (builtin.cpu.arch) {
429429 // - https://www.mono-project.com/news/2016/09/12/arm64-icache/
430430 // - https://cpufun.substack.com/p/more-m1-fun-hardware-information
431431 //
432 // powerpc64: PPC has 128-byte cache lines
432 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/arc/Kconfig#L212
433433 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
434 .x86_64, .aarch64, .powerpc64 => 128,
434 .x86_64,
435 .aarch64,
436 .aarch64_be,
437 .arc,
438 .powerpc64,
439 .powerpc64le,
440 => 128,
435441
436 // These platforms reportedly have 32-byte cache lines
437442 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
438443 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
439444 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
440445 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
441446 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
442 .arm, .mips, .mips64, .riscv64 => 32,
447 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/hexagon/include/asm/cache.h#L13
448 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
449 .arm,
450 .armeb,
451 .thumb,
452 .thumbeb,
453 .hexagon,
454 .mips,
455 .mipsel,
456 .mips64,
457 .mips64el,
458 .riscv32,
459 .riscv64,
460 .sparc,
461 .sparcel,
462 .sparc64,
463 => 32,
464
465 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/m68k/include/asm/cache.h#L10
466 .m68k,
467 => 16,
468
469 // - https://www.ti.com/lit/pdf/slaa498
470 .msp430,
471 => 8,
443472
444 // This platform reportedly has 256-byte cache lines
445473 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
446 .s390x => 256,
474 // - https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf
475 .s390x,
476 .ve,
477 => 256,
447478
448479 // Other x86 and WASM platforms have 64-byte cache lines.
449480 // The rest of the architectures are assumed to be similar.
450481 // - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
482 // - https://github.com/golang/go/blob/0a9321ad7f8c91e1b0c7184731257df923977eb9/src/internal/cpu/cpu_loong64.go#L11
451483 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
484 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209
485 // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183
486 // - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf
452487 else => 64,
453488};
454489