authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-02 03:14:51-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-14 23:04:05-07:00
log5ec926cdbf05312111cb5451bf152ee054f9ef1f
treedbd77c69c7e4f7bec6e4cf0c3a7cd95a22dc8057
parent5a2c547fc1eedcec52e9e7259449d9a093e21ab1
signaturelock-open Commit is signed but in an unrecognized format.

riscv: refactor `bin_file` and `zcu` usage

1 files changed, 29 insertions(+), 38 deletions(-)

src/arch/riscv64/CodeGen.zig+29-38
......@@ -1,8 +1,12 @@
11const std = @import("std");
22const builtin = @import("builtin");
3const build_options = @import("build_options");
4
35const mem = std.mem;
46const math = std.math;
57const assert = std.debug.assert;
8const Allocator = mem.Allocator;
9
610const Air = @import("../../Air.zig");
711const Mir = @import("Mir.zig");
812const Emit = @import("Emit.zig");
......@@ -14,18 +18,16 @@ const Zcu = @import("../../Zcu.zig");
1418const Package = @import("../../Package.zig");
1519const InternPool = @import("../../InternPool.zig");
1620const Compilation = @import("../../Compilation.zig");
21const trace = @import("../../tracy.zig").trace;
22const codegen = @import("../../codegen.zig");
23
1724const ErrorMsg = Zcu.ErrorMsg;
1825const Target = std.Target;
19const Allocator = mem.Allocator;
20const trace = @import("../../tracy.zig").trace;
21const DW = std.dwarf;
22const leb128 = std.leb;
26
2327const log = std.log.scoped(.riscv_codegen);
2428const tracking_log = std.log.scoped(.tracking);
2529const verbose_tracking_log = std.log.scoped(.verbose_tracking);
2630const wip_mir_log = std.log.scoped(.wip_mir);
27const build_options = @import("build_options");
28const codegen = @import("../../codegen.zig");
2931const Alignment = InternPool.Alignment;
3032
3133const CodeGenError = codegen.CodeGenError;
......@@ -46,15 +48,16 @@ const RegisterLock = RegisterManager.RegisterLock;
4648
4749const InnerError = CodeGenError || error{OutOfRegisters};
4850
49gpa: Allocator,
5051pt: Zcu.PerThread,
5152air: Air,
52mod: *Package.Module,
5353liveness: Liveness,
54zcu: *Zcu,
5455bin_file: *link.File,
56gpa: Allocator,
57
58mod: *Package.Module,
5559target: *const std.Target,
5660func_index: InternPool.Index,
57code: *std.ArrayList(u8),
5861debug_output: DebugInfoOutput,
5962err_msg: ?*ErrorMsg,
6063args: []MCValue,
......@@ -63,9 +66,7 @@ fn_type: Type,
6366arg_index: usize,
6467src_loc: Zcu.LazySrcLoc,
6568
66/// MIR Instructions
6769mir_instructions: std.MultiArrayList(Mir.Inst) = .{},
68/// MIR extra data
6970mir_extra: std.ArrayListUnmanaged(u32) = .{},
7071
7172/// Byte offset within the source file of the ending curly.
......@@ -731,16 +732,16 @@ pub fn generate(
731732 }
732733 try branch_stack.append(.{});
733734
734 var function = Func{
735 var function: Func = .{
735736 .gpa = gpa,
736737 .air = air,
737738 .pt = pt,
738739 .mod = mod,
740 .zcu = zcu,
741 .bin_file = bin_file,
739742 .liveness = liveness,
740743 .target = target,
741 .bin_file = bin_file,
742744 .func_index = func_index,
743 .code = code,
744745 .debug_output = debug_output,
745746 .err_msg = null,
746747 .args = undefined, // populated after `resolveCallingConventionValues`
......@@ -825,7 +826,7 @@ pub fn generate(
825826 else => |e| return e,
826827 };
827828
828 var mir = Mir{
829 var mir: Mir = .{
829830 .instructions = function.mir_instructions.toOwnedSlice(),
830831 .extra = try function.mir_extra.toOwnedSlice(gpa),
831832 .frame_locs = function.frame_locs.toOwnedSlice(),
......@@ -833,7 +834,6 @@ pub fn generate(
833834 defer mir.deinit(gpa);
834835
835836 var emit: Emit = .{
836 .bin_file = bin_file,
837837 .lower = .{
838838 .pt = pt,
839839 .allocator = gpa,
......@@ -844,6 +844,7 @@ pub fn generate(
844844 .link_mode = comp.config.link_mode,
845845 .pic = mod.pic,
846846 },
847 .bin_file = bin_file,
847848 .debug_output = debug_output,
848849 .code = code,
849850 .prev_di_pc = 0,
......@@ -932,7 +933,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir)
932933}
933934
934935const FormatDeclData = struct {
935 mod: *Zcu,
936 zcu: *Zcu,
936937 decl_index: InternPool.DeclIndex,
937938};
938939fn formatDecl(
......@@ -941,11 +942,11 @@ fn formatDecl(
941942 _: std.fmt.FormatOptions,
942943 writer: anytype,
943944) @TypeOf(writer).Error!void {
944 try writer.print("{}", .{data.mod.declPtr(data.decl_index).fqn.fmt(&data.mod.intern_pool)});
945 try writer.print("{}", .{data.zcu.declPtr(data.decl_index).fqn.fmt(&data.zcu.intern_pool)});
945946}
946947fn fmtDecl(func: *Func, decl_index: InternPool.DeclIndex) std.fmt.Formatter(formatDecl) {
947948 return .{ .data = .{
948 .mod = func.pt.zcu,
949 .zcu = func.zcu,
949950 .decl_index = decl_index,
950951 } };
951952}
......@@ -1882,14 +1883,9 @@ fn symbolIndex(func: *Func) !u32 {
18821883 const pt = func.pt;
18831884 const zcu = pt.zcu;
18841885 const decl_index = zcu.funcOwnerDeclIndex(func.func_index);
1885 return switch (func.bin_file.tag) {
1886 .elf => blk: {
1887 const elf_file = func.bin_file.cast(link.File.Elf).?;
1888 const atom_index = try elf_file.zigObjectPtr().?.getOrCreateMetadataForDecl(elf_file, decl_index);
1889 break :blk atom_index;
1890 },
1891 else => return func.fail("TODO symbolIndex {s}", .{@tagName(func.bin_file.tag)}),
1892 };
1886 const elf_file = func.bin_file.cast(link.File.Elf).?;
1887 const atom_index = try elf_file.zigObjectPtr().?.getOrCreateMetadataForDecl(elf_file, decl_index);
1888 return atom_index;
18931889}
18941890
18951891fn allocFrameIndex(func: *Func, alloc: FrameAlloc) !FrameIndex {
......@@ -1940,9 +1936,7 @@ fn typeRegClass(func: *Func, ty: Type) abi.RegisterClass {
19401936}
19411937
19421938fn regGeneralClassForType(func: *Func, ty: Type) RegisterManager.RegisterBitSet {
1943 const pt = func.pt;
1944 const zcu = pt.zcu;
1945 return switch (ty.zigTypeTag(zcu)) {
1939 return switch (ty.zigTypeTag(func.pt.zcu)) {
19461940 .Float => abi.Registers.Float.general_purpose,
19471941 .Vector => abi.Registers.Vector.general_purpose,
19481942 else => abi.Registers.Integer.general_purpose,
......@@ -1950,9 +1944,7 @@ fn regGeneralClassForType(func: *Func, ty: Type) RegisterManager.RegisterBitSet
19501944}
19511945
19521946fn regTempClassForType(func: *Func, ty: Type) RegisterManager.RegisterBitSet {
1953 const pt = func.pt;
1954 const zcu = pt.zcu;
1955 return switch (ty.zigTypeTag(zcu)) {
1947 return switch (ty.zigTypeTag(func.pt.zcu)) {
19561948 .Float => abi.Registers.Float.temporary,
19571949 .Vector => abi.Registers.Vector.general_purpose, // there are no temporary vector registers
19581950 else => abi.Registers.Integer.temporary,
......@@ -1961,9 +1953,10 @@ fn regTempClassForType(func: *Func, ty: Type) RegisterManager.RegisterBitSet {
19611953
19621954fn allocRegOrMem(func: *Func, elem_ty: Type, inst: ?Air.Inst.Index, reg_ok: bool) !MCValue {
19631955 const pt = func.pt;
1956 const zcu = pt.zcu;
19641957
19651958 const bit_size = elem_ty.bitSize(pt);
1966 const min_size: u64 = switch (elem_ty.zigTypeTag(pt.zcu)) {
1959 const min_size: u64 = switch (elem_ty.zigTypeTag(zcu)) {
19671960 .Float => if (func.hasFeature(.d)) 64 else 32,
19681961 .Vector => 256, // TODO: calculate it from avl * vsew
19691962 else => 64,
......@@ -1973,7 +1966,7 @@ fn allocRegOrMem(func: *Func, elem_ty: Type, inst: ?Air.Inst.Index, reg_ok: bool
19731966 if (func.register_manager.tryAllocReg(inst, func.regGeneralClassForType(elem_ty))) |reg| {
19741967 return .{ .register = reg };
19751968 }
1976 } else if (reg_ok and elem_ty.zigTypeTag(pt.zcu) == .Vector) {
1969 } else if (reg_ok and elem_ty.zigTypeTag(zcu) == .Vector) {
19771970 return func.fail("did you forget to extend vector registers before allocating", .{});
19781971 }
19791972
......@@ -7270,9 +7263,7 @@ fn parseRegName(name: []const u8) ?Register {
72707263}
72717264
72727265fn typeOf(func: *Func, inst: Air.Inst.Ref) Type {
7273 const pt = func.pt;
7274 const zcu = pt.zcu;
7275 return func.air.typeOf(inst, &zcu.intern_pool);
7266 return func.air.typeOf(inst, &func.pt.zcu.intern_pool);
72767267}
72777268
72787269fn typeOfIndex(func: *Func, inst: Air.Inst.Index) Type {