| ... | ... | @@ -442,6 +442,7 @@ pub const X86 = enum(usize) { |
| 442 | 442 | process_mrelease = 448, |
| 443 | 443 | futex_waitv = 449, |
| 444 | 444 | set_mempolicy_home_node = 450, |
| 445 | cachestat = 451, |
| 445 | 446 | }; |
| 446 | 447 | |
| 447 | 448 | pub const X64 = enum(usize) { |
| ... | ... | @@ -807,6 +808,7 @@ pub const X64 = enum(usize) { |
| 807 | 808 | process_mrelease = 448, |
| 808 | 809 | futex_waitv = 449, |
| 809 | 810 | set_mempolicy_home_node = 450, |
| 811 | cachestat = 451, |
| 810 | 812 | }; |
| 811 | 813 | |
| 812 | 814 | pub const Arm = enum(usize) { |
| ... | ... | @@ -1215,6 +1217,7 @@ pub const Arm = enum(usize) { |
| 1215 | 1217 | process_mrelease = 448, |
| 1216 | 1218 | futex_waitv = 449, |
| 1217 | 1219 | set_mempolicy_home_node = 450, |
| 1220 | cachestat = 451, |
| 1218 | 1221 | |
| 1219 | 1222 | breakpoint = arm_base + 1, |
| 1220 | 1223 | cacheflush = arm_base + 2, |
| ... | ... | @@ -1607,6 +1610,7 @@ pub const Sparc64 = enum(usize) { |
| 1607 | 1610 | process_mrelease = 448, |
| 1608 | 1611 | futex_waitv = 449, |
| 1609 | 1612 | set_mempolicy_home_node = 450, |
| 1613 | cachestat = 451, |
| 1610 | 1614 | }; |
| 1611 | 1615 | |
| 1612 | 1616 | pub const Mips = enum(usize) { |
| ... | ... | @@ -2030,6 +2034,7 @@ pub const Mips = enum(usize) { |
| 2030 | 2034 | process_mrelease = Linux + 448, |
| 2031 | 2035 | futex_waitv = Linux + 449, |
| 2032 | 2036 | set_mempolicy_home_node = Linux + 450, |
| 2037 | cachestat = Linux + 451, |
| 2033 | 2038 | }; |
| 2034 | 2039 | |
| 2035 | 2040 | pub const Mips64 = enum(usize) { |
| ... | ... | @@ -2389,6 +2394,7 @@ pub const Mips64 = enum(usize) { |
| 2389 | 2394 | process_mrelease = Linux + 448, |
| 2390 | 2395 | futex_waitv = Linux + 449, |
| 2391 | 2396 | set_mempolicy_home_node = Linux + 450, |
| 2397 | cachestat = Linux + 451, |
| 2392 | 2398 | }; |
| 2393 | 2399 | |
| 2394 | 2400 | pub const PowerPC = enum(usize) { |
| ... | ... | @@ -2823,6 +2829,7 @@ pub const PowerPC = enum(usize) { |
| 2823 | 2829 | process_mrelease = 448, |
| 2824 | 2830 | futex_waitv = 449, |
| 2825 | 2831 | set_mempolicy_home_node = 450, |
| 2832 | cachestat = 451, |
| 2826 | 2833 | }; |
| 2827 | 2834 | |
| 2828 | 2835 | pub const PowerPC64 = enum(usize) { |
| ... | ... | @@ -3229,6 +3236,7 @@ pub const PowerPC64 = enum(usize) { |
| 3229 | 3236 | process_mrelease = 448, |
| 3230 | 3237 | futex_waitv = 449, |
| 3231 | 3238 | set_mempolicy_home_node = 450, |
| 3239 | cachestat = 451, |
| 3232 | 3240 | }; |
| 3233 | 3241 | |
| 3234 | 3242 | pub const Arm64 = enum(usize) { |
| ... | ... | @@ -3538,6 +3546,7 @@ pub const Arm64 = enum(usize) { |
| 3538 | 3546 | process_mrelease = 448, |
| 3539 | 3547 | futex_waitv = 449, |
| 3540 | 3548 | set_mempolicy_home_node = 450, |
| 3549 | cachestat = 451, |
| 3541 | 3550 | }; |
| 3542 | 3551 | |
| 3543 | 3552 | pub const RiscV64 = enum(usize) { |
| ... | ... | @@ -3848,6 +3857,7 @@ pub const RiscV64 = enum(usize) { |
| 3848 | 3857 | process_mrelease = 448, |
| 3849 | 3858 | futex_waitv = 449, |
| 3850 | 3859 | set_mempolicy_home_node = 450, |
| 3860 | cachestat = 451, |
| 3851 | 3861 | |
| 3852 | 3862 | riscv_flush_icache = arch_specific_syscall + 15, |
| 3853 | 3863 | }; |