| ... | ... | @@ -558,6 +558,8 @@ static void destroy_instruction_src(IrInstSrc *inst) { |
| 558 | 558 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcCallArgs *>(inst)); |
| 559 | 559 | case IrInstSrcIdWasmMemorySize: |
| 560 | 560 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemorySize *>(inst)); |
| 561 | case IrInstSrcIdWasmMemoryGrow: |
| 562 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcWasmMemoryGrow *>(inst)); |
| 561 | 563 | } |
| 562 | 564 | zig_unreachable(); |
| 563 | 565 | } |
| ... | ... | @@ -740,6 +742,8 @@ void destroy_instruction_gen(IrInstGen *inst) { |
| 740 | 742 | return heap::c_allocator.destroy(reinterpret_cast<IrInstGenNegationWrapping *>(inst)); |
| 741 | 743 | case IrInstGenIdWasmMemorySize: |
| 742 | 744 | return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemorySize *>(inst)); |
| 745 | case IrInstGenIdWasmMemoryGrow: |
| 746 | return heap::c_allocator.destroy(reinterpret_cast<IrInstGenWasmMemoryGrow *>(inst)); |
| 743 | 747 | } |
| 744 | 748 | zig_unreachable(); |
| 745 | 749 | } |
| ... | ... | @@ -1338,10 +1342,6 @@ static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolNot *) { |
| 1338 | 1342 | return IrInstSrcIdBoolNot; |
| 1339 | 1343 | } |
| 1340 | 1344 | |
| 1341 | | static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemorySize *) { |
| 1342 | | return IrInstSrcIdWasmMemorySize; |
| 1343 | | } |
| 1344 | | |
| 1345 | 1345 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemset *) { |
| 1346 | 1346 | return IrInstSrcIdMemset; |
| 1347 | 1347 | } |
| ... | ... | @@ -1618,6 +1618,14 @@ static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillEnd *) { |
| 1618 | 1618 | return IrInstSrcIdSpillEnd; |
| 1619 | 1619 | } |
| 1620 | 1620 | |
| 1621 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemorySize *) { |
| 1622 | return IrInstSrcIdWasmMemorySize; |
| 1623 | } |
| 1624 | |
| 1625 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemoryGrow *) { |
| 1626 | return IrInstSrcIdWasmMemoryGrow; |
| 1627 | } |
| 1628 | |
| 1621 | 1629 | |
| 1622 | 1630 | static constexpr IrInstGenId ir_inst_id(IrInstGenDeclVar *) { |
| 1623 | 1631 | return IrInstGenIdDeclVar; |
| ... | ... | @@ -1967,6 +1975,10 @@ static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemorySize *) { |
| 1967 | 1975 | return IrInstGenIdWasmMemorySize; |
| 1968 | 1976 | } |
| 1969 | 1977 | |
| 1978 | static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemoryGrow *) { |
| 1979 | return IrInstGenIdWasmMemoryGrow; |
| 1980 | } |
| 1981 | |
| 1970 | 1982 | template<typename T> |
| 1971 | 1983 | static T *ir_create_instruction(IrBuilderSrc *irb, Scope *scope, AstNode *source_node) { |
| 1972 | 1984 | T *special_instruction = heap::c_allocator.create<T>(); |
| ... | ... | @@ -3654,20 +3666,6 @@ static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, IrInst *source_instr, Ir |
| 3654 | 3666 | return &instruction->base; |
| 3655 | 3667 | } |
| 3656 | 3668 | |
| 3657 | | static IrInstSrc *ir_build_wasm_memory_size_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node) { |
| 3658 | | IrInstSrcWasmMemorySize *instruction = ir_build_instruction<IrInstSrcWasmMemorySize>(irb, scope, source_node); |
| 3659 | | |
| 3660 | | return &instruction->base; |
| 3661 | | } |
| 3662 | | |
| 3663 | | static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, IrInst *source_instr) { |
| 3664 | | IrInstGenWasmMemorySize *instruction = ir_build_inst_gen<IrInstGenWasmMemorySize>(&ira->new_irb, |
| 3665 | | source_instr->scope, source_instr->source_node); |
| 3666 | | instruction->base.value->type = ira->codegen->builtin_types.entry_i32; |
| 3667 | | |
| 3668 | | return &instruction->base; |
| 3669 | | } |
| 3670 | | |
| 3671 | 3669 | static IrInstSrc *ir_build_memset_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, |
| 3672 | 3670 | IrInstSrc *dest_ptr, IrInstSrc *byte, IrInstSrc *count) |
| 3673 | 3671 | { |
| ... | ... | @@ -4987,6 +4985,41 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, IrInst *source_in |
| 4987 | 4985 | return &instruction->base; |
| 4988 | 4986 | } |
| 4989 | 4987 | |
| 4988 | static IrInstSrc *ir_build_wasm_memory_size_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node) { |
| 4989 | IrInstSrcWasmMemorySize *instruction = ir_build_instruction<IrInstSrcWasmMemorySize>(irb, scope, source_node); |
| 4990 | |
| 4991 | return &instruction->base; |
| 4992 | } |
| 4993 | |
| 4994 | static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, IrInst *source_instr) { |
| 4995 | IrInstGenWasmMemorySize *instruction = ir_build_inst_gen<IrInstGenWasmMemorySize>(&ira->new_irb, |
| 4996 | source_instr->scope, source_instr->source_node); |
| 4997 | instruction->base.value->type = ira->codegen->builtin_types.entry_i32; |
| 4998 | |
| 4999 | return &instruction->base; |
| 5000 | } |
| 5001 | |
| 5002 | static IrInstSrc *ir_build_wasm_memory_grow_src(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *delta) { |
| 5003 | IrInstSrcWasmMemoryGrow *instruction = ir_build_instruction<IrInstSrcWasmMemoryGrow>(irb, scope, source_node); |
| 5004 | instruction->delta = delta; |
| 5005 | |
| 5006 | ir_ref_instruction(delta, irb->current_basic_block); |
| 5007 | |
| 5008 | return &instruction->base; |
| 5009 | } |
| 5010 | |
| 5011 | static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, IrInst *source_instr, IrInstGen *delta) { |
| 5012 | IrInstGenWasmMemoryGrow *instruction = ir_build_inst_gen<IrInstGenWasmMemoryGrow>(&ira->new_irb, |
| 5013 | source_instr->scope, source_instr->source_node); |
| 5014 | instruction->base.value->type = ira->codegen->builtin_types.entry_i32; |
| 5015 | instruction->delta = delta; |
| 5016 | |
| 5017 | ir_ref_inst_gen(delta); |
| 5018 | |
| 5019 | return &instruction->base; |
| 5020 | } |
| 5021 | |
| 5022 | |
| 4990 | 5023 | static void ir_count_defers(IrBuilderSrc *irb, Scope *inner_scope, Scope *outer_scope, size_t *results) { |
| 4991 | 5024 | results[ReturnKindUnconditional] = 0; |
| 4992 | 5025 | results[ReturnKindError] = 0; |
| ... | ... | @@ -6785,6 +6818,16 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod |
| 6785 | 6818 | IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(irb, scope, node); |
| 6786 | 6819 | return ir_lval_wrap(irb, scope, ir_wasm_memory_size, lval, result_loc); |
| 6787 | 6820 | } |
| 6821 | case BuiltinFnIdWasmMemoryGrow: |
| 6822 | { |
| 6823 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); |
| 6824 | IrInstSrc *arg0_value = ir_gen_node(irb, arg0_node, scope); |
| 6825 | if (arg0_value == irb->codegen->invalid_inst_src) |
| 6826 | return arg0_value; |
| 6827 | |
| 6828 | IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(irb, scope, node, arg0_value); |
| 6829 | return ir_lval_wrap(irb, scope, ir_wasm_memory_grow, lval, result_loc); |
| 6830 | } |
| 6788 | 6831 | case BuiltinFnIdField: |
| 6789 | 6832 | { |
| 6790 | 6833 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); |
| ... | ... | @@ -27683,15 +27726,37 @@ static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasF |
| 27683 | 27726 | } |
| 27684 | 27727 | |
| 27685 | 27728 | static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInstSrcWasmMemorySize *instruction) { |
| 27729 | // TODO generate compile error for target_arch different than 32bit |
| 27686 | 27730 | if (!target_is_wasm(ira->codegen->zig_target)) { |
| 27687 | 27731 | ir_add_error_node(ira, instruction->base.base.source_node, |
| 27688 | | buf_sprintf("@wasmMemorySize is a wasm feature only")); |
| 27732 | buf_sprintf("@wasmMemorySize is a wasm32 feature only")); |
| 27689 | 27733 | return ira->codegen->invalid_inst_gen; |
| 27690 | 27734 | } |
| 27691 | 27735 | |
| 27692 | 27736 | return ir_build_wasm_memory_size_gen(ira, &instruction->base.base); |
| 27693 | 27737 | } |
| 27694 | 27738 | |
| 27739 | static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInstSrcWasmMemoryGrow *instruction) { |
| 27740 | // TODO generate compile error for target_arch different than 32bit |
| 27741 | if (!target_is_wasm(ira->codegen->zig_target)) { |
| 27742 | ir_add_error_node(ira, instruction->base.base.source_node, |
| 27743 | buf_sprintf("@wasmMemoryGrow is a wasm32 feature only")); |
| 27744 | return ira->codegen->invalid_inst_gen; |
| 27745 | } |
| 27746 | |
| 27747 | IrInstGen *delta = instruction->delta->child; |
| 27748 | if (type_is_invalid(delta->value->type)) |
| 27749 | return ira->codegen->invalid_inst_gen; |
| 27750 | |
| 27751 | ZigType *i32_type = ira->codegen->builtin_types.entry_i32; |
| 27752 | |
| 27753 | IrInstGen *casted_delta = ir_implicit_cast(ira, delta, i32_type); |
| 27754 | if (type_is_invalid(casted_delta->value->type)) |
| 27755 | return ira->codegen->invalid_inst_gen; |
| 27756 | |
| 27757 | return ir_build_wasm_memory_grow_gen(ira, &instruction->base.base, casted_delta); |
| 27758 | } |
| 27759 | |
| 27695 | 27760 | static IrInstGen *ir_analyze_instruction_breakpoint(IrAnalyze *ira, IrInstSrcBreakpoint *instruction) { |
| 27696 | 27761 | return ir_build_breakpoint_gen(ira, &instruction->base.base); |
| 27697 | 27762 | } |
| ... | ... | @@ -30935,6 +31000,8 @@ static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruc |
| 30935 | 31000 | return ir_analyze_instruction_spill_end(ira, (IrInstSrcSpillEnd *)instruction); |
| 30936 | 31001 | case IrInstSrcIdWasmMemorySize: |
| 30937 | 31002 | return ir_analyze_instruction_wasm_memory_size(ira, (IrInstSrcWasmMemorySize *)instruction); |
| 31003 | case IrInstSrcIdWasmMemoryGrow: |
| 31004 | return ir_analyze_instruction_wasm_memory_grow(ira, (IrInstSrcWasmMemoryGrow *)instruction); |
| 30938 | 31005 | } |
| 30939 | 31006 | zig_unreachable(); |
| 30940 | 31007 | } |
| ... | ... | @@ -31111,6 +31178,7 @@ bool ir_inst_gen_has_side_effects(IrInstGen *instruction) { |
| 31111 | 31178 | case IrInstGenIdResume: |
| 31112 | 31179 | case IrInstGenIdAwait: |
| 31113 | 31180 | case IrInstGenIdSpillBegin: |
| 31181 | case IrInstGenIdWasmMemoryGrow: |
| 31114 | 31182 | return true; |
| 31115 | 31183 | |
| 31116 | 31184 | case IrInstGenIdPhi: |
| ... | ... | @@ -31243,6 +31311,7 @@ bool ir_inst_src_has_side_effects(IrInstSrc *instruction) { |
| 31243 | 31311 | case IrInstSrcIdResume: |
| 31244 | 31312 | case IrInstSrcIdAwait: |
| 31245 | 31313 | case IrInstSrcIdSpillBegin: |
| 31314 | case IrInstSrcIdWasmMemoryGrow: |
| 31246 | 31315 | return true; |
| 31247 | 31316 | |
| 31248 | 31317 | case IrInstSrcIdPhi: |