authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-07 02:27:38+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-07 02:28:09+02:00
log603798d409a963ccdf5ab2273a6a02ef04d0952b
treef5c1458f0452304b587c9273070572f2271c85ab
parentb686b84ff3ce184094d2bd949f56c7f8271c22f5
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.linux: some corrections to riscv CPU model list

1 files changed, 2 insertions(+), 1 deletions(-)

lib/std/zig/system/linux.zig+2-1
......@@ -71,10 +71,11 @@ const RiscvCpuinfoImpl = struct {
7171
7272 const cpu_names = .{
7373 .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
74 .{ "sifive,bullet0", &Target.riscv.cpu.sifive_u74 },
7475 .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
7576 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
7677 .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
77 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
78 .{ "sifive,u7", &Target.riscv.cpu.sifive_u74 },
7879 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
7980 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
8081 .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },