Commit 664e3e16fa8dd49ff97f78dcdbf4579ff7f652aa | zig

this opens up the door for addition!

2 files changed, 8 insertions(+), 0 deletions(-)

src/arch/riscv64/CodeGen.zig+2

...	...	@@ -942,6 +942,8 @@ fn binOpRegister(
942	942	},
943	943	});
944	944
	945	// generate the struct for OF checks
	946
945	947	return MCValue{ .register = dest_reg };
946	948	}
947	949

src/arch/riscv64/Emit.zig+6

...	...	@@ -177,6 +177,10 @@ fn mirRType(emit: *Emit, inst: Mir.Inst.Index) !void {
177	177	.add => try emit.writeInstruction(Instruction.add(r_type.rd, r_type.rs1, r_type.rs2)),
178	178	.sub => try emit.writeInstruction(Instruction.sub(r_type.rd, r_type.rs1, r_type.rs2)),
179	179	.cmp_gt => try emit.writeInstruction(Instruction.slt(r_type.rd, r_type.rs1, r_type.rs2)),
	180	.cmp_eq => {
	181	try emit.writeInstruction(Instruction.xor(r_type.rd, r_type.rs1, r_type.rs2));
	182	try emit.writeInstruction(Instruction.sltiu(r_type.rd, r_type.rd, 1));
	183	},
180	184	else => unreachable,
181	185	}
182	186	}
...	...	@@ -459,6 +463,8 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
459	463
460	464	.abs => 12, // 3 * 4
461	465
	466	.cmp_eq => 8,
	467
462	468	else => 4,
463	469	};
464	470	}