authorgravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-12 21:15:58+02:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-12 22:02:58+02:00
log6dde769279aaa0cc09d13dd0670b74a8dd24f547
treee02a5e125271242d8255e368898df600004f2dc1
parentce19638cd4690a8ac01a04500fcc525341d0de78
signaturelock-open Commit is signed but in an unrecognized format.

Simplify stores, use sext for signed ints

3 files changed, 59 insertions(+), 20 deletions(-)

src/codegen.cpp+18-4
......@@ -5259,8 +5259,13 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, IrExecutableGen *executable, I
52595259 // operand needs widening and truncating
52605260 ptr_val = LLVMBuildBitCast(g->builder, ptr_val,
52615261 LLVMPointerType(actual_abi_type, 0), "");
5262 cmp_val = LLVMBuildZExt(g->builder, cmp_val, actual_abi_type, "");
5263 new_val = LLVMBuildZExt(g->builder, new_val, actual_abi_type, "");
5262 if (operand_type->data.integral.is_signed) {
5263 cmp_val = LLVMBuildSExt(g->builder, cmp_val, actual_abi_type, "");
5264 new_val = LLVMBuildSExt(g->builder, new_val, actual_abi_type, "");
5265 } else {
5266 cmp_val = LLVMBuildZExt(g->builder, cmp_val, actual_abi_type, "");
5267 new_val = LLVMBuildZExt(g->builder, new_val, actual_abi_type, "");
5268 }
52645269 }
52655270
52665271 LLVMAtomicOrdering success_order = to_LLVMAtomicOrdering(instruction->success_order);
......@@ -5877,7 +5882,12 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, IrExecutableGen *executable
58775882 // operand needs widening and truncating
58785883 LLVMValueRef casted_ptr = LLVMBuildBitCast(g->builder, ptr,
58795884 LLVMPointerType(actual_abi_type, 0), "");
5880 LLVMValueRef casted_operand = LLVMBuildZExt(g->builder, operand, actual_abi_type, "");
5885 LLVMValueRef casted_operand;
5886 if (operand_type->data.integral.is_signed) {
5887 casted_operand = LLVMBuildSExt(g->builder, operand, actual_abi_type, "");
5888 } else {
5889 casted_operand = LLVMBuildZExt(g->builder, operand, actual_abi_type, "");
5890 }
58815891 LLVMValueRef uncasted_result = ZigLLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering,
58825892 g->is_single_threaded);
58835893 return LLVMBuildTrunc(g->builder, uncasted_result, get_llvm_type(g, operand_type), "");
......@@ -5929,7 +5939,11 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, IrExecutableGen *executab
59295939 // operand needs widening
59305940 ptr = LLVMBuildBitCast(g->builder, ptr,
59315941 LLVMPointerType(actual_abi_type, 0), "");
5932 value = LLVMBuildZExt(g->builder, value, actual_abi_type, "");
5942 if (instruction->value->value->type->data.integral.is_signed) {
5943 value = LLVMBuildSExt(g->builder, value, actual_abi_type, "");
5944 } else {
5945 value = LLVMBuildZExt(g->builder, value, actual_abi_type, "");
5946 }
59335947 }
59345948 LLVMValueRef store_inst = gen_store(g, value, ptr, instruction->ptr->value->type);
59355949 LLVMSetOrdering(store_inst, ordering);
src/ir.cpp+39-14
......@@ -25197,10 +25197,16 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
2519725197 ZigType *result_type = get_optional_type(ira->codegen, operand_type);
2519825198
2519925199 // special case zero bit types
25200 if (type_has_one_possible_value(ira->codegen, operand_type) == OnePossibleValueYes) {
25201 IrInstGen *result = ir_const(ira, &instruction->base.base, result_type);
25202 set_optional_value_to_null(result->value);
25203 return result;
25200 switch (type_has_one_possible_value(ira->codegen, operand_type)) {
25201 case OnePossibleValueInvalid:
25202 return ira->codegen->invalid_inst_gen;
25203 case OnePossibleValueYes: {
25204 IrInstGen *result = ir_const(ira, &instruction->base.base, result_type);
25205 set_optional_value_to_null(result->value);
25206 return result;
25207 }
25208 case OnePossibleValueNo:
25209 break;
2520425210 }
2520525211
2520625212 if (instr_is_comptime(casted_ptr) && casted_ptr->value->data.x_ptr.mut != ConstPtrMutRuntimeVar &&
......@@ -28432,8 +28438,13 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2843228438 }
2843328439
2843428440 // special case zero bit types
28435 if (type_has_one_possible_value(ira->codegen, operand_type) == OnePossibleValueYes) {
28436 return ir_const_move(ira, &instruction->base.base, get_the_one_possible_value(ira->codegen, operand_type));
28441 switch (type_has_one_possible_value(ira->codegen, operand_type)) {
28442 case OnePossibleValueInvalid:
28443 return ira->codegen->invalid_inst_gen;
28444 case OnePossibleValueYes:
28445 return ir_const_move(ira, &instruction->base.base, get_the_one_possible_value(ira->codegen, operand_type));
28446 case OnePossibleValueNo:
28447 break;
2843728448 }
2843828449
2843928450 IrInst *source_inst = &instruction->base.base;
......@@ -28450,9 +28461,11 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2845028461 if (op2_val == nullptr)
2845128462 return ira->codegen->invalid_inst_gen;
2845228463
28464 IrInstGen *result = ir_const(ira, source_inst, operand_type);
28465 copy_const_val(ira->codegen, result->value, op1_val);
2845328466 if (op == AtomicRmwOp_xchg) {
28454 ir_analyze_store_ptr(ira, source_inst, casted_ptr, casted_operand, false);
28455 return ir_const_move(ira, source_inst, op1_val);
28467 copy_const_val(ira->codegen, op1_val, op2_val);
28468 return result;
2845628469 }
2845728470
2845828471 if (operand_type->id == ZigTypeIdPointer || operand_type->id == ZigTypeIdOptional) {
......@@ -28461,6 +28474,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2846128474 return ira->codegen->invalid_inst_gen;
2846228475 }
2846328476
28477 ErrorMsg *msg;
2846428478 if (op == AtomicRmwOp_min || op == AtomicRmwOp_max) {
2846528479 IrBinOp bin_op;
2846628480 if (op == AtomicRmwOp_min)
......@@ -28471,9 +28485,12 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2847128485 bin_op = IrBinOpCmpLessThan;
2847228486
2847328487 IrInstGen *dummy_value = ir_const(ira, source_inst, operand_type);
28474 ir_eval_bin_op_cmp_scalar(ira, source_inst, op1_val, bin_op, op2_val, dummy_value->value);
28488 msg = ir_eval_bin_op_cmp_scalar(ira, source_inst, op1_val, bin_op, op2_val, dummy_value->value);
28489 if (msg != nullptr) {
28490 return ira->codegen->invalid_inst_gen;
28491 }
2847528492 if (dummy_value->value->data.x_bool)
28476 ir_analyze_store_ptr(ira, source_inst, casted_ptr, casted_operand, false);
28493 copy_const_val(ira->codegen, op1_val, op2_val);
2847728494 } else {
2847828495 IrBinOp bin_op;
2847928496 switch (op) {
......@@ -28504,13 +28521,16 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2850428521 bin_op = IrBinOpBinXor;
2850528522 break;
2850628523 }
28507 ir_eval_math_op_scalar(ira, source_inst, operand_type, op1_val, bin_op, op2_val, op1_val);
28524 msg = ir_eval_math_op_scalar(ira, source_inst, operand_type, op1_val, bin_op, op2_val, op1_val);
28525 if (msg != nullptr) {
28526 return ira->codegen->invalid_inst_gen;
28527 }
2850828528 if (op == AtomicRmwOp_nand) {
2850928529 bigint_not(&op1_val->data.x_bigint, &op1_val->data.x_bigint,
2851028530 operand_type->data.integral.bit_count, operand_type->data.integral.is_signed);
2851128531 }
2851228532 }
28513 return ir_const_move(ira, source_inst, op1_val);
28533 return result;
2851428534 }
2851528535
2851628536 return ir_build_atomic_rmw_gen(ira, source_inst, casted_ptr, casted_operand, op,
......@@ -28586,8 +28606,13 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA
2858628606 }
2858728607
2858828608 // special case zero bit types
28589 if (type_has_one_possible_value(ira->codegen, operand_type) == OnePossibleValueYes) {
28590 return ir_const_void(ira, &instruction->base.base);
28609 switch (type_has_one_possible_value(ira->codegen, operand_type)) {
28610 case OnePossibleValueInvalid:
28611 return ira->codegen->invalid_inst_gen;
28612 case OnePossibleValueYes:
28613 return ir_const_void(ira, &instruction->base.base);
28614 case OnePossibleValueNo:
28615 break;
2859128616 }
2859228617
2859328618 if (instr_is_comptime(casted_value) && instr_is_comptime(casted_ptr)) {
test/stage1/behavior/atomics.zig+2-2
......@@ -175,8 +175,8 @@ test "atomicrmw with ints" {
175175
176176fn testAtomicRmwInt() void {
177177 var x: u8 = 1;
178 _ = @atomicRmw(u8, &x, .Xchg, 3, .SeqCst);
179 expect(x == 3);
178 var res = @atomicRmw(u8, &x, .Xchg, 3, .SeqCst);
179 expect(x == 3 and res == 1);
180180 _ = @atomicRmw(u8, &x, .Add, 3, .SeqCst);
181181 expect(x == 6);
182182 _ = @atomicRmw(u8, &x, .Sub, 1, .SeqCst);