authorgravatar for xtex@astrafall.orgxtex <xtex@astrafall.org> 2026-08-07 15:04:16+08:00
committergravatar for xtex@astrafall.orgxtex <xtex@astrafall.org> 2026-08-08 10:53:46+08:00
log709154ffb87790ef1537f7929df731e70b54f367
tree96bcbc10118b8287a5d8747f78a764d187338dc1
parent0fe189415864329769ae5967d504c0574fe41060
signaturebadge-check Signed by SSH key SHA256:IEYEjkZlkUTr5U9GiDAmZU/4eZus2t2RsxusyhQqwao

loongarch: add generated encoding data

Generated with tools/gen_loongarch_encoding.zig, using loongarch-opcodes version 878c9a2366d1 (Merge pull request #7 from ksco/develop, 2026-03-06) Signed-off-by: xtex <xtex@astrafall.org>

3 files changed, 27571 insertions(+), 0 deletions(-)

src/codegen/loongarch/decode_tree.zon created+2817
...@@ -0,0 +1,2817 @@
1// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig.
2.{ .mask = 0xfc000000, .cases = .{
3 .{ .value = 0x00000000, .then = .{ .mask = 0x03c00000, .cases = .{
4 .{ .value = 0x00000000, .then = .{ .mask = 0x003c0000, .cases = .{
5 .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{
6 .{ .value = 0x00000000, .then = .{ .instruction = .@"adc.b" } },
7 .{ .value = 0x00018000, .then = .{ .instruction = .@"adc.d" } },
8 .{ .value = 0x00008000, .then = .{ .instruction = .@"adc.h" } },
9 .{ .value = 0x00010000, .then = .{ .instruction = .@"adc.w" } },
10 .{ .value = 0x00020000, .then = .{ .instruction = .@"sbc.b" } },
11 .{ .value = 0x00038000, .then = .{ .instruction = .@"sbc.d" } },
12 .{ .value = 0x00028000, .then = .{ .instruction = .@"sbc.h" } },
13 .{ .value = 0x00030000, .then = .{ .instruction = .@"sbc.w" } },
14 } } },
15 .{ .value = 0x00100000, .then = .{ .mask = 0x00038000, .cases = .{
16 .{ .value = 0x00008000, .then = .{ .instruction = .@"add.d" } },
17 .{ .value = 0x00000000, .then = .{ .instruction = .@"add.w" } },
18 .{ .value = 0x00030000, .then = .{ .instruction = .maskeqz } },
19 .{ .value = 0x00038000, .then = .{ .instruction = .masknez } },
20 .{ .value = 0x00020000, .then = .{ .instruction = .slt } },
21 .{ .value = 0x00028000, .then = .{ .instruction = .sltu } },
22 .{ .value = 0x00018000, .then = .{ .instruction = .@"sub.d" } },
23 .{ .value = 0x00010000, .then = .{ .instruction = .@"sub.w" } },
24 } } },
25 .{ .value = 0x00280000, .then = .{ .mask = 0x00038000, .cases = .{
26 .{ .value = 0x00018000, .then = .{ .instruction = .@"addu12i.d" } },
27 .{ .value = 0x00010000, .then = .{ .instruction = .@"addu12i.w" } },
28 .{ .value = 0x00020000, .then = .{ .instruction = .@"break" } },
29 .{ .value = 0x00028000, .then = .{ .instruction = .dbgcall } },
30 .{ .value = 0x00038000, .then = .{ .instruction = .hypcall } },
31 .{ .value = 0x00030000, .then = .{ .instruction = .syscall } },
32 } } },
33 .{ .value = 0x00140000, .then = .{ .mask = 0x00038000, .cases = .{
34 .{ .value = 0x00008000, .then = .{ .instruction = .@"and" } },
35 .{ .value = 0x00028000, .then = .{ .instruction = .andn } },
36 .{ .value = 0x00000000, .then = .{ .instruction = .nor } },
37 .{ .value = 0x00010000, .then = .{ .instruction = .@"or" } },
38 .{ .value = 0x00020000, .then = .{ .instruction = .orn } },
39 .{ .value = 0x00030000, .then = .{ .instruction = .@"sll.w" } },
40 .{ .value = 0x00038000, .then = .{ .instruction = .@"srl.w" } },
41 .{ .value = 0x00018000, .then = .{ .instruction = .xor } },
42 } } },
43 .{ .value = 0x00380000, .then = .{ .mask = 0x00038010, .cases = .{
44 .{ .value = 0x00000010, .then = .{ .instruction = .@"armadc.w" } },
45 .{ .value = 0x00010010, .then = .{ .instruction = .@"armand.w" } },
46 .{ .value = 0x00018010, .then = .{ .instruction = .@"armor.w" } },
47 .{ .value = 0x00008010, .then = .{ .instruction = .@"armsbc.w" } },
48 .{ .value = 0x00028010, .then = .{ .instruction = .@"armsll.w" } },
49 .{ .value = 0x00038010, .then = .{ .instruction = .@"armsra.w" } },
50 .{ .value = 0x00030010, .then = .{ .instruction = .@"armsrl.w" } },
51 .{ .value = 0x00020010, .then = .{ .instruction = .@"armxor.w" } },
52 } } },
53 .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{
54 .{ .value = 0x00030000, .then = .{ .instruction = .@"armadd.w" } },
55 .{ .value = 0x00020000, .then = .{ .instruction = .armmove } },
56 .{ .value = 0x00028000, .then = .{ .mask = 0x000043e0, .cases = .{
57 .{ .value = 0x00004000, .then = .{ .instruction = .armsetj } },
58 .{ .value = 0x00000000, .then = .{ .instruction = .x86setj } },
59 } } },
60 .{ .value = 0x00038000, .then = .{ .instruction = .@"armsub.w" } },
61 .{ .value = 0x00000000, .then = .{ .instruction = .@"rcr.b" } },
62 .{ .value = 0x00018000, .then = .{ .instruction = .@"rcr.d" } },
63 .{ .value = 0x00008000, .then = .{ .instruction = .@"rcr.h" } },
64 .{ .value = 0x00010000, .then = .{ .instruction = .@"rcr.w" } },
65 } } },
66 .{ .value = 0x003c0000, .then = .{ .mask = 0x00038010, .cases = .{
67 .{ .value = 0x00038010, .then = .{ .mask = 0x0000000f, .cases = .{
68 .{ .value = 0x0000000e, .then = .{ .instruction = .@"armmov.d" } },
69 .{ .value = 0x0000000d, .then = .{ .instruction = .@"armmov.w" } },
70 .{ .value = 0x0000000c, .then = .{ .instruction = .@"armnot.w" } },
71 .{ .value = 0x0000000f, .then = .{ .instruction = .@"armrrx.w" } },
72 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86and.b" } },
73 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86and.d" } },
74 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86and.h" } },
75 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86and.w" } },
76 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86or.b" } },
77 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86or.d" } },
78 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86or.h" } },
79 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86or.w" } },
80 .{ .value = 0x00000008, .then = .{ .instruction = .@"x86xor.b" } },
81 .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86xor.d" } },
82 .{ .value = 0x00000009, .then = .{ .instruction = .@"x86xor.h" } },
83 .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86xor.w" } },
84 } } },
85 .{ .value = 0x00000010, .then = .{ .instruction = .@"armrotr.w" } },
86 .{ .value = 0x00020010, .then = .{ .instruction = .@"armrotri.w" } },
87 .{ .value = 0x00008010, .then = .{ .instruction = .@"armslli.w" } },
88 .{ .value = 0x00018010, .then = .{ .instruction = .@"armsrai.w" } },
89 .{ .value = 0x00010010, .then = .{ .instruction = .@"armsrli.w" } },
90 .{ .value = 0x00030000, .then = .{ .mask = 0x0000000f, .cases = .{
91 .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86adc.b" } },
92 .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86adc.d" } },
93 .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86adc.h" } },
94 .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86adc.w" } },
95 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86add.b" } },
96 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86add.d" } },
97 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86add.du" } },
98 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86add.h" } },
99 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86add.w" } },
100 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86add.wu" } },
101 .{ .value = 0x00000008, .then = .{ .instruction = .@"x86sub.b" } },
102 .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86sub.d" } },
103 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sub.du" } },
104 .{ .value = 0x00000009, .then = .{ .instruction = .@"x86sub.h" } },
105 .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86sub.w" } },
106 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sub.wu" } },
107 } } },
108 .{ .value = 0x00028000, .then = .{ .mask = 0x0000000f, .cases = .{
109 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86mul.b" } },
110 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86mul.bu" } },
111 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86mul.d" } },
112 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86mul.du" } },
113 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86mul.h" } },
114 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86mul.hu" } },
115 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86mul.w" } },
116 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86mul.wu" } },
117 } } },
118 .{ .value = 0x00038000, .then = .{ .mask = 0x0000000f, .cases = .{
119 .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rcl.b" } },
120 .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86rcl.d" } },
121 .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rcl.h" } },
122 .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rcl.w" } },
123 .{ .value = 0x00000008, .then = .{ .instruction = .@"x86rcr.b" } },
124 .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86rcr.d" } },
125 .{ .value = 0x00000009, .then = .{ .instruction = .@"x86rcr.h" } },
126 .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86rcr.w" } },
127 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86rotl.b" } },
128 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86rotl.d" } },
129 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86rotl.h" } },
130 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86rotl.w" } },
131 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86rotr.b" } },
132 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86rotr.d" } },
133 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86rotr.h" } },
134 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86rotr.w" } },
135 } } },
136 .{ .value = 0x00030010, .then = .{ .mask = 0x0000000f, .cases = .{
137 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86sbc.b" } },
138 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sbc.d" } },
139 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86sbc.h" } },
140 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sbc.w" } },
141 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86sll.b" } },
142 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86sll.d" } },
143 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86sll.h" } },
144 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86sll.w" } },
145 .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86sra.b" } },
146 .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86sra.d" } },
147 .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86sra.h" } },
148 .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86sra.w" } },
149 .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srl.b" } },
150 .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86srl.d" } },
151 .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srl.h" } },
152 .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srl.w" } },
153 } } },
154 } } },
155 .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{
156 .{ .value = 0x00018000, .then = .{ .instruction = .asrtgt } },
157 .{ .value = 0x00010000, .then = .{ .instruction = .asrtle } },
158 .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{
159 .{ .value = 0x00002000, .then = .{ .instruction = .@"clo.d" } },
160 .{ .value = 0x00001000, .then = .{ .instruction = .@"clo.w" } },
161 .{ .value = 0x00002400, .then = .{ .instruction = .@"clz.d" } },
162 .{ .value = 0x00001400, .then = .{ .instruction = .@"clz.w" } },
163 .{ .value = 0x00006c00, .then = .{ .instruction = .cpucfg } },
164 .{ .value = 0x00002800, .then = .{ .instruction = .@"cto.d" } },
165 .{ .value = 0x00001800, .then = .{ .instruction = .@"cto.w" } },
166 .{ .value = 0x00002c00, .then = .{ .instruction = .@"ctz.d" } },
167 .{ .value = 0x00001c00, .then = .{ .instruction = .@"ctz.w" } },
168 .{ .value = 0x00000800, .then = .{ .instruction = .movgr2scr } },
169 .{ .value = 0x00000c00, .then = .{ .instruction = .movscr2gr } },
170 .{ .value = 0x00006800, .then = .{ .instruction = .@"rdtime.d" } },
171 .{ .value = 0x00006400, .then = .{ .instruction = .@"rdtimeh.w" } },
172 .{ .value = 0x00006000, .then = .{ .instruction = .@"rdtimel.w" } },
173 .{ .value = 0x00003000, .then = .{ .instruction = .@"revb.2h" } },
174 .{ .value = 0x00003800, .then = .{ .instruction = .@"revb.2w" } },
175 .{ .value = 0x00003400, .then = .{ .instruction = .@"revb.4h" } },
176 .{ .value = 0x00003c00, .then = .{ .instruction = .@"revb.d" } },
177 .{ .value = 0x00004800, .then = .{ .instruction = .@"revbit.4b" } },
178 .{ .value = 0x00004c00, .then = .{ .instruction = .@"revbit.8b" } },
179 .{ .value = 0x00005400, .then = .{ .instruction = .@"revbit.d" } },
180 .{ .value = 0x00005000, .then = .{ .instruction = .@"revbit.w" } },
181 .{ .value = 0x00004000, .then = .{ .instruction = .@"revh.2w" } },
182 .{ .value = 0x00004400, .then = .{ .instruction = .@"revh.d" } },
183 .{ .value = 0x00005c00, .then = .{ .instruction = .@"sext.b" } },
184 .{ .value = 0x00005800, .then = .{ .instruction = .@"sext.h" } },
185 .{ .value = 0x00007400, .then = .{ .instruction = .x86mftop } },
186 .{ .value = 0x00007000, .then = .{ .instruction = .x86mttop } },
187 .{ .value = 0x00007800, .then = .{ .instruction = .x86setloope } },
188 .{ .value = 0x00007c00, .then = .{ .instruction = .x86setloopne } },
189 } } },
190 .{ .value = 0x00008000, .then = .{ .mask = 0x00007c1f, .cases = .{
191 .{ .value = 0x00000008, .then = .{ .mask = 0x000003e0, .cases = .{
192 .{ .value = 0x00000020, .then = .{ .instruction = .x86clrtm } },
193 .{ .value = 0x00000000, .then = .{ .instruction = .x86settm } },
194 } } },
195 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86dec.b" } },
196 .{ .value = 0x00000007, .then = .{ .instruction = .@"x86dec.d" } },
197 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86dec.h" } },
198 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86dec.w" } },
199 .{ .value = 0x00000009, .then = .{ .mask = 0x000003e0, .cases = .{
200 .{ .value = 0x00000020, .then = .{ .instruction = .x86dectop } },
201 .{ .value = 0x00000000, .then = .{ .instruction = .x86inctop } },
202 } } },
203 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86inc.b" } },
204 .{ .value = 0x00000003, .then = .{ .instruction = .@"x86inc.d" } },
205 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86inc.h" } },
206 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86inc.w" } },
207 } } },
208 } } },
209 .{ .value = 0x000c0000, .then = .{ .instruction = .@"catpick.d" } },
210 .{ .value = 0x00080000, .then = .{ .instruction = .@"catpick.w" } },
211 .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{
212 .{ .value = 0x00000000, .then = .{ .instruction = .@"crc.w.b.w" } },
213 .{ .value = 0x00018000, .then = .{ .instruction = .@"crc.w.d.w" } },
214 .{ .value = 0x00008000, .then = .{ .instruction = .@"crc.w.h.w" } },
215 .{ .value = 0x00010000, .then = .{ .instruction = .@"crc.w.w.w" } },
216 .{ .value = 0x00020000, .then = .{ .instruction = .@"crcc.w.b.w" } },
217 .{ .value = 0x00038000, .then = .{ .instruction = .@"crcc.w.d.w" } },
218 .{ .value = 0x00028000, .then = .{ .instruction = .@"crcc.w.h.w" } },
219 .{ .value = 0x00030000, .then = .{ .instruction = .@"crcc.w.w.w" } },
220 } } },
221 .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{
222 .{ .value = 0x00020000, .then = .{ .instruction = .@"div.d" } },
223 .{ .value = 0x00030000, .then = .{ .instruction = .@"div.du" } },
224 .{ .value = 0x00000000, .then = .{ .instruction = .@"div.w" } },
225 .{ .value = 0x00010000, .then = .{ .instruction = .@"div.wu" } },
226 .{ .value = 0x00028000, .then = .{ .instruction = .@"mod.d" } },
227 .{ .value = 0x00038000, .then = .{ .instruction = .@"mod.du" } },
228 .{ .value = 0x00008000, .then = .{ .instruction = .@"mod.w" } },
229 .{ .value = 0x00018000, .then = .{ .instruction = .@"mod.wu" } },
230 } } },
231 .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{
232 .{ .value = 0x00018000, .then = .{ .instruction = .@"mul.d" } },
233 .{ .value = 0x00000000, .then = .{ .instruction = .@"mul.w" } },
234 .{ .value = 0x00020000, .then = .{ .instruction = .@"mulh.d" } },
235 .{ .value = 0x00028000, .then = .{ .instruction = .@"mulh.du" } },
236 .{ .value = 0x00008000, .then = .{ .instruction = .@"mulh.w" } },
237 .{ .value = 0x00010000, .then = .{ .instruction = .@"mulh.wu" } },
238 .{ .value = 0x00030000, .then = .{ .instruction = .@"mulw.d.w" } },
239 .{ .value = 0x00038000, .then = .{ .instruction = .@"mulw.d.wu" } },
240 } } },
241 .{ .value = 0x00180000, .then = .{ .mask = 0x00038000, .cases = .{
242 .{ .value = 0x00020000, .then = .{ .instruction = .@"rotr.b" } },
243 .{ .value = 0x00038000, .then = .{ .instruction = .@"rotr.d" } },
244 .{ .value = 0x00028000, .then = .{ .instruction = .@"rotr.h" } },
245 .{ .value = 0x00030000, .then = .{ .instruction = .@"rotr.w" } },
246 .{ .value = 0x00008000, .then = .{ .instruction = .@"sll.d" } },
247 .{ .value = 0x00018000, .then = .{ .instruction = .@"sra.d" } },
248 .{ .value = 0x00000000, .then = .{ .instruction = .@"sra.w" } },
249 .{ .value = 0x00010000, .then = .{ .instruction = .@"srl.d" } },
250 } } },
251 .{ .value = 0x002c0000, .then = .{ .instruction = .@"sladd.d" } },
252 .{ .value = 0x00040000, .then = .{ .mask = 0x00020000, .cases = .{
253 .{ .value = 0x00000000, .then = .{ .instruction = .@"sladd.w" } },
254 .{ .value = 0x00020000, .then = .{ .instruction = .@"sladd.wu" } },
255 } } },
256 } } },
257 .{ .value = 0x02c00000, .then = .{ .instruction = .@"addi.d" } },
258 .{ .value = 0x02800000, .then = .{ .instruction = .@"addi.w" } },
259 .{ .value = 0x03400000, .then = .{ .instruction = .andi } },
260 .{ .value = 0x00400000, .then = .{ .mask = 0x00200000, .cases = .{
261 .{ .value = 0x00000000, .then = .{ .mask = 0x001c0000, .cases = .{
262 .{ .value = 0x001c0000, .then = .{ .mask = 0x000003e0, .cases = .{
263 .{ .value = 0x00000040, .then = .{ .instruction = .armmfflag } },
264 .{ .value = 0x00000060, .then = .{ .instruction = .armmtflag } },
265 .{ .value = 0x00000000, .then = .{ .instruction = .x86mfflag } },
266 .{ .value = 0x00000020, .then = .{ .instruction = .x86mtflag } },
267 } } },
268 .{ .value = 0x00100000, .then = .{ .mask = 0x00030000, .cases = .{
269 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
270 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
271 .{ .value = 0x00000000, .then = .{ .instruction = .@"rcri.b" } },
272 .{ .value = 0x00004000, .then = .{ .instruction = .@"rcri.h" } },
273 } } },
274 .{ .value = 0x00008000, .then = .{ .instruction = .@"rcri.w" } },
275 } } },
276 .{ .value = 0x00010000, .then = .{ .instruction = .@"rcri.d" } },
277 } } },
278 .{ .value = 0x000c0000, .then = .{ .mask = 0x00030000, .cases = .{
279 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
280 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
281 .{ .value = 0x00000000, .then = .{ .instruction = .@"rotri.b" } },
282 .{ .value = 0x00004000, .then = .{ .instruction = .@"rotri.h" } },
283 } } },
284 .{ .value = 0x00008000, .then = .{ .instruction = .@"rotri.w" } },
285 } } },
286 .{ .value = 0x00010000, .then = .{ .instruction = .@"rotri.d" } },
287 } } },
288 .{ .value = 0x00000000, .then = .{ .mask = 0x00030000, .cases = .{
289 .{ .value = 0x00010000, .then = .{ .instruction = .@"slli.d" } },
290 .{ .value = 0x00000000, .then = .{ .instruction = .@"slli.w" } },
291 } } },
292 .{ .value = 0x00080000, .then = .{ .mask = 0x00030000, .cases = .{
293 .{ .value = 0x00010000, .then = .{ .instruction = .@"srai.d" } },
294 .{ .value = 0x00000000, .then = .{ .instruction = .@"srai.w" } },
295 } } },
296 .{ .value = 0x00040000, .then = .{ .mask = 0x00030000, .cases = .{
297 .{ .value = 0x00010000, .then = .{ .instruction = .@"srli.d" } },
298 .{ .value = 0x00000000, .then = .{ .instruction = .@"srli.w" } },
299 } } },
300 .{ .value = 0x00140000, .then = .{ .mask = 0x0003001f, .cases = .{
301 .{ .value = 0x00000018, .then = .{ .instruction = .@"x86rcli.b" } },
302 .{ .value = 0x0001001b, .then = .{ .instruction = .@"x86rcli.d" } },
303 .{ .value = 0x00000019, .then = .{ .instruction = .@"x86rcli.h" } },
304 .{ .value = 0x0000001a, .then = .{ .instruction = .@"x86rcli.w" } },
305 .{ .value = 0x00000010, .then = .{ .instruction = .@"x86rcri.b" } },
306 .{ .value = 0x00010013, .then = .{ .instruction = .@"x86rcri.d" } },
307 .{ .value = 0x00000011, .then = .{ .instruction = .@"x86rcri.h" } },
308 .{ .value = 0x00000012, .then = .{ .instruction = .@"x86rcri.w" } },
309 .{ .value = 0x00000014, .then = .{ .instruction = .@"x86rotli.b" } },
310 .{ .value = 0x00010017, .then = .{ .instruction = .@"x86rotli.d" } },
311 .{ .value = 0x00000015, .then = .{ .instruction = .@"x86rotli.h" } },
312 .{ .value = 0x00000016, .then = .{ .instruction = .@"x86rotli.w" } },
313 .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rotri.b" } },
314 .{ .value = 0x0001000f, .then = .{ .instruction = .@"x86rotri.d" } },
315 .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rotri.h" } },
316 .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rotri.w" } },
317 .{ .value = 0x00000000, .then = .{ .instruction = .@"x86slli.b" } },
318 .{ .value = 0x00010003, .then = .{ .instruction = .@"x86slli.d" } },
319 .{ .value = 0x00000001, .then = .{ .instruction = .@"x86slli.h" } },
320 .{ .value = 0x00000002, .then = .{ .instruction = .@"x86slli.w" } },
321 .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srai.b" } },
322 .{ .value = 0x0001000b, .then = .{ .instruction = .@"x86srai.d" } },
323 .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srai.h" } },
324 .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srai.w" } },
325 .{ .value = 0x00000004, .then = .{ .instruction = .@"x86srli.b" } },
326 .{ .value = 0x00010007, .then = .{ .instruction = .@"x86srli.d" } },
327 .{ .value = 0x00000005, .then = .{ .instruction = .@"x86srli.h" } },
328 .{ .value = 0x00000006, .then = .{ .instruction = .@"x86srli.w" } },
329 } } },
330 .{ .value = 0x00180000, .then = .{ .instruction = .x86settag } },
331 } } },
332 .{ .value = 0x00200000, .then = .{ .mask = 0x00008000, .cases = .{
333 .{ .value = 0x00000000, .then = .{ .instruction = .@"bstrins.w" } },
334 .{ .value = 0x00008000, .then = .{ .instruction = .@"bstrpick.w" } },
335 } } },
336 } } },
337 .{ .value = 0x00800000, .then = .{ .instruction = .@"bstrins.d" } },
338 .{ .value = 0x00c00000, .then = .{ .instruction = .@"bstrpick.d" } },
339 .{ .value = 0x03000000, .then = .{ .instruction = .@"cu52i.d" } },
340 .{ .value = 0x01000000, .then = .{ .mask = 0x003f8000, .cases = .{
341 .{ .value = 0x00140000, .then = .{ .mask = 0x00007c00, .cases = .{
342 .{ .value = 0x00000800, .then = .{ .instruction = .@"fabs.d" } },
343 .{ .value = 0x00000400, .then = .{ .instruction = .@"fabs.s" } },
344 .{ .value = 0x00003800, .then = .{ .instruction = .@"fclass.d" } },
345 .{ .value = 0x00003400, .then = .{ .instruction = .@"fclass.s" } },
346 .{ .value = 0x00002800, .then = .{ .instruction = .@"flogb.d" } },
347 .{ .value = 0x00002400, .then = .{ .instruction = .@"flogb.s" } },
348 .{ .value = 0x00001800, .then = .{ .instruction = .@"fneg.d" } },
349 .{ .value = 0x00001400, .then = .{ .instruction = .@"fneg.s" } },
350 .{ .value = 0x00005800, .then = .{ .instruction = .@"frecip.d" } },
351 .{ .value = 0x00005400, .then = .{ .instruction = .@"frecip.s" } },
352 .{ .value = 0x00007800, .then = .{ .instruction = .@"frecipe.d" } },
353 .{ .value = 0x00007400, .then = .{ .instruction = .@"frecipe.s" } },
354 .{ .value = 0x00006800, .then = .{ .instruction = .@"frsqrt.d" } },
355 .{ .value = 0x00006400, .then = .{ .instruction = .@"frsqrt.s" } },
356 .{ .value = 0x00004800, .then = .{ .instruction = .@"fsqrt.d" } },
357 .{ .value = 0x00004400, .then = .{ .instruction = .@"fsqrt.s" } },
358 } } },
359 .{ .value = 0x00010000, .then = .{ .instruction = .@"fadd.d" } },
360 .{ .value = 0x00008000, .then = .{ .instruction = .@"fadd.s" } },
361 .{ .value = 0x00130000, .then = .{ .instruction = .@"fcopysign.d" } },
362 .{ .value = 0x00128000, .then = .{ .instruction = .@"fcopysign.s" } },
363 .{ .value = 0x00148000, .then = .{ .mask = 0x00007c00, .cases = .{
364 .{ .value = 0x00004800, .then = .{ .instruction = .fcsrrd } },
365 .{ .value = 0x00004000, .then = .{ .instruction = .fcsrwr } },
366 .{ .value = 0x00006000, .then = .{ .instruction = .@"fcvt.ld.d" } },
367 .{ .value = 0x00006400, .then = .{ .instruction = .@"fcvt.ud.d" } },
368 .{ .value = 0x00001800, .then = .{ .instruction = .@"fmov.d" } },
369 .{ .value = 0x00001400, .then = .{ .instruction = .@"fmov.s" } },
370 .{ .value = 0x00000800, .then = .{ .instruction = .@"frsqrte.d" } },
371 .{ .value = 0x00000400, .then = .{ .instruction = .@"frsqrte.s" } },
372 .{ .value = 0x00005400, .then = .{ .instruction = .movfcc2fr } },
373 .{ .value = 0x00005c00, .then = .{ .instruction = .movfcc2gr } },
374 .{ .value = 0x00005000, .then = .{ .instruction = .movfr2fcc } },
375 .{ .value = 0x00003800, .then = .{ .instruction = .@"movfr2gr.d" } },
376 .{ .value = 0x00003400, .then = .{ .instruction = .@"movfr2gr.s" } },
377 .{ .value = 0x00003c00, .then = .{ .instruction = .@"movfrh2gr.s" } },
378 .{ .value = 0x00005800, .then = .{ .instruction = .movgr2fcc } },
379 .{ .value = 0x00002800, .then = .{ .instruction = .@"movgr2fr.d" } },
380 .{ .value = 0x00002400, .then = .{ .instruction = .@"movgr2fr.w" } },
381 .{ .value = 0x00002c00, .then = .{ .instruction = .@"movgr2frh.w" } },
382 } } },
383 .{ .value = 0x00150000, .then = .{ .instruction = .@"fcvt.d.ld" } },
384 .{ .value = 0x00190000, .then = .{ .mask = 0x00007c00, .cases = .{
385 .{ .value = 0x00002400, .then = .{ .instruction = .@"fcvt.d.s" } },
386 .{ .value = 0x00001800, .then = .{ .instruction = .@"fcvt.s.d" } },
387 } } },
388 .{ .value = 0x00070000, .then = .{ .instruction = .@"fdiv.d" } },
389 .{ .value = 0x00068000, .then = .{ .instruction = .@"fdiv.s" } },
390 .{ .value = 0x001d0000, .then = .{ .mask = 0x00007c00, .cases = .{
391 .{ .value = 0x00002800, .then = .{ .instruction = .@"ffint.d.l" } },
392 .{ .value = 0x00002000, .then = .{ .instruction = .@"ffint.d.w" } },
393 .{ .value = 0x00001800, .then = .{ .instruction = .@"ffint.s.l" } },
394 .{ .value = 0x00001000, .then = .{ .instruction = .@"ffint.s.w" } },
395 } } },
396 .{ .value = 0x00090000, .then = .{ .instruction = .@"fmax.d" } },
397 .{ .value = 0x00088000, .then = .{ .instruction = .@"fmax.s" } },
398 .{ .value = 0x000d0000, .then = .{ .instruction = .@"fmaxa.d" } },
399 .{ .value = 0x000c8000, .then = .{ .instruction = .@"fmaxa.s" } },
400 .{ .value = 0x000b0000, .then = .{ .instruction = .@"fmin.d" } },
401 .{ .value = 0x000a8000, .then = .{ .instruction = .@"fmin.s" } },
402 .{ .value = 0x000f0000, .then = .{ .instruction = .@"fmina.d" } },
403 .{ .value = 0x000e8000, .then = .{ .instruction = .@"fmina.s" } },
404 .{ .value = 0x00050000, .then = .{ .instruction = .@"fmul.d" } },
405 .{ .value = 0x00048000, .then = .{ .instruction = .@"fmul.s" } },
406 .{ .value = 0x001e0000, .then = .{ .mask = 0x00007c00, .cases = .{
407 .{ .value = 0x00004800, .then = .{ .instruction = .@"frint.d" } },
408 .{ .value = 0x00004400, .then = .{ .instruction = .@"frint.s" } },
409 } } },
410 .{ .value = 0x00110000, .then = .{ .instruction = .@"fscaleb.d" } },
411 .{ .value = 0x00108000, .then = .{ .instruction = .@"fscaleb.s" } },
412 .{ .value = 0x00030000, .then = .{ .instruction = .@"fsub.d" } },
413 .{ .value = 0x00028000, .then = .{ .instruction = .@"fsub.s" } },
414 .{ .value = 0x001b0000, .then = .{ .mask = 0x00007c00, .cases = .{
415 .{ .value = 0x00002800, .then = .{ .instruction = .@"ftint.l.d" } },
416 .{ .value = 0x00002400, .then = .{ .instruction = .@"ftint.l.s" } },
417 .{ .value = 0x00000800, .then = .{ .instruction = .@"ftint.w.d" } },
418 .{ .value = 0x00000400, .then = .{ .instruction = .@"ftint.w.s" } },
419 } } },
420 .{ .value = 0x001a0000, .then = .{ .mask = 0x00007c00, .cases = .{
421 .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrm.l.d" } },
422 .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrm.l.s" } },
423 .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrm.w.d" } },
424 .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrm.w.s" } },
425 .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrp.l.d" } },
426 .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrp.l.s" } },
427 .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrp.w.d" } },
428 .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrp.w.s" } },
429 } } },
430 .{ .value = 0x001a8000, .then = .{ .mask = 0x00007c00, .cases = .{
431 .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrne.l.d" } },
432 .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrne.l.s" } },
433 .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrne.w.d" } },
434 .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrne.w.s" } },
435 .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrz.l.d" } },
436 .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrz.l.s" } },
437 .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrz.w.d" } },
438 .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrz.w.s" } },
439 } } },
440 } } },
441 .{ .value = 0x03800000, .then = .{ .instruction = .ori } },
442 .{ .value = 0x02000000, .then = .{ .instruction = .slti } },
443 .{ .value = 0x02400000, .then = .{ .instruction = .sltui } },
444 .{ .value = 0x03c00000, .then = .{ .instruction = .xori } },
445 } } },
446 .{ .value = 0x10000000, .then = .{ .instruction = .@"addu16i.d" } },
447 .{ .value = 0x38000000, .then = .{ .mask = 0x03ff8000, .cases = .{
448 .{ .value = 0x005d0000, .then = .{ .instruction = .@"amadd.b" } },
449 .{ .value = 0x00618000, .then = .{ .instruction = .@"amadd.d" } },
450 .{ .value = 0x005d8000, .then = .{ .instruction = .@"amadd.h" } },
451 .{ .value = 0x00610000, .then = .{ .instruction = .@"amadd.w" } },
452 .{ .value = 0x005f0000, .then = .{ .instruction = .@"amadd_db.b" } },
453 .{ .value = 0x006a8000, .then = .{ .instruction = .@"amadd_db.d" } },
454 .{ .value = 0x005f8000, .then = .{ .instruction = .@"amadd_db.h" } },
455 .{ .value = 0x006a0000, .then = .{ .instruction = .@"amadd_db.w" } },
456 .{ .value = 0x00628000, .then = .{ .instruction = .@"amand.d" } },
457 .{ .value = 0x00620000, .then = .{ .instruction = .@"amand.w" } },
458 .{ .value = 0x006b8000, .then = .{ .instruction = .@"amand_db.d" } },
459 .{ .value = 0x006b0000, .then = .{ .instruction = .@"amand_db.w" } },
460 .{ .value = 0x00580000, .then = .{ .instruction = .@"amcas.b" } },
461 .{ .value = 0x00598000, .then = .{ .instruction = .@"amcas.d" } },
462 .{ .value = 0x00588000, .then = .{ .instruction = .@"amcas.h" } },
463 .{ .value = 0x00590000, .then = .{ .instruction = .@"amcas.w" } },
464 .{ .value = 0x005a0000, .then = .{ .instruction = .@"amcas_db.b" } },
465 .{ .value = 0x005b8000, .then = .{ .instruction = .@"amcas_db.d" } },
466 .{ .value = 0x005a8000, .then = .{ .instruction = .@"amcas_db.h" } },
467 .{ .value = 0x005b0000, .then = .{ .instruction = .@"amcas_db.w" } },
468 .{ .value = 0x00658000, .then = .{ .instruction = .@"ammax.d" } },
469 .{ .value = 0x00678000, .then = .{ .instruction = .@"ammax.du" } },
470 .{ .value = 0x00650000, .then = .{ .instruction = .@"ammax.w" } },
471 .{ .value = 0x00670000, .then = .{ .instruction = .@"ammax.wu" } },
472 .{ .value = 0x006e8000, .then = .{ .instruction = .@"ammax_db.d" } },
473 .{ .value = 0x00708000, .then = .{ .instruction = .@"ammax_db.du" } },
474 .{ .value = 0x006e0000, .then = .{ .instruction = .@"ammax_db.w" } },
475 .{ .value = 0x00700000, .then = .{ .instruction = .@"ammax_db.wu" } },
476 .{ .value = 0x00668000, .then = .{ .instruction = .@"ammin.d" } },
477 .{ .value = 0x00688000, .then = .{ .instruction = .@"ammin.du" } },
478 .{ .value = 0x00660000, .then = .{ .instruction = .@"ammin.w" } },
479 .{ .value = 0x00680000, .then = .{ .instruction = .@"ammin.wu" } },
480 .{ .value = 0x006f8000, .then = .{ .instruction = .@"ammin_db.d" } },
481 .{ .value = 0x00718000, .then = .{ .instruction = .@"ammin_db.du" } },
482 .{ .value = 0x006f0000, .then = .{ .instruction = .@"ammin_db.w" } },
483 .{ .value = 0x00710000, .then = .{ .instruction = .@"ammin_db.wu" } },
484 .{ .value = 0x00638000, .then = .{ .instruction = .@"amor.d" } },
485 .{ .value = 0x00630000, .then = .{ .instruction = .@"amor.w" } },
486 .{ .value = 0x006c8000, .then = .{ .instruction = .@"amor_db.d" } },
487 .{ .value = 0x006c0000, .then = .{ .instruction = .@"amor_db.w" } },
488 .{ .value = 0x005c0000, .then = .{ .instruction = .@"amswap.b" } },
489 .{ .value = 0x00608000, .then = .{ .instruction = .@"amswap.d" } },
490 .{ .value = 0x005c8000, .then = .{ .instruction = .@"amswap.h" } },
491 .{ .value = 0x00600000, .then = .{ .instruction = .@"amswap.w" } },
492 .{ .value = 0x005e0000, .then = .{ .instruction = .@"amswap_db.b" } },
493 .{ .value = 0x00698000, .then = .{ .instruction = .@"amswap_db.d" } },
494 .{ .value = 0x005e8000, .then = .{ .instruction = .@"amswap_db.h" } },
495 .{ .value = 0x00690000, .then = .{ .instruction = .@"amswap_db.w" } },
496 .{ .value = 0x00648000, .then = .{ .instruction = .@"amxor.d" } },
497 .{ .value = 0x00640000, .then = .{ .instruction = .@"amxor.w" } },
498 .{ .value = 0x006d8000, .then = .{ .instruction = .@"amxor_db.d" } },
499 .{ .value = 0x006d0000, .then = .{ .instruction = .@"amxor_db.w" } },
500 .{ .value = 0x00720000, .then = .{ .instruction = .dbar } },
501 .{ .value = 0x00748000, .then = .{ .instruction = .@"fldgt.d" } },
502 .{ .value = 0x00740000, .then = .{ .instruction = .@"fldgt.s" } },
503 .{ .value = 0x00758000, .then = .{ .instruction = .@"fldle.d" } },
504 .{ .value = 0x00750000, .then = .{ .instruction = .@"fldle.s" } },
505 .{ .value = 0x00340000, .then = .{ .instruction = .@"fldx.d" } },
506 .{ .value = 0x00300000, .then = .{ .instruction = .@"fldx.s" } },
507 .{ .value = 0x00768000, .then = .{ .instruction = .@"fstgt.d" } },
508 .{ .value = 0x00760000, .then = .{ .instruction = .@"fstgt.s" } },
509 .{ .value = 0x00778000, .then = .{ .instruction = .@"fstle.d" } },
510 .{ .value = 0x00770000, .then = .{ .instruction = .@"fstle.s" } },
511 .{ .value = 0x003c0000, .then = .{ .instruction = .@"fstx.d" } },
512 .{ .value = 0x00380000, .then = .{ .instruction = .@"fstx.s" } },
513 .{ .value = 0x00728000, .then = .{ .instruction = .ibar } },
514 .{ .value = 0x00780000, .then = .{ .instruction = .@"ldgt.b" } },
515 .{ .value = 0x00798000, .then = .{ .instruction = .@"ldgt.d" } },
516 .{ .value = 0x00788000, .then = .{ .instruction = .@"ldgt.h" } },
517 .{ .value = 0x00790000, .then = .{ .instruction = .@"ldgt.w" } },
518 .{ .value = 0x007a0000, .then = .{ .instruction = .@"ldle.b" } },
519 .{ .value = 0x007b8000, .then = .{ .instruction = .@"ldle.d" } },
520 .{ .value = 0x007a8000, .then = .{ .instruction = .@"ldle.h" } },
521 .{ .value = 0x007b0000, .then = .{ .instruction = .@"ldle.w" } },
522 .{ .value = 0x00000000, .then = .{ .instruction = .@"ldx.b" } },
523 .{ .value = 0x00200000, .then = .{ .instruction = .@"ldx.bu" } },
524 .{ .value = 0x000c0000, .then = .{ .instruction = .@"ldx.d" } },
525 .{ .value = 0x00040000, .then = .{ .instruction = .@"ldx.h" } },
526 .{ .value = 0x00240000, .then = .{ .instruction = .@"ldx.hu" } },
527 .{ .value = 0x00080000, .then = .{ .instruction = .@"ldx.w" } },
528 .{ .value = 0x00280000, .then = .{ .instruction = .@"ldx.wu" } },
529 .{ .value = 0x00578000, .then = .{ .mask = 0x00007c00, .cases = .{
530 .{ .value = 0x00000800, .then = .{ .instruction = .@"llacq.d" } },
531 .{ .value = 0x00000000, .then = .{ .instruction = .@"llacq.w" } },
532 .{ .value = 0x00000c00, .then = .{ .instruction = .@"screl.d" } },
533 .{ .value = 0x00000400, .then = .{ .instruction = .@"screl.w" } },
534 } } },
535 .{ .value = 0x002c0000, .then = .{ .instruction = .preldx } },
536 .{ .value = 0x00570000, .then = .{ .instruction = .@"sc.q" } },
537 .{ .value = 0x007c0000, .then = .{ .instruction = .@"stgt.b" } },
538 .{ .value = 0x007d8000, .then = .{ .instruction = .@"stgt.d" } },
539 .{ .value = 0x007c8000, .then = .{ .instruction = .@"stgt.h" } },
540 .{ .value = 0x007d0000, .then = .{ .instruction = .@"stgt.w" } },
541 .{ .value = 0x007e0000, .then = .{ .instruction = .@"stle.b" } },
542 .{ .value = 0x007f8000, .then = .{ .instruction = .@"stle.d" } },
543 .{ .value = 0x007e8000, .then = .{ .instruction = .@"stle.h" } },
544 .{ .value = 0x007f0000, .then = .{ .instruction = .@"stle.w" } },
545 .{ .value = 0x00100000, .then = .{ .instruction = .@"stx.b" } },
546 .{ .value = 0x001c0000, .then = .{ .instruction = .@"stx.d" } },
547 .{ .value = 0x00140000, .then = .{ .instruction = .@"stx.h" } },
548 .{ .value = 0x00180000, .then = .{ .instruction = .@"stx.w" } },
549 .{ .value = 0x00400000, .then = .{ .instruction = .vldx } },
550 .{ .value = 0x00440000, .then = .{ .instruction = .vstx } },
551 .{ .value = 0x00480000, .then = .{ .instruction = .xvldx } },
552 .{ .value = 0x004c0000, .then = .{ .instruction = .xvstx } },
553 } } },
554 .{ .value = 0x50000000, .then = .{ .instruction = .b } },
555 .{ .value = 0x48000000, .then = .{ .mask = 0x00000300, .cases = .{
556 .{ .value = 0x00000000, .then = .{ .instruction = .bceqz } },
557 .{ .value = 0x00000100, .then = .{ .instruction = .bcnez } },
558 .{ .value = 0x00000200, .then = .{ .instruction = .jiscr0 } },
559 .{ .value = 0x00000300, .then = .{ .instruction = .jiscr1 } },
560 } } },
561 .{ .value = 0x58000000, .then = .{ .instruction = .beq } },
562 .{ .value = 0x40000000, .then = .{ .instruction = .beqz } },
563 .{ .value = 0x60000000, .then = .{ .instruction = .bgt } },
564 .{ .value = 0x68000000, .then = .{ .instruction = .bgtu } },
565 .{ .value = 0x54000000, .then = .{ .instruction = .bl } },
566 .{ .value = 0x64000000, .then = .{ .instruction = .ble } },
567 .{ .value = 0x6c000000, .then = .{ .instruction = .bleu } },
568 .{ .value = 0x5c000000, .then = .{ .instruction = .bne } },
569 .{ .value = 0x44000000, .then = .{ .instruction = .bnez } },
570 .{ .value = 0x04000000, .then = .{ .mask = 0x03000000, .cases = .{
571 .{ .value = 0x02000000, .then = .{ .mask = 0x00c00000, .cases = .{
572 .{ .value = 0x00000000, .then = .{ .instruction = .cacop } },
573 .{ .value = 0x00400000, .then = .{ .mask = 0x003c0000, .cases = .{
574 .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{
575 .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{
576 .{ .value = 0x00003800, .then = .{ .instruction = .eret } },
577 .{ .value = 0x00002000, .then = .{ .mask = 0x000003ff, .cases = .{
578 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbclr } },
579 .{ .value = 0x00000000, .then = .{ .instruction = .tlbclr } },
580 } } },
581 .{ .value = 0x00003400, .then = .{ .mask = 0x000003ff, .cases = .{
582 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbfill } },
583 .{ .value = 0x00000000, .then = .{ .instruction = .tlbfill } },
584 } } },
585 .{ .value = 0x00002400, .then = .{ .mask = 0x000003ff, .cases = .{
586 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbflush } },
587 .{ .value = 0x00000000, .then = .{ .instruction = .tlbflush } },
588 } } },
589 .{ .value = 0x00002c00, .then = .{ .mask = 0x000003ff, .cases = .{
590 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbrd } },
591 .{ .value = 0x00000000, .then = .{ .instruction = .tlbrd } },
592 } } },
593 .{ .value = 0x00002800, .then = .{ .mask = 0x000003ff, .cases = .{
594 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbsrch } },
595 .{ .value = 0x00000000, .then = .{ .instruction = .tlbsrch } },
596 } } },
597 .{ .value = 0x00003000, .then = .{ .mask = 0x000003ff, .cases = .{
598 .{ .value = 0x00000001, .then = .{ .instruction = .gtlbwr } },
599 .{ .value = 0x00000000, .then = .{ .instruction = .tlbwr } },
600 } } },
601 .{ .value = 0x00000000, .then = .{ .instruction = .@"iocsrrd.b" } },
602 .{ .value = 0x00000c00, .then = .{ .instruction = .@"iocsrrd.d" } },
603 .{ .value = 0x00000400, .then = .{ .instruction = .@"iocsrrd.h" } },
604 .{ .value = 0x00000800, .then = .{ .instruction = .@"iocsrrd.w" } },
605 .{ .value = 0x00001000, .then = .{ .instruction = .@"iocsrwr.b" } },
606 .{ .value = 0x00001c00, .then = .{ .instruction = .@"iocsrwr.d" } },
607 .{ .value = 0x00001400, .then = .{ .instruction = .@"iocsrwr.h" } },
608 .{ .value = 0x00001800, .then = .{ .instruction = .@"iocsrwr.w" } },
609 } } },
610 .{ .value = 0x00008000, .then = .{ .instruction = .idle } },
611 .{ .value = 0x00018000, .then = .{ .instruction = .tlbinv } },
612 .{ .value = 0x00010000, .then = .{ .instruction = .@"xxx.unknown.1" } },
613 } } },
614 .{ .value = 0x00000000, .then = .{ .instruction = .lddir } },
615 .{ .value = 0x00040000, .then = .{ .instruction = .ldpte } },
616 } } },
617 } } },
618 .{ .value = 0x00000000, .then = .{ .mask = 0x000003e0, .cases = .{
619 .{ .value = 0x00000000, .then = .{ .instruction = .csrrd } },
620 .{ .value = 0x00000020, .then = .{ .instruction = .csrwr } },
621 .{ .then = .{ .instruction = .csrxchg } },
622 } } },
623 .{ .value = 0x01000000, .then = .{ .mask = 0x000003e0, .cases = .{
624 .{ .value = 0x00000000, .then = .{ .instruction = .gcsrrd } },
625 .{ .value = 0x00000020, .then = .{ .instruction = .gcsrwr } },
626 .{ .then = .{ .instruction = .gcsrxchg } },
627 } } },
628 } } },
629 .{ .value = 0x14000000, .then = .{ .mask = 0x02000000, .cases = .{
630 .{ .value = 0x02000000, .then = .{ .instruction = .@"cu32i.d" } },
631 .{ .value = 0x00000000, .then = .{ .instruction = .@"lu12i.w" } },
632 } } },
633 .{ .value = 0x0c000000, .then = .{ .mask = 0x03f00000, .cases = .{
634 .{ .value = 0x00200000, .then = .{ .mask = 0x000f8018, .cases = .{
635 .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.d" } },
636 .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.d" } },
637 .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.d" } },
638 .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.d" } },
639 .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.d" } },
640 .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.d" } },
641 .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.d" } },
642 .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.d" } },
643 .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.d" } },
644 .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.d" } },
645 .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.d" } },
646 .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.d" } },
647 .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.d" } },
648 .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.d" } },
649 .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.d" } },
650 .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.d" } },
651 .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.d" } },
652 .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.d" } },
653 .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.d" } },
654 .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.d" } },
655 .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.d" } },
656 .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.d" } },
657 } } },
658 .{ .value = 0x00100000, .then = .{ .mask = 0x000f8018, .cases = .{
659 .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.s" } },
660 .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.s" } },
661 .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.s" } },
662 .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.s" } },
663 .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.s" } },
664 .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.s" } },
665 .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.s" } },
666 .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.s" } },
667 .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.s" } },
668 .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.s" } },
669 .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.s" } },
670 .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.s" } },
671 .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.s" } },
672 .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.s" } },
673 .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.s" } },
674 .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.s" } },
675 .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.s" } },
676 .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.s" } },
677 .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.s" } },
678 .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.s" } },
679 .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.s" } },
680 .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.s" } },
681 } } },
682 .{ .value = 0x01000000, .then = .{ .instruction = .fsel } },
683 .{ .value = 0x01100000, .then = .{ .instruction = .@"vbitsel.v" } },
684 .{ .value = 0x00600000, .then = .{ .mask = 0x000f8000, .cases = .{
685 .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.d" } },
686 .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.d" } },
687 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.d" } },
688 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.d" } },
689 .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.d" } },
690 .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.d" } },
691 .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.d" } },
692 .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.d" } },
693 .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.d" } },
694 .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.d" } },
695 .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.d" } },
696 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.d" } },
697 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.d" } },
698 .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.d" } },
699 .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.d" } },
700 .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.d" } },
701 .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.d" } },
702 .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.d" } },
703 .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.d" } },
704 .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.d" } },
705 .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.d" } },
706 .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.d" } },
707 } } },
708 .{ .value = 0x00500000, .then = .{ .mask = 0x000f8000, .cases = .{
709 .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.s" } },
710 .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.s" } },
711 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.s" } },
712 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.s" } },
713 .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.s" } },
714 .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.s" } },
715 .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.s" } },
716 .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.s" } },
717 .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.s" } },
718 .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.s" } },
719 .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.s" } },
720 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.s" } },
721 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.s" } },
722 .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.s" } },
723 .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.s" } },
724 .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.s" } },
725 .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.s" } },
726 .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.s" } },
727 .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.s" } },
728 .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.s" } },
729 .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.s" } },
730 .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.s" } },
731 } } },
732 .{ .value = 0x01500000, .then = .{ .instruction = .@"vshuf.b" } },
733 .{ .value = 0x01200000, .then = .{ .instruction = .@"xvbitsel.v" } },
734 .{ .value = 0x00a00000, .then = .{ .mask = 0x000f8000, .cases = .{
735 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.d" } },
736 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.d" } },
737 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.d" } },
738 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.d" } },
739 .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.d" } },
740 .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.d" } },
741 .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.d" } },
742 .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.d" } },
743 .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.d" } },
744 .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.d" } },
745 .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.d" } },
746 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.d" } },
747 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.d" } },
748 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.d" } },
749 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.d" } },
750 .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.d" } },
751 .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.d" } },
752 .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.d" } },
753 .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.d" } },
754 .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.d" } },
755 .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.d" } },
756 .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.d" } },
757 } } },
758 .{ .value = 0x00900000, .then = .{ .mask = 0x000f8000, .cases = .{
759 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.s" } },
760 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.s" } },
761 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.s" } },
762 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.s" } },
763 .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.s" } },
764 .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.s" } },
765 .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.s" } },
766 .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.s" } },
767 .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.s" } },
768 .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.s" } },
769 .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.s" } },
770 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.s" } },
771 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.s" } },
772 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.s" } },
773 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.s" } },
774 .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.s" } },
775 .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.s" } },
776 .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.s" } },
777 .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.s" } },
778 .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.s" } },
779 .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.s" } },
780 .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.s" } },
781 } } },
782 .{ .value = 0x01600000, .then = .{ .instruction = .@"xvshuf.b" } },
783 } } },
784 .{ .value = 0x28000000, .then = .{ .mask = 0x03c00000, .cases = .{
785 .{ .value = 0x03800000, .then = .{ .instruction = .@"fld.d" } },
786 .{ .value = 0x03000000, .then = .{ .instruction = .@"fld.s" } },
787 .{ .value = 0x03c00000, .then = .{ .instruction = .@"fst.d" } },
788 .{ .value = 0x03400000, .then = .{ .instruction = .@"fst.s" } },
789 .{ .value = 0x00000000, .then = .{ .instruction = .@"ld.b" } },
790 .{ .value = 0x02000000, .then = .{ .instruction = .@"ld.bu" } },
791 .{ .value = 0x00c00000, .then = .{ .instruction = .@"ld.d" } },
792 .{ .value = 0x00400000, .then = .{ .instruction = .@"ld.h" } },
793 .{ .value = 0x02400000, .then = .{ .instruction = .@"ld.hu" } },
794 .{ .value = 0x00800000, .then = .{ .instruction = .@"ld.w" } },
795 .{ .value = 0x02800000, .then = .{ .instruction = .@"ld.wu" } },
796 .{ .value = 0x02c00000, .then = .{ .instruction = .preld } },
797 .{ .value = 0x01000000, .then = .{ .instruction = .@"st.b" } },
798 .{ .value = 0x01c00000, .then = .{ .instruction = .@"st.d" } },
799 .{ .value = 0x01400000, .then = .{ .instruction = .@"st.h" } },
800 .{ .value = 0x01800000, .then = .{ .instruction = .@"st.w" } },
801 } } },
802 .{ .value = 0x08000000, .then = .{ .mask = 0x03f00000, .cases = .{
803 .{ .value = 0x00200000, .then = .{ .instruction = .@"fmadd.d" } },
804 .{ .value = 0x00100000, .then = .{ .instruction = .@"fmadd.s" } },
805 .{ .value = 0x00600000, .then = .{ .instruction = .@"fmsub.d" } },
806 .{ .value = 0x00500000, .then = .{ .instruction = .@"fmsub.s" } },
807 .{ .value = 0x00a00000, .then = .{ .instruction = .@"fnmadd.d" } },
808 .{ .value = 0x00900000, .then = .{ .instruction = .@"fnmadd.s" } },
809 .{ .value = 0x00e00000, .then = .{ .instruction = .@"fnmsub.d" } },
810 .{ .value = 0x00d00000, .then = .{ .instruction = .@"fnmsub.s" } },
811 .{ .value = 0x01200000, .then = .{ .instruction = .@"vfmadd.d" } },
812 .{ .value = 0x01100000, .then = .{ .instruction = .@"vfmadd.s" } },
813 .{ .value = 0x01600000, .then = .{ .instruction = .@"vfmsub.d" } },
814 .{ .value = 0x01500000, .then = .{ .instruction = .@"vfmsub.s" } },
815 .{ .value = 0x01a00000, .then = .{ .instruction = .@"vfnmadd.d" } },
816 .{ .value = 0x01900000, .then = .{ .instruction = .@"vfnmadd.s" } },
817 .{ .value = 0x01e00000, .then = .{ .instruction = .@"vfnmsub.d" } },
818 .{ .value = 0x01d00000, .then = .{ .instruction = .@"vfnmsub.s" } },
819 .{ .value = 0x02200000, .then = .{ .instruction = .@"xvfmadd.d" } },
820 .{ .value = 0x02100000, .then = .{ .instruction = .@"xvfmadd.s" } },
821 .{ .value = 0x02600000, .then = .{ .instruction = .@"xvfmsub.d" } },
822 .{ .value = 0x02500000, .then = .{ .instruction = .@"xvfmsub.s" } },
823 .{ .value = 0x02a00000, .then = .{ .instruction = .@"xvfnmadd.d" } },
824 .{ .value = 0x02900000, .then = .{ .instruction = .@"xvfnmadd.s" } },
825 .{ .value = 0x02e00000, .then = .{ .instruction = .@"xvfnmsub.d" } },
826 .{ .value = 0x02d00000, .then = .{ .instruction = .@"xvfnmsub.s" } },
827 } } },
828 .{ .value = 0x4c000000, .then = .{ .instruction = .jirl } },
829 .{ .value = 0x2c000000, .then = .{ .mask = 0x03c00000, .cases = .{
830 .{ .value = 0x02800000, .then = .{ .instruction = .@"ldl.d" } },
831 .{ .value = 0x02000000, .then = .{ .instruction = .@"ldl.w" } },
832 .{ .value = 0x02c00000, .then = .{ .instruction = .@"ldr.d" } },
833 .{ .value = 0x02400000, .then = .{ .instruction = .@"ldr.w" } },
834 .{ .value = 0x03800000, .then = .{ .instruction = .@"stl.d" } },
835 .{ .value = 0x03000000, .then = .{ .instruction = .@"stl.w" } },
836 .{ .value = 0x03c00000, .then = .{ .instruction = .@"str.d" } },
837 .{ .value = 0x03400000, .then = .{ .instruction = .@"str.w" } },
838 .{ .value = 0x00000000, .then = .{ .instruction = .vld } },
839 .{ .value = 0x00400000, .then = .{ .instruction = .vst } },
840 .{ .value = 0x00800000, .then = .{ .instruction = .xvld } },
841 .{ .value = 0x00c00000, .then = .{ .instruction = .xvst } },
842 } } },
843 .{ .value = 0x24000000, .then = .{ .mask = 0x03000000, .cases = .{
844 .{ .value = 0x02000000, .then = .{ .instruction = .@"ldox4.d" } },
845 .{ .value = 0x00000000, .then = .{ .instruction = .@"ldox4.w" } },
846 .{ .value = 0x03000000, .then = .{ .instruction = .@"stox4.d" } },
847 .{ .value = 0x01000000, .then = .{ .instruction = .@"stox4.w" } },
848 } } },
849 .{ .value = 0x20000000, .then = .{ .mask = 0x03000000, .cases = .{
850 .{ .value = 0x02000000, .then = .{ .instruction = .@"ll.d" } },
851 .{ .value = 0x00000000, .then = .{ .instruction = .@"ll.w" } },
852 .{ .value = 0x03000000, .then = .{ .instruction = .@"sc.d" } },
853 .{ .value = 0x01000000, .then = .{ .instruction = .@"sc.w" } },
854 } } },
855 .{ .value = 0x1c000000, .then = .{ .mask = 0x02000000, .cases = .{
856 .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu12i } },
857 .{ .value = 0x02000000, .then = .{ .instruction = .pcaddu18i } },
858 } } },
859 .{ .value = 0x18000000, .then = .{ .mask = 0x02000000, .cases = .{
860 .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu2i } },
861 .{ .value = 0x02000000, .then = .{ .instruction = .pcalau12i } },
862 } } },
863 .{ .value = 0x70000000, .then = .{ .mask = 0x03fc0000, .cases = .{
864 .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{
865 .{ .value = 0x00000000, .then = .{ .instruction = .@"vabsd.b" } },
866 .{ .value = 0x00020000, .then = .{ .instruction = .@"vabsd.bu" } },
867 .{ .value = 0x00018000, .then = .{ .instruction = .@"vabsd.d" } },
868 .{ .value = 0x00038000, .then = .{ .instruction = .@"vabsd.du" } },
869 .{ .value = 0x00008000, .then = .{ .instruction = .@"vabsd.h" } },
870 .{ .value = 0x00028000, .then = .{ .instruction = .@"vabsd.hu" } },
871 .{ .value = 0x00010000, .then = .{ .instruction = .@"vabsd.w" } },
872 .{ .value = 0x00030000, .then = .{ .instruction = .@"vabsd.wu" } },
873 } } },
874 .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{
875 .{ .value = 0x00020000, .then = .{ .instruction = .@"vadd.b" } },
876 .{ .value = 0x00038000, .then = .{ .instruction = .@"vadd.d" } },
877 .{ .value = 0x00028000, .then = .{ .instruction = .@"vadd.h" } },
878 .{ .value = 0x00030000, .then = .{ .instruction = .@"vadd.w" } },
879 .{ .value = 0x00000000, .then = .{ .instruction = .@"vslt.bu" } },
880 .{ .value = 0x00018000, .then = .{ .instruction = .@"vslt.du" } },
881 .{ .value = 0x00008000, .then = .{ .instruction = .@"vslt.hu" } },
882 .{ .value = 0x00010000, .then = .{ .instruction = .@"vslt.wu" } },
883 } } },
884 .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{
885 .{ .value = 0x00010000, .then = .{ .instruction = .@"vadd.q" } },
886 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsigncov.b" } },
887 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsigncov.d" } },
888 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsigncov.h" } },
889 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsigncov.w" } },
890 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.q" } },
891 } } },
892 .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{
893 .{ .value = 0x00000000, .then = .{ .instruction = .@"vadda.b" } },
894 .{ .value = 0x00018000, .then = .{ .instruction = .@"vadda.d" } },
895 .{ .value = 0x00008000, .then = .{ .instruction = .@"vadda.h" } },
896 .{ .value = 0x00010000, .then = .{ .instruction = .@"vadda.w" } },
897 } } },
898 .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{
899 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddi.bu" } },
900 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddi.du" } },
901 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddi.hu" } },
902 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddi.wu" } },
903 .{ .value = 0x00000000, .then = .{ .instruction = .@"vslti.bu" } },
904 .{ .value = 0x00018000, .then = .{ .instruction = .@"vslti.du" } },
905 .{ .value = 0x00008000, .then = .{ .instruction = .@"vslti.hu" } },
906 .{ .value = 0x00010000, .then = .{ .instruction = .@"vslti.wu" } },
907 } } },
908 .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{
909 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.w" } },
910 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.b" } },
911 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.d" } },
912 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.h" } },
913 } } },
914 .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{
915 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu" } },
916 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu" } },
917 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du" } },
918 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu" } },
919 } } },
920 .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{
921 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu.w" } },
922 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu.b" } },
923 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du.d" } },
924 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu.h" } },
925 } } },
926 .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{
927 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.w" } },
928 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.b" } },
929 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.d" } },
930 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.h" } },
931 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.w" } },
932 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.b" } },
933 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.d" } },
934 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.h" } },
935 } } },
936 .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{
937 .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.wu" } },
938 .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.bu" } },
939 .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.du" } },
940 .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.hu" } },
941 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.wu" } },
942 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.bu" } },
943 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.du" } },
944 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.hu" } },
945 } } },
946 .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{
947 .{ .value = 0x00010000, .then = .{ .instruction = .@"vaddwod.d.wu.w" } },
948 .{ .value = 0x00000000, .then = .{ .instruction = .@"vaddwod.h.bu.b" } },
949 .{ .value = 0x00018000, .then = .{ .instruction = .@"vaddwod.q.du.d" } },
950 .{ .value = 0x00008000, .then = .{ .instruction = .@"vaddwod.w.hu.h" } },
951 } } },
952 .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{
953 .{ .value = 0x00020000, .then = .{ .instruction = .@"vand.v" } },
954 .{ .value = 0x00038000, .then = .{ .instruction = .@"vnor.v" } },
955 .{ .value = 0x00028000, .then = .{ .instruction = .@"vor.v" } },
956 .{ .value = 0x00030000, .then = .{ .instruction = .@"vxor.v" } },
957 } } },
958 .{ .value = 0x03d00000, .then = .{ .instruction = .@"vandi.b" } },
959 .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{
960 .{ .value = 0x00000000, .then = .{ .instruction = .@"vandn.v" } },
961 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfrstp.b" } },
962 .{ .value = 0x00038000, .then = .{ .instruction = .@"vfrstp.h" } },
963 .{ .value = 0x00008000, .then = .{ .instruction = .@"vorn.v" } },
964 } } },
965 .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{
966 .{ .value = 0x00000000, .then = .{ .instruction = .@"vavg.b" } },
967 .{ .value = 0x00020000, .then = .{ .instruction = .@"vavg.bu" } },
968 .{ .value = 0x00018000, .then = .{ .instruction = .@"vavg.d" } },
969 .{ .value = 0x00038000, .then = .{ .instruction = .@"vavg.du" } },
970 .{ .value = 0x00008000, .then = .{ .instruction = .@"vavg.h" } },
971 .{ .value = 0x00028000, .then = .{ .instruction = .@"vavg.hu" } },
972 .{ .value = 0x00010000, .then = .{ .instruction = .@"vavg.w" } },
973 .{ .value = 0x00030000, .then = .{ .instruction = .@"vavg.wu" } },
974 } } },
975 .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{
976 .{ .value = 0x00000000, .then = .{ .instruction = .@"vavgr.b" } },
977 .{ .value = 0x00020000, .then = .{ .instruction = .@"vavgr.bu" } },
978 .{ .value = 0x00018000, .then = .{ .instruction = .@"vavgr.d" } },
979 .{ .value = 0x00038000, .then = .{ .instruction = .@"vavgr.du" } },
980 .{ .value = 0x00008000, .then = .{ .instruction = .@"vavgr.h" } },
981 .{ .value = 0x00028000, .then = .{ .instruction = .@"vavgr.hu" } },
982 .{ .value = 0x00010000, .then = .{ .instruction = .@"vavgr.w" } },
983 .{ .value = 0x00030000, .then = .{ .instruction = .@"vavgr.wu" } },
984 } } },
985 .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{
986 .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclr.b" } },
987 .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitclr.d" } },
988 .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclr.h" } },
989 .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclr.w" } },
990 .{ .value = 0x00020000, .then = .{ .instruction = .@"vbitset.b" } },
991 .{ .value = 0x00038000, .then = .{ .instruction = .@"vbitset.d" } },
992 .{ .value = 0x00028000, .then = .{ .instruction = .@"vbitset.h" } },
993 .{ .value = 0x00030000, .then = .{ .instruction = .@"vbitset.w" } },
994 } } },
995 .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{
996 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
997 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
998 .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclri.b" } },
999 .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitclri.h" } },
1000 } } },
1001 .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclri.w" } },
1002 } } },
1003 .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclri.d" } },
1004 } } },
1005 .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{
1006 .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrev.b" } },
1007 .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitrev.d" } },
1008 .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrev.h" } },
1009 .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrev.w" } },
1010 } } },
1011 .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{
1012 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1013 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1014 .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrevi.b" } },
1015 .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitrevi.h" } },
1016 } } },
1017 .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrevi.w" } },
1018 } } },
1019 .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrevi.d" } },
1020 } } },
1021 .{ .value = 0x03c40000, .then = .{ .instruction = .@"vbitseli.b" } },
1022 .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{
1023 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1024 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1025 .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitseti.b" } },
1026 .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitseti.h" } },
1027 } } },
1028 .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitseti.w" } },
1029 } } },
1030 .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitseti.d" } },
1031 } } },
1032 .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{
1033 .{ .value = 0x00020000, .then = .{ .instruction = .@"vbsll.v" } },
1034 .{ .value = 0x00028000, .then = .{ .instruction = .@"vbsrl.v" } },
1035 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubi.bu" } },
1036 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubi.du" } },
1037 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubi.hu" } },
1038 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubi.wu" } },
1039 } } },
1040 .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{
1041 .{ .value = 0x00000000, .then = .{ .instruction = .@"vclo.b" } },
1042 .{ .value = 0x00000c00, .then = .{ .instruction = .@"vclo.d" } },
1043 .{ .value = 0x00000400, .then = .{ .instruction = .@"vclo.h" } },
1044 .{ .value = 0x00000800, .then = .{ .instruction = .@"vclo.w" } },
1045 .{ .value = 0x00001000, .then = .{ .instruction = .@"vclz.b" } },
1046 .{ .value = 0x00001c00, .then = .{ .instruction = .@"vclz.d" } },
1047 .{ .value = 0x00001400, .then = .{ .instruction = .@"vclz.h" } },
1048 .{ .value = 0x00001800, .then = .{ .instruction = .@"vclz.w" } },
1049 .{ .value = 0x0002e800, .then = .{ .instruction = .@"vexth.d.w" } },
1050 .{ .value = 0x0002f800, .then = .{ .instruction = .@"vexth.du.wu" } },
1051 .{ .value = 0x0002e000, .then = .{ .instruction = .@"vexth.h.b" } },
1052 .{ .value = 0x0002f000, .then = .{ .instruction = .@"vexth.hu.bu" } },
1053 .{ .value = 0x0002ec00, .then = .{ .instruction = .@"vexth.q.d" } },
1054 .{ .value = 0x0002fc00, .then = .{ .instruction = .@"vexth.qu.du" } },
1055 .{ .value = 0x0002e400, .then = .{ .instruction = .@"vexth.w.h" } },
1056 .{ .value = 0x0002f400, .then = .{ .instruction = .@"vexth.wu.hu" } },
1057 .{ .value = 0x0000d800, .then = .{ .instruction = .@"vfclass.d" } },
1058 .{ .value = 0x0000d400, .then = .{ .instruction = .@"vfclass.s" } },
1059 .{ .value = 0x0001f400, .then = .{ .instruction = .@"vfcvth.d.s" } },
1060 .{ .value = 0x0001ec00, .then = .{ .instruction = .@"vfcvth.s.h" } },
1061 .{ .value = 0x0001f000, .then = .{ .instruction = .@"vfcvtl.d.s" } },
1062 .{ .value = 0x0001e800, .then = .{ .instruction = .@"vfcvtl.s.h" } },
1063 .{ .value = 0x00020800, .then = .{ .instruction = .@"vffint.d.l" } },
1064 .{ .value = 0x00020c00, .then = .{ .instruction = .@"vffint.d.lu" } },
1065 .{ .value = 0x00020000, .then = .{ .instruction = .@"vffint.s.w" } },
1066 .{ .value = 0x00020400, .then = .{ .instruction = .@"vffint.s.wu" } },
1067 .{ .value = 0x00021400, .then = .{ .instruction = .@"vffinth.d.w" } },
1068 .{ .value = 0x00021000, .then = .{ .instruction = .@"vffintl.d.w" } },
1069 .{ .value = 0x0000c800, .then = .{ .instruction = .@"vflogb.d" } },
1070 .{ .value = 0x0000c400, .then = .{ .instruction = .@"vflogb.s" } },
1071 .{ .value = 0x0000f800, .then = .{ .instruction = .@"vfrecip.d" } },
1072 .{ .value = 0x0000f400, .then = .{ .instruction = .@"vfrecip.s" } },
1073 .{ .value = 0x00011800, .then = .{ .instruction = .@"vfrecipe.d" } },
1074 .{ .value = 0x00011400, .then = .{ .instruction = .@"vfrecipe.s" } },
1075 .{ .value = 0x00013800, .then = .{ .instruction = .@"vfrint.d" } },
1076 .{ .value = 0x00013400, .then = .{ .instruction = .@"vfrint.s" } },
1077 .{ .value = 0x00014800, .then = .{ .instruction = .@"vfrintrm.d" } },
1078 .{ .value = 0x00014400, .then = .{ .instruction = .@"vfrintrm.s" } },
1079 .{ .value = 0x00017800, .then = .{ .instruction = .@"vfrintrne.d" } },
1080 .{ .value = 0x00017400, .then = .{ .instruction = .@"vfrintrne.s" } },
1081 .{ .value = 0x00015800, .then = .{ .instruction = .@"vfrintrp.d" } },
1082 .{ .value = 0x00015400, .then = .{ .instruction = .@"vfrintrp.s" } },
1083 .{ .value = 0x00016800, .then = .{ .instruction = .@"vfrintrz.d" } },
1084 .{ .value = 0x00016400, .then = .{ .instruction = .@"vfrintrz.s" } },
1085 .{ .value = 0x00010800, .then = .{ .instruction = .@"vfrsqrt.d" } },
1086 .{ .value = 0x00010400, .then = .{ .instruction = .@"vfrsqrt.s" } },
1087 .{ .value = 0x00012800, .then = .{ .instruction = .@"vfrsqrte.d" } },
1088 .{ .value = 0x00012400, .then = .{ .instruction = .@"vfrsqrte.s" } },
1089 .{ .value = 0x0000e800, .then = .{ .instruction = .@"vfsqrt.d" } },
1090 .{ .value = 0x0000e400, .then = .{ .instruction = .@"vfsqrt.s" } },
1091 .{ .value = 0x00023400, .then = .{ .instruction = .@"vftint.l.d" } },
1092 .{ .value = 0x00025c00, .then = .{ .instruction = .@"vftint.lu.d" } },
1093 .{ .value = 0x00023000, .then = .{ .instruction = .@"vftint.w.s" } },
1094 .{ .value = 0x00025800, .then = .{ .instruction = .@"vftint.wu.s" } },
1095 .{ .value = 0x00028400, .then = .{ .instruction = .@"vftinth.l.s" } },
1096 .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintl.l.s" } },
1097 .{ .value = 0x00023c00, .then = .{ .instruction = .@"vftintrm.l.d" } },
1098 .{ .value = 0x00023800, .then = .{ .instruction = .@"vftintrm.w.s" } },
1099 .{ .value = 0x00028c00, .then = .{ .instruction = .@"vftintrmh.l.s" } },
1100 .{ .value = 0x00028800, .then = .{ .instruction = .@"vftintrml.l.s" } },
1101 .{ .value = 0x00025400, .then = .{ .instruction = .@"vftintrne.l.d" } },
1102 .{ .value = 0x00025000, .then = .{ .instruction = .@"vftintrne.w.s" } },
1103 .{ .value = 0x0002a400, .then = .{ .instruction = .@"vftintrneh.l.s" } },
1104 .{ .value = 0x0002a000, .then = .{ .instruction = .@"vftintrnel.l.s" } },
1105 .{ .value = 0x00024400, .then = .{ .instruction = .@"vftintrp.l.d" } },
1106 .{ .value = 0x00024000, .then = .{ .instruction = .@"vftintrp.w.s" } },
1107 .{ .value = 0x00029400, .then = .{ .instruction = .@"vftintrph.l.s" } },
1108 .{ .value = 0x00029000, .then = .{ .instruction = .@"vftintrpl.l.s" } },
1109 .{ .value = 0x00024c00, .then = .{ .instruction = .@"vftintrz.l.d" } },
1110 .{ .value = 0x00027400, .then = .{ .instruction = .@"vftintrz.lu.d" } },
1111 .{ .value = 0x00024800, .then = .{ .instruction = .@"vftintrz.w.s" } },
1112 .{ .value = 0x00027000, .then = .{ .instruction = .@"vftintrz.wu.s" } },
1113 .{ .value = 0x00029c00, .then = .{ .instruction = .@"vftintrzh.l.s" } },
1114 .{ .value = 0x00029800, .then = .{ .instruction = .@"vftintrzl.l.s" } },
1115 .{ .value = 0x00005000, .then = .{ .instruction = .@"vmskgez.b" } },
1116 .{ .value = 0x00004000, .then = .{ .instruction = .@"vmskltz.b" } },
1117 .{ .value = 0x00004c00, .then = .{ .instruction = .@"vmskltz.d" } },
1118 .{ .value = 0x00004400, .then = .{ .instruction = .@"vmskltz.h" } },
1119 .{ .value = 0x00004800, .then = .{ .instruction = .@"vmskltz.w" } },
1120 .{ .value = 0x00006000, .then = .{ .instruction = .@"vmsknz.b" } },
1121 .{ .value = 0x00003000, .then = .{ .instruction = .@"vneg.b" } },
1122 .{ .value = 0x00003c00, .then = .{ .instruction = .@"vneg.d" } },
1123 .{ .value = 0x00003400, .then = .{ .instruction = .@"vneg.h" } },
1124 .{ .value = 0x00003800, .then = .{ .instruction = .@"vneg.w" } },
1125 .{ .value = 0x00002000, .then = .{ .instruction = .@"vpcnt.b" } },
1126 .{ .value = 0x00002c00, .then = .{ .instruction = .@"vpcnt.d" } },
1127 .{ .value = 0x00002400, .then = .{ .instruction = .@"vpcnt.h" } },
1128 .{ .value = 0x00002800, .then = .{ .instruction = .@"vpcnt.w" } },
1129 .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplgr2vr.b" } },
1130 .{ .value = 0x00030c00, .then = .{ .instruction = .@"vreplgr2vr.d" } },
1131 .{ .value = 0x00030400, .then = .{ .instruction = .@"vreplgr2vr.h" } },
1132 .{ .value = 0x00030800, .then = .{ .instruction = .@"vreplgr2vr.w" } },
1133 .{ .value = 0x0000b000, .then = .{ .instruction = .@"vsetallnez.b" } },
1134 .{ .value = 0x0000bc00, .then = .{ .instruction = .@"vsetallnez.d" } },
1135 .{ .value = 0x0000b400, .then = .{ .instruction = .@"vsetallnez.h" } },
1136 .{ .value = 0x0000b800, .then = .{ .instruction = .@"vsetallnez.w" } },
1137 .{ .value = 0x0000a000, .then = .{ .instruction = .@"vsetanyeqz.b" } },
1138 .{ .value = 0x0000ac00, .then = .{ .instruction = .@"vsetanyeqz.d" } },
1139 .{ .value = 0x0000a400, .then = .{ .instruction = .@"vsetanyeqz.h" } },
1140 .{ .value = 0x0000a800, .then = .{ .instruction = .@"vsetanyeqz.w" } },
1141 .{ .value = 0x00009800, .then = .{ .instruction = .@"vseteqz.v" } },
1142 .{ .value = 0x00009c00, .then = .{ .instruction = .@"vsetnez.v" } },
1143 } } },
1144 .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{
1145 .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.b" } },
1146 .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.d" } },
1147 .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.h" } },
1148 .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.w" } },
1149 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.b" } },
1150 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.d" } },
1151 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.h" } },
1152 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.w" } },
1153 } } },
1154 .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{
1155 .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.bu" } },
1156 .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.du" } },
1157 .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.hu" } },
1158 .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.wu" } },
1159 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.bu" } },
1160 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.du" } },
1161 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.hu" } },
1162 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.wu" } },
1163 } } },
1164 .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{
1165 .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.q.d" } },
1166 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.d.w" } },
1167 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1168 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.h.b" } },
1169 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.w.h" } },
1170 } } },
1171 } } },
1172 .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{
1173 .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.qu.du" } },
1174 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.du.wu" } },
1175 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1176 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.hu.bu" } },
1177 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.wu.hu" } },
1178 } } },
1179 } } },
1180 .{ .value = 0x038c0000, .then = .{ .instruction = .@"vextrins.b" } },
1181 .{ .value = 0x03800000, .then = .{ .instruction = .@"vextrins.d" } },
1182 .{ .value = 0x03880000, .then = .{ .instruction = .@"vextrins.h" } },
1183 .{ .value = 0x03840000, .then = .{ .instruction = .@"vextrins.w" } },
1184 .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{
1185 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfadd.d" } },
1186 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfadd.s" } },
1187 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfsub.d" } },
1188 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfsub.s" } },
1189 } } },
1190 .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{
1191 .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcvt.h.s" } },
1192 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcvt.s.d" } },
1193 } } },
1194 .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{
1195 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfdiv.d" } },
1196 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfdiv.s" } },
1197 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmul.d" } },
1198 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmul.s" } },
1199 } } },
1200 .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{
1201 .{ .value = 0x00000000, .then = .{ .instruction = .@"vffint.s.l" } },
1202 .{ .value = 0x00018000, .then = .{ .instruction = .@"vftint.w.d" } },
1203 .{ .value = 0x00020000, .then = .{ .instruction = .@"vftintrm.w.d" } },
1204 .{ .value = 0x00038000, .then = .{ .instruction = .@"vftintrne.w.d" } },
1205 .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintrp.w.d" } },
1206 .{ .value = 0x00030000, .then = .{ .instruction = .@"vftintrz.w.d" } },
1207 } } },
1208 .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{
1209 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmax.d" } },
1210 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmax.s" } },
1211 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmin.d" } },
1212 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmin.s" } },
1213 } } },
1214 .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{
1215 .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmaxa.d" } },
1216 .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmaxa.s" } },
1217 .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmina.d" } },
1218 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmina.s" } },
1219 } } },
1220 .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{
1221 .{ .value = 0x00020000, .then = .{ .instruction = .@"vfrstpi.b" } },
1222 .{ .value = 0x00028000, .then = .{ .instruction = .@"vfrstpi.h" } },
1223 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmepatmsk.v" } },
1224 } } },
1225 .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{
1226 .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.d.w" } },
1227 .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.h.b" } },
1228 .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.q.d" } },
1229 .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.w.h" } },
1230 .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.d.w" } },
1231 .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.h.b" } },
1232 .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.q.d" } },
1233 .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.w.h" } },
1234 } } },
1235 .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{
1236 .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.du.wu" } },
1237 .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.hu.bu" } },
1238 .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.qu.du" } },
1239 .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.wu.hu" } },
1240 .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.du.wu" } },
1241 .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.hu.bu" } },
1242 .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.qu.du" } },
1243 .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.wu.hu" } },
1244 } } },
1245 .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{
1246 .{ .value = 0x00000000, .then = .{ .instruction = .@"vilvh.b" } },
1247 .{ .value = 0x00018000, .then = .{ .instruction = .@"vilvh.d" } },
1248 .{ .value = 0x00008000, .then = .{ .instruction = .@"vilvh.h" } },
1249 .{ .value = 0x00010000, .then = .{ .instruction = .@"vilvh.w" } },
1250 .{ .value = 0x00020000, .then = .{ .instruction = .@"vpickev.b" } },
1251 .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickev.d" } },
1252 .{ .value = 0x00028000, .then = .{ .instruction = .@"vpickev.h" } },
1253 .{ .value = 0x00030000, .then = .{ .instruction = .@"vpickev.w" } },
1254 } } },
1255 .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{
1256 .{ .value = 0x00020000, .then = .{ .instruction = .@"vilvl.b" } },
1257 .{ .value = 0x00038000, .then = .{ .instruction = .@"vilvl.d" } },
1258 .{ .value = 0x00028000, .then = .{ .instruction = .@"vilvl.h" } },
1259 .{ .value = 0x00030000, .then = .{ .instruction = .@"vilvl.w" } },
1260 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpackod.b" } },
1261 .{ .value = 0x00018000, .then = .{ .instruction = .@"vpackod.d" } },
1262 .{ .value = 0x00008000, .then = .{ .instruction = .@"vpackod.h" } },
1263 .{ .value = 0x00010000, .then = .{ .instruction = .@"vpackod.w" } },
1264 } } },
1265 .{ .value = 0x02e80000, .then = .{ .mask = 0x0003c000, .cases = .{
1266 .{ .value = 0x00038000, .then = .{ .instruction = .@"vinsgr2vr.b" } },
1267 .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{
1268 .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{
1269 .{ .value = 0x00001000, .then = .{ .instruction = .@"vinsgr2vr.d" } },
1270 .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.w" } },
1271 } } },
1272 .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.h" } },
1273 } } },
1274 } } },
1275 .{ .value = 0x03e00000, .then = .{ .instruction = .vldi } },
1276 .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{
1277 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmadd.b" } },
1278 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmadd.d" } },
1279 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmadd.h" } },
1280 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmadd.w" } },
1281 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmsub.b" } },
1282 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmsub.d" } },
1283 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmsub.h" } },
1284 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmsub.w" } },
1285 } } },
1286 .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{
1287 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.w" } },
1288 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.b" } },
1289 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.d" } },
1290 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.h" } },
1291 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.w" } },
1292 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.b" } },
1293 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.d" } },
1294 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.h" } },
1295 } } },
1296 .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{
1297 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu" } },
1298 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu" } },
1299 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du" } },
1300 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu" } },
1301 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu" } },
1302 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu" } },
1303 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du" } },
1304 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu" } },
1305 } } },
1306 .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{
1307 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu.w" } },
1308 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu.b" } },
1309 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du.d" } },
1310 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu.h" } },
1311 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu.w" } },
1312 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu.b" } },
1313 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du.d" } },
1314 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu.h" } },
1315 } } },
1316 .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{
1317 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.b" } },
1318 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.d" } },
1319 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.h" } },
1320 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.w" } },
1321 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.b" } },
1322 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.d" } },
1323 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.h" } },
1324 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.w" } },
1325 } } },
1326 .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{
1327 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.bu" } },
1328 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.du" } },
1329 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.hu" } },
1330 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.wu" } },
1331 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.bu" } },
1332 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.du" } },
1333 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.hu" } },
1334 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.wu" } },
1335 } } },
1336 .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{
1337 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.b" } },
1338 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.d" } },
1339 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.h" } },
1340 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.w" } },
1341 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.b" } },
1342 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.d" } },
1343 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.h" } },
1344 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.w" } },
1345 } } },
1346 .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{
1347 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.bu" } },
1348 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.du" } },
1349 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.hu" } },
1350 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.wu" } },
1351 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.bu" } },
1352 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.du" } },
1353 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.hu" } },
1354 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.wu" } },
1355 } } },
1356 .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{
1357 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmuh.b" } },
1358 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmuh.d" } },
1359 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmuh.h" } },
1360 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmuh.w" } },
1361 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmul.b" } },
1362 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmul.d" } },
1363 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmul.h" } },
1364 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmul.w" } },
1365 } } },
1366 .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{
1367 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmuh.bu" } },
1368 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmuh.du" } },
1369 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmuh.hu" } },
1370 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmuh.wu" } },
1371 } } },
1372 .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{
1373 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.w" } },
1374 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.b" } },
1375 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.d" } },
1376 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.h" } },
1377 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.w" } },
1378 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.b" } },
1379 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.d" } },
1380 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.h" } },
1381 } } },
1382 .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{
1383 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu" } },
1384 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu" } },
1385 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du" } },
1386 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu" } },
1387 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu" } },
1388 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu" } },
1389 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du" } },
1390 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu" } },
1391 } } },
1392 .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{
1393 .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu.w" } },
1394 .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu.b" } },
1395 .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du.d" } },
1396 .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu.h" } },
1397 .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu.w" } },
1398 .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu.b" } },
1399 .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du.d" } },
1400 .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu.h" } },
1401 } } },
1402 .{ .value = 0x03dc0000, .then = .{ .instruction = .@"vnori.b" } },
1403 .{ .value = 0x03d40000, .then = .{ .instruction = .@"vori.b" } },
1404 .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{
1405 .{ .value = 0x00020000, .then = .{ .instruction = .@"vpackev.b" } },
1406 .{ .value = 0x00038000, .then = .{ .instruction = .@"vpackev.d" } },
1407 .{ .value = 0x00028000, .then = .{ .instruction = .@"vpackev.h" } },
1408 .{ .value = 0x00030000, .then = .{ .instruction = .@"vpackev.w" } },
1409 } } },
1410 .{ .value = 0x03e40000, .then = .{ .instruction = .@"vpermi.w" } },
1411 .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{
1412 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickod.b" } },
1413 .{ .value = 0x00018000, .then = .{ .instruction = .@"vpickod.d" } },
1414 .{ .value = 0x00008000, .then = .{ .instruction = .@"vpickod.h" } },
1415 .{ .value = 0x00010000, .then = .{ .instruction = .@"vpickod.w" } },
1416 .{ .value = 0x00020000, .then = .{ .instruction = .@"vreplve.b" } },
1417 .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplve.d" } },
1418 .{ .value = 0x00028000, .then = .{ .instruction = .@"vreplve.h" } },
1419 .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplve.w" } },
1420 } } },
1421 .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003c000, .cases = .{
1422 .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.b" } },
1423 .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{
1424 .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{
1425 .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.d" } },
1426 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.w" } },
1427 } } },
1428 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.h" } },
1429 } } },
1430 } } },
1431 .{ .value = 0x02f00000, .then = .{ .mask = 0x0003c000, .cases = .{
1432 .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.bu" } },
1433 .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{
1434 .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{
1435 .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.du" } },
1436 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.wu" } },
1437 } } },
1438 .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.hu" } },
1439 } } },
1440 } } },
1441 .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{
1442 .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplvei.b" } },
1443 .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{
1444 .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{
1445 .{ .value = 0x00001000, .then = .{ .instruction = .@"vreplvei.d" } },
1446 .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.w" } },
1447 } } },
1448 .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.h" } },
1449 } } },
1450 } } },
1451 .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{
1452 .{ .value = 0x00020000, .then = .{ .instruction = .@"vrotr.b" } },
1453 .{ .value = 0x00038000, .then = .{ .instruction = .@"vrotr.d" } },
1454 .{ .value = 0x00028000, .then = .{ .instruction = .@"vrotr.h" } },
1455 .{ .value = 0x00030000, .then = .{ .instruction = .@"vrotr.w" } },
1456 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsra.b" } },
1457 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsra.d" } },
1458 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsra.h" } },
1459 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsra.w" } },
1460 } } },
1461 .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{
1462 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1463 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1464 .{ .value = 0x00000000, .then = .{ .instruction = .@"vrotri.b" } },
1465 .{ .value = 0x00004000, .then = .{ .instruction = .@"vrotri.h" } },
1466 } } },
1467 .{ .value = 0x00008000, .then = .{ .instruction = .@"vrotri.w" } },
1468 } } },
1469 .{ .value = 0x00010000, .then = .{ .instruction = .@"vrotri.d" } },
1470 } } },
1471 .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{
1472 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.b" } },
1473 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.d" } },
1474 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.h" } },
1475 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.w" } },
1476 } } },
1477 .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{
1478 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.bu" } },
1479 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.du" } },
1480 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.hu" } },
1481 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.wu" } },
1482 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.b" } },
1483 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.d" } },
1484 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.h" } },
1485 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.w" } },
1486 } } },
1487 .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{
1488 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1489 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1490 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.b" } },
1491 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.h" } },
1492 } } },
1493 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.w" } },
1494 } } },
1495 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.d" } },
1496 } } },
1497 .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{
1498 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1499 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1500 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.bu" } },
1501 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.hu" } },
1502 } } },
1503 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.wu" } },
1504 } } },
1505 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.du" } },
1506 } } },
1507 .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{
1508 .{ .value = 0x00000000, .then = .{ .instruction = .@"vseq.b" } },
1509 .{ .value = 0x00018000, .then = .{ .instruction = .@"vseq.d" } },
1510 .{ .value = 0x00008000, .then = .{ .instruction = .@"vseq.h" } },
1511 .{ .value = 0x00010000, .then = .{ .instruction = .@"vseq.w" } },
1512 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsle.b" } },
1513 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsle.d" } },
1514 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsle.h" } },
1515 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsle.w" } },
1516 } } },
1517 .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{
1518 .{ .value = 0x00000000, .then = .{ .instruction = .@"vseqi.b" } },
1519 .{ .value = 0x00018000, .then = .{ .instruction = .@"vseqi.d" } },
1520 .{ .value = 0x00008000, .then = .{ .instruction = .@"vseqi.h" } },
1521 .{ .value = 0x00010000, .then = .{ .instruction = .@"vseqi.w" } },
1522 .{ .value = 0x00020000, .then = .{ .instruction = .@"vslei.b" } },
1523 .{ .value = 0x00038000, .then = .{ .instruction = .@"vslei.d" } },
1524 .{ .value = 0x00028000, .then = .{ .instruction = .@"vslei.h" } },
1525 .{ .value = 0x00030000, .then = .{ .instruction = .@"vslei.w" } },
1526 } } },
1527 .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{
1528 .{ .value = 0x00038000, .then = .{ .instruction = .@"vshuf.d" } },
1529 .{ .value = 0x00028000, .then = .{ .instruction = .@"vshuf.h" } },
1530 .{ .value = 0x00030000, .then = .{ .instruction = .@"vshuf.w" } },
1531 } } },
1532 .{ .value = 0x03900000, .then = .{ .instruction = .@"vshuf4i.b" } },
1533 .{ .value = 0x039c0000, .then = .{ .instruction = .@"vshuf4i.d" } },
1534 .{ .value = 0x03940000, .then = .{ .instruction = .@"vshuf4i.h" } },
1535 .{ .value = 0x03980000, .then = .{ .instruction = .@"vshuf4i.w" } },
1536 .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{
1537 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsle.bu" } },
1538 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsle.du" } },
1539 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsle.hu" } },
1540 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsle.wu" } },
1541 .{ .value = 0x00020000, .then = .{ .instruction = .@"vslt.b" } },
1542 .{ .value = 0x00038000, .then = .{ .instruction = .@"vslt.d" } },
1543 .{ .value = 0x00028000, .then = .{ .instruction = .@"vslt.h" } },
1544 .{ .value = 0x00030000, .then = .{ .instruction = .@"vslt.w" } },
1545 } } },
1546 .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{
1547 .{ .value = 0x00000000, .then = .{ .instruction = .@"vslei.bu" } },
1548 .{ .value = 0x00018000, .then = .{ .instruction = .@"vslei.du" } },
1549 .{ .value = 0x00008000, .then = .{ .instruction = .@"vslei.hu" } },
1550 .{ .value = 0x00010000, .then = .{ .instruction = .@"vslei.wu" } },
1551 .{ .value = 0x00020000, .then = .{ .instruction = .@"vslti.b" } },
1552 .{ .value = 0x00038000, .then = .{ .instruction = .@"vslti.d" } },
1553 .{ .value = 0x00028000, .then = .{ .instruction = .@"vslti.h" } },
1554 .{ .value = 0x00030000, .then = .{ .instruction = .@"vslti.w" } },
1555 } } },
1556 .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{
1557 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsll.b" } },
1558 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsll.d" } },
1559 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsll.h" } },
1560 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsll.w" } },
1561 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrl.b" } },
1562 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrl.d" } },
1563 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrl.h" } },
1564 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrl.w" } },
1565 } } },
1566 .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{
1567 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1568 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1569 .{ .value = 0x00000000, .then = .{ .instruction = .@"vslli.b" } },
1570 .{ .value = 0x00004000, .then = .{ .instruction = .@"vslli.h" } },
1571 } } },
1572 .{ .value = 0x00008000, .then = .{ .instruction = .@"vslli.w" } },
1573 } } },
1574 .{ .value = 0x00010000, .then = .{ .instruction = .@"vslli.d" } },
1575 } } },
1576 .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{
1577 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1578 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1579 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrai.b" } },
1580 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrai.h" } },
1581 } } },
1582 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrai.w" } },
1583 } } },
1584 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrai.d" } },
1585 } } },
1586 .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{
1587 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsran.b.h" } },
1588 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsran.h.w" } },
1589 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsran.w.d" } },
1590 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrln.b.h" } },
1591 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrln.h.w" } },
1592 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrln.w.d" } },
1593 } } },
1594 .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{
1595 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1596 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1597 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrani.b.h" } },
1598 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrani.h.w" } },
1599 } } },
1600 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrani.w.d" } },
1601 } } },
1602 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrani.d.q" } },
1603 } } },
1604 .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{
1605 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrar.b" } },
1606 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrar.d" } },
1607 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrar.h" } },
1608 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrar.w" } },
1609 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlr.b" } },
1610 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlr.d" } },
1611 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlr.h" } },
1612 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlr.w" } },
1613 } } },
1614 .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{
1615 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1616 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1617 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrari.b" } },
1618 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrari.h" } },
1619 } } },
1620 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrari.w" } },
1621 } } },
1622 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrari.d" } },
1623 } } },
1624 .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{
1625 .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrarn.b.h" } },
1626 .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrarn.h.w" } },
1627 .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrarn.w.d" } },
1628 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrn.b.h" } },
1629 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrn.h.w" } },
1630 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlrn.w.d" } },
1631 } } },
1632 .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{
1633 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1634 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1635 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrarni.b.h" } },
1636 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrarni.h.w" } },
1637 } } },
1638 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrarni.w.d" } },
1639 } } },
1640 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrarni.d.q" } },
1641 } } },
1642 .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{
1643 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1644 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1645 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrli.b" } },
1646 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrli.h" } },
1647 } } },
1648 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrli.w" } },
1649 } } },
1650 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrli.d" } },
1651 } } },
1652 .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{
1653 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1654 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1655 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlni.b.h" } },
1656 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlni.h.w" } },
1657 } } },
1658 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlni.w.d" } },
1659 } } },
1660 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlni.d.q" } },
1661 } } },
1662 .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{
1663 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1664 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
1665 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlri.b" } },
1666 .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrlri.h" } },
1667 } } },
1668 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlri.w" } },
1669 } } },
1670 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlri.d" } },
1671 } } },
1672 .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{
1673 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1674 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1675 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlrni.b.h" } },
1676 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrni.h.w" } },
1677 } } },
1678 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrni.w.d" } },
1679 } } },
1680 .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlrni.d.q" } },
1681 } } },
1682 .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{
1683 .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.b.h" } },
1684 .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.h.w" } },
1685 .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.w.d" } },
1686 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.b.h" } },
1687 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.h.w" } },
1688 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.w.d" } },
1689 } } },
1690 .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{
1691 .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.bu.h" } },
1692 .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.hu.w" } },
1693 .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.wu.d" } },
1694 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.bu.h" } },
1695 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.hu.w" } },
1696 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.wu.d" } },
1697 } } },
1698 .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{
1699 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1700 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1701 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.b.h" } },
1702 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.h.w" } },
1703 } } },
1704 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.w.d" } },
1705 } } },
1706 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.d.q" } },
1707 } } },
1708 .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{
1709 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1710 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1711 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.bu.h" } },
1712 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.hu.w" } },
1713 } } },
1714 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.wu.d" } },
1715 } } },
1716 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.du.q" } },
1717 } } },
1718 .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{
1719 .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.b.h" } },
1720 .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.h.w" } },
1721 .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.w.d" } },
1722 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.b.h" } },
1723 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.h.w" } },
1724 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.w.d" } },
1725 } } },
1726 .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{
1727 .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.bu.h" } },
1728 .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.hu.w" } },
1729 .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.wu.d" } },
1730 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.bu.h" } },
1731 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.hu.w" } },
1732 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.wu.d" } },
1733 } } },
1734 .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{
1735 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1736 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1737 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.b.h" } },
1738 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.h.w" } },
1739 } } },
1740 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.w.d" } },
1741 } } },
1742 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.d.q" } },
1743 } } },
1744 .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{
1745 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1746 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1747 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.bu.h" } },
1748 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.hu.w" } },
1749 } } },
1750 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.wu.d" } },
1751 } } },
1752 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.du.q" } },
1753 } } },
1754 .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{
1755 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1756 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1757 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.b.h" } },
1758 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.h.w" } },
1759 } } },
1760 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.w.d" } },
1761 } } },
1762 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.d.q" } },
1763 } } },
1764 .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{
1765 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1766 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1767 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.bu.h" } },
1768 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.hu.w" } },
1769 } } },
1770 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.wu.d" } },
1771 } } },
1772 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.du.q" } },
1773 } } },
1774 .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{
1775 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1776 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1777 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.b.h" } },
1778 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.h.w" } },
1779 } } },
1780 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.w.d" } },
1781 } } },
1782 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.d.q" } },
1783 } } },
1784 .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{
1785 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
1786 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
1787 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.bu.h" } },
1788 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.hu.w" } },
1789 } } },
1790 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.wu.d" } },
1791 } } },
1792 .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.du.q" } },
1793 } } },
1794 .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{
1795 .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.bu" } },
1796 .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.du" } },
1797 .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.hu" } },
1798 .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.wu" } },
1799 } } },
1800 .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{
1801 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsub.b" } },
1802 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.d" } },
1803 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsub.h" } },
1804 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsub.w" } },
1805 } } },
1806 .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{
1807 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.w" } },
1808 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.b" } },
1809 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.d" } },
1810 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.h" } },
1811 } } },
1812 .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{
1813 .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.wu" } },
1814 .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.bu" } },
1815 .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.du" } },
1816 .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.hu" } },
1817 } } },
1818 .{ .value = 0x03d80000, .then = .{ .instruction = .@"vxori.b" } },
1819 } } },
1820 .{ .value = 0x74000000, .then = .{ .mask = 0x03fc0000, .cases = .{
1821 .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{
1822 .{ .value = 0x00031800, .then = .{ .instruction = .@"vext2xv.d.b" } },
1823 .{ .value = 0x00032000, .then = .{ .instruction = .@"vext2xv.d.h" } },
1824 .{ .value = 0x00032400, .then = .{ .instruction = .@"vext2xv.d.w" } },
1825 .{ .value = 0x00033000, .then = .{ .instruction = .@"vext2xv.du.bu" } },
1826 .{ .value = 0x00033800, .then = .{ .instruction = .@"vext2xv.du.hu" } },
1827 .{ .value = 0x00033c00, .then = .{ .instruction = .@"vext2xv.du.wu" } },
1828 .{ .value = 0x00031000, .then = .{ .instruction = .@"vext2xv.h.b" } },
1829 .{ .value = 0x00032800, .then = .{ .instruction = .@"vext2xv.hu.bu" } },
1830 .{ .value = 0x00031400, .then = .{ .instruction = .@"vext2xv.w.b" } },
1831 .{ .value = 0x00031c00, .then = .{ .instruction = .@"vext2xv.w.h" } },
1832 .{ .value = 0x00032c00, .then = .{ .instruction = .@"vext2xv.wu.bu" } },
1833 .{ .value = 0x00033400, .then = .{ .instruction = .@"vext2xv.wu.hu" } },
1834 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvclo.b" } },
1835 .{ .value = 0x00000c00, .then = .{ .instruction = .@"xvclo.d" } },
1836 .{ .value = 0x00000400, .then = .{ .instruction = .@"xvclo.h" } },
1837 .{ .value = 0x00000800, .then = .{ .instruction = .@"xvclo.w" } },
1838 .{ .value = 0x00001000, .then = .{ .instruction = .@"xvclz.b" } },
1839 .{ .value = 0x00001c00, .then = .{ .instruction = .@"xvclz.d" } },
1840 .{ .value = 0x00001400, .then = .{ .instruction = .@"xvclz.h" } },
1841 .{ .value = 0x00001800, .then = .{ .instruction = .@"xvclz.w" } },
1842 .{ .value = 0x0002e800, .then = .{ .instruction = .@"xvexth.d.w" } },
1843 .{ .value = 0x0002f800, .then = .{ .instruction = .@"xvexth.du.wu" } },
1844 .{ .value = 0x0002e000, .then = .{ .instruction = .@"xvexth.h.b" } },
1845 .{ .value = 0x0002f000, .then = .{ .instruction = .@"xvexth.hu.bu" } },
1846 .{ .value = 0x0002ec00, .then = .{ .instruction = .@"xvexth.q.d" } },
1847 .{ .value = 0x0002fc00, .then = .{ .instruction = .@"xvexth.qu.du" } },
1848 .{ .value = 0x0002e400, .then = .{ .instruction = .@"xvexth.w.h" } },
1849 .{ .value = 0x0002f400, .then = .{ .instruction = .@"xvexth.wu.hu" } },
1850 .{ .value = 0x0000d800, .then = .{ .instruction = .@"xvfclass.d" } },
1851 .{ .value = 0x0000d400, .then = .{ .instruction = .@"xvfclass.s" } },
1852 .{ .value = 0x0001f400, .then = .{ .instruction = .@"xvfcvth.d.s" } },
1853 .{ .value = 0x0001ec00, .then = .{ .instruction = .@"xvfcvth.s.h" } },
1854 .{ .value = 0x0001f000, .then = .{ .instruction = .@"xvfcvtl.d.s" } },
1855 .{ .value = 0x0001e800, .then = .{ .instruction = .@"xvfcvtl.s.h" } },
1856 .{ .value = 0x00020800, .then = .{ .instruction = .@"xvffint.d.l" } },
1857 .{ .value = 0x00020c00, .then = .{ .instruction = .@"xvffint.d.lu" } },
1858 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvffint.s.w" } },
1859 .{ .value = 0x00020400, .then = .{ .instruction = .@"xvffint.s.wu" } },
1860 .{ .value = 0x00021400, .then = .{ .instruction = .@"xvffinth.d.w" } },
1861 .{ .value = 0x00021000, .then = .{ .instruction = .@"xvffintl.d.w" } },
1862 .{ .value = 0x0000c800, .then = .{ .instruction = .@"xvflogb.d" } },
1863 .{ .value = 0x0000c400, .then = .{ .instruction = .@"xvflogb.s" } },
1864 .{ .value = 0x0000f800, .then = .{ .instruction = .@"xvfrecip.d" } },
1865 .{ .value = 0x0000f400, .then = .{ .instruction = .@"xvfrecip.s" } },
1866 .{ .value = 0x00011800, .then = .{ .instruction = .@"xvfrecipe.d" } },
1867 .{ .value = 0x00011400, .then = .{ .instruction = .@"xvfrecipe.s" } },
1868 .{ .value = 0x00013800, .then = .{ .instruction = .@"xvfrint.d" } },
1869 .{ .value = 0x00013400, .then = .{ .instruction = .@"xvfrint.s" } },
1870 .{ .value = 0x00014800, .then = .{ .instruction = .@"xvfrintrm.d" } },
1871 .{ .value = 0x00014400, .then = .{ .instruction = .@"xvfrintrm.s" } },
1872 .{ .value = 0x00017800, .then = .{ .instruction = .@"xvfrintrne.d" } },
1873 .{ .value = 0x00017400, .then = .{ .instruction = .@"xvfrintrne.s" } },
1874 .{ .value = 0x00015800, .then = .{ .instruction = .@"xvfrintrp.d" } },
1875 .{ .value = 0x00015400, .then = .{ .instruction = .@"xvfrintrp.s" } },
1876 .{ .value = 0x00016800, .then = .{ .instruction = .@"xvfrintrz.d" } },
1877 .{ .value = 0x00016400, .then = .{ .instruction = .@"xvfrintrz.s" } },
1878 .{ .value = 0x00010800, .then = .{ .instruction = .@"xvfrsqrt.d" } },
1879 .{ .value = 0x00010400, .then = .{ .instruction = .@"xvfrsqrt.s" } },
1880 .{ .value = 0x00012800, .then = .{ .instruction = .@"xvfrsqrte.d" } },
1881 .{ .value = 0x00012400, .then = .{ .instruction = .@"xvfrsqrte.s" } },
1882 .{ .value = 0x0000e800, .then = .{ .instruction = .@"xvfsqrt.d" } },
1883 .{ .value = 0x0000e400, .then = .{ .instruction = .@"xvfsqrt.s" } },
1884 .{ .value = 0x00023400, .then = .{ .instruction = .@"xvftint.l.d" } },
1885 .{ .value = 0x00025c00, .then = .{ .instruction = .@"xvftint.lu.d" } },
1886 .{ .value = 0x00023000, .then = .{ .instruction = .@"xvftint.w.s" } },
1887 .{ .value = 0x00025800, .then = .{ .instruction = .@"xvftint.wu.s" } },
1888 .{ .value = 0x00028400, .then = .{ .instruction = .@"xvftinth.l.s" } },
1889 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintl.l.s" } },
1890 .{ .value = 0x00023c00, .then = .{ .instruction = .@"xvftintrm.l.d" } },
1891 .{ .value = 0x00023800, .then = .{ .instruction = .@"xvftintrm.w.s" } },
1892 .{ .value = 0x00028c00, .then = .{ .instruction = .@"xvftintrmh.l.s" } },
1893 .{ .value = 0x00028800, .then = .{ .instruction = .@"xvftintrml.l.s" } },
1894 .{ .value = 0x00025400, .then = .{ .instruction = .@"xvftintrne.l.d" } },
1895 .{ .value = 0x00025000, .then = .{ .instruction = .@"xvftintrne.w.s" } },
1896 .{ .value = 0x0002a400, .then = .{ .instruction = .@"xvftintrneh.l.s" } },
1897 .{ .value = 0x0002a000, .then = .{ .instruction = .@"xvftintrnel.l.s" } },
1898 .{ .value = 0x00024400, .then = .{ .instruction = .@"xvftintrp.l.d" } },
1899 .{ .value = 0x00024000, .then = .{ .instruction = .@"xvftintrp.w.s" } },
1900 .{ .value = 0x00029400, .then = .{ .instruction = .@"xvftintrph.l.s" } },
1901 .{ .value = 0x00029000, .then = .{ .instruction = .@"xvftintrpl.l.s" } },
1902 .{ .value = 0x00024c00, .then = .{ .instruction = .@"xvftintrz.l.d" } },
1903 .{ .value = 0x00027400, .then = .{ .instruction = .@"xvftintrz.lu.d" } },
1904 .{ .value = 0x00024800, .then = .{ .instruction = .@"xvftintrz.w.s" } },
1905 .{ .value = 0x00027000, .then = .{ .instruction = .@"xvftintrz.wu.s" } },
1906 .{ .value = 0x00029c00, .then = .{ .instruction = .@"xvftintrzh.l.s" } },
1907 .{ .value = 0x00029800, .then = .{ .instruction = .@"xvftintrzl.l.s" } },
1908 .{ .value = 0x00005000, .then = .{ .instruction = .@"xvmskgez.b" } },
1909 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvmskltz.b" } },
1910 .{ .value = 0x00004c00, .then = .{ .instruction = .@"xvmskltz.d" } },
1911 .{ .value = 0x00004400, .then = .{ .instruction = .@"xvmskltz.h" } },
1912 .{ .value = 0x00004800, .then = .{ .instruction = .@"xvmskltz.w" } },
1913 .{ .value = 0x00006000, .then = .{ .instruction = .@"xvmsknz.b" } },
1914 .{ .value = 0x00003000, .then = .{ .instruction = .@"xvneg.b" } },
1915 .{ .value = 0x00003c00, .then = .{ .instruction = .@"xvneg.d" } },
1916 .{ .value = 0x00003400, .then = .{ .instruction = .@"xvneg.h" } },
1917 .{ .value = 0x00003800, .then = .{ .instruction = .@"xvneg.w" } },
1918 .{ .value = 0x00002000, .then = .{ .instruction = .@"xvpcnt.b" } },
1919 .{ .value = 0x00002c00, .then = .{ .instruction = .@"xvpcnt.d" } },
1920 .{ .value = 0x00002400, .then = .{ .instruction = .@"xvpcnt.h" } },
1921 .{ .value = 0x00002800, .then = .{ .instruction = .@"xvpcnt.w" } },
1922 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplgr2vr.b" } },
1923 .{ .value = 0x00030c00, .then = .{ .instruction = .@"xvreplgr2vr.d" } },
1924 .{ .value = 0x00030400, .then = .{ .instruction = .@"xvreplgr2vr.h" } },
1925 .{ .value = 0x00030800, .then = .{ .instruction = .@"xvreplgr2vr.w" } },
1926 .{ .value = 0x0000b000, .then = .{ .instruction = .@"xvsetallnez.b" } },
1927 .{ .value = 0x0000bc00, .then = .{ .instruction = .@"xvsetallnez.d" } },
1928 .{ .value = 0x0000b400, .then = .{ .instruction = .@"xvsetallnez.h" } },
1929 .{ .value = 0x0000b800, .then = .{ .instruction = .@"xvsetallnez.w" } },
1930 .{ .value = 0x0000a000, .then = .{ .instruction = .@"xvsetanyeqz.b" } },
1931 .{ .value = 0x0000ac00, .then = .{ .instruction = .@"xvsetanyeqz.d" } },
1932 .{ .value = 0x0000a400, .then = .{ .instruction = .@"xvsetanyeqz.h" } },
1933 .{ .value = 0x0000a800, .then = .{ .instruction = .@"xvsetanyeqz.w" } },
1934 .{ .value = 0x00009800, .then = .{ .instruction = .@"xvseteqz.v" } },
1935 .{ .value = 0x00009c00, .then = .{ .instruction = .@"xvsetnez.v" } },
1936 } } },
1937 .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{
1938 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvabsd.b" } },
1939 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvabsd.bu" } },
1940 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvabsd.d" } },
1941 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvabsd.du" } },
1942 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvabsd.h" } },
1943 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvabsd.hu" } },
1944 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvabsd.w" } },
1945 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvabsd.wu" } },
1946 } } },
1947 .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{
1948 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvadd.b" } },
1949 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvadd.d" } },
1950 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvadd.h" } },
1951 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvadd.w" } },
1952 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslt.bu" } },
1953 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslt.du" } },
1954 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslt.hu" } },
1955 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslt.wu" } },
1956 } } },
1957 .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{
1958 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadd.q" } },
1959 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsigncov.b" } },
1960 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsigncov.d" } },
1961 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsigncov.h" } },
1962 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsigncov.w" } },
1963 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.q" } },
1964 } } },
1965 .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{
1966 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvadda.b" } },
1967 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvadda.d" } },
1968 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvadda.h" } },
1969 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadda.w" } },
1970 } } },
1971 .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{
1972 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddi.bu" } },
1973 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddi.du" } },
1974 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddi.hu" } },
1975 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddi.wu" } },
1976 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslti.bu" } },
1977 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslti.du" } },
1978 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslti.hu" } },
1979 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslti.wu" } },
1980 } } },
1981 .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{
1982 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.w" } },
1983 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.b" } },
1984 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.d" } },
1985 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.h" } },
1986 } } },
1987 .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{
1988 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu" } },
1989 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu" } },
1990 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du" } },
1991 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu" } },
1992 } } },
1993 .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{
1994 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu.w" } },
1995 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu.b" } },
1996 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du.d" } },
1997 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu.h" } },
1998 } } },
1999 .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{
2000 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.w" } },
2001 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.b" } },
2002 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.d" } },
2003 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.h" } },
2004 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.w" } },
2005 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.b" } },
2006 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.d" } },
2007 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.h" } },
2008 } } },
2009 .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{
2010 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.wu" } },
2011 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.bu" } },
2012 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.du" } },
2013 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.hu" } },
2014 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.wu" } },
2015 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.bu" } },
2016 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.du" } },
2017 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.hu" } },
2018 } } },
2019 .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{
2020 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvaddwod.d.wu.w" } },
2021 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvaddwod.h.bu.b" } },
2022 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvaddwod.q.du.d" } },
2023 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvaddwod.w.hu.h" } },
2024 } } },
2025 .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{
2026 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvand.v" } },
2027 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvnor.v" } },
2028 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvor.v" } },
2029 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvxor.v" } },
2030 } } },
2031 .{ .value = 0x03d00000, .then = .{ .instruction = .@"xvandi.b" } },
2032 .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{
2033 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvandn.v" } },
2034 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfrstp.b" } },
2035 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfrstp.h" } },
2036 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvorn.v" } },
2037 } } },
2038 .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{
2039 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavg.b" } },
2040 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavg.bu" } },
2041 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavg.d" } },
2042 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavg.du" } },
2043 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavg.h" } },
2044 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavg.hu" } },
2045 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavg.w" } },
2046 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavg.wu" } },
2047 } } },
2048 .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{
2049 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavgr.b" } },
2050 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavgr.bu" } },
2051 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavgr.d" } },
2052 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavgr.du" } },
2053 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavgr.h" } },
2054 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavgr.hu" } },
2055 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavgr.w" } },
2056 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavgr.wu" } },
2057 } } },
2058 .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{
2059 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclr.b" } },
2060 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitclr.d" } },
2061 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclr.h" } },
2062 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclr.w" } },
2063 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbitset.b" } },
2064 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvbitset.d" } },
2065 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbitset.h" } },
2066 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvbitset.w" } },
2067 } } },
2068 .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{
2069 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2070 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2071 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclri.b" } },
2072 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitclri.h" } },
2073 } } },
2074 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclri.w" } },
2075 } } },
2076 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclri.d" } },
2077 } } },
2078 .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{
2079 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrev.b" } },
2080 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitrev.d" } },
2081 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrev.h" } },
2082 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrev.w" } },
2083 } } },
2084 .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{
2085 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2086 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2087 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrevi.b" } },
2088 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitrevi.h" } },
2089 } } },
2090 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrevi.w" } },
2091 } } },
2092 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrevi.d" } },
2093 } } },
2094 .{ .value = 0x03c40000, .then = .{ .instruction = .@"xvbitseli.b" } },
2095 .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{
2096 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2097 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2098 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitseti.b" } },
2099 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitseti.h" } },
2100 } } },
2101 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitseti.w" } },
2102 } } },
2103 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitseti.d" } },
2104 } } },
2105 .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{
2106 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbsll.v" } },
2107 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbsrl.v" } },
2108 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubi.bu" } },
2109 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubi.du" } },
2110 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubi.hu" } },
2111 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubi.wu" } },
2112 } } },
2113 .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{
2114 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.b" } },
2115 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.d" } },
2116 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.h" } },
2117 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.w" } },
2118 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.b" } },
2119 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.d" } },
2120 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.h" } },
2121 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.w" } },
2122 } } },
2123 .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{
2124 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.bu" } },
2125 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.du" } },
2126 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.hu" } },
2127 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.wu" } },
2128 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.bu" } },
2129 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.du" } },
2130 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.hu" } },
2131 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.wu" } },
2132 } } },
2133 .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{
2134 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.q.d" } },
2135 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.d.w" } },
2136 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2137 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.h.b" } },
2138 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.w.h" } },
2139 } } },
2140 } } },
2141 .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{
2142 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.qu.du" } },
2143 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.du.wu" } },
2144 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2145 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.hu.bu" } },
2146 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.wu.hu" } },
2147 } } },
2148 } } },
2149 .{ .value = 0x038c0000, .then = .{ .instruction = .@"xvextrins.b" } },
2150 .{ .value = 0x03800000, .then = .{ .instruction = .@"xvextrins.d" } },
2151 .{ .value = 0x03880000, .then = .{ .instruction = .@"xvextrins.h" } },
2152 .{ .value = 0x03840000, .then = .{ .instruction = .@"xvextrins.w" } },
2153 .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{
2154 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfadd.d" } },
2155 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfadd.s" } },
2156 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfsub.d" } },
2157 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfsub.s" } },
2158 } } },
2159 .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{
2160 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcvt.h.s" } },
2161 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcvt.s.d" } },
2162 } } },
2163 .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{
2164 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfdiv.d" } },
2165 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfdiv.s" } },
2166 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmul.d" } },
2167 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmul.s" } },
2168 } } },
2169 .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{
2170 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvffint.s.l" } },
2171 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvftint.w.d" } },
2172 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvftintrm.w.d" } },
2173 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvftintrne.w.d" } },
2174 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintrp.w.d" } },
2175 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvftintrz.w.d" } },
2176 } } },
2177 .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{
2178 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmax.d" } },
2179 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmax.s" } },
2180 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmin.d" } },
2181 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmin.s" } },
2182 } } },
2183 .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{
2184 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmaxa.d" } },
2185 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmaxa.s" } },
2186 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmina.d" } },
2187 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmina.s" } },
2188 } } },
2189 .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{
2190 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfrstpi.b" } },
2191 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfrstpi.h" } },
2192 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmepatmsk.v" } },
2193 } } },
2194 .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{
2195 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.d.w" } },
2196 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.h.b" } },
2197 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.q.d" } },
2198 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.w.h" } },
2199 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.d.w" } },
2200 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.h.b" } },
2201 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.q.d" } },
2202 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.w.h" } },
2203 } } },
2204 .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{
2205 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.du.wu" } },
2206 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.hu.bu" } },
2207 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.qu.du" } },
2208 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.wu.hu" } },
2209 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.du.wu" } },
2210 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.hu.bu" } },
2211 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.qu.du" } },
2212 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.wu.hu" } },
2213 } } },
2214 .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{
2215 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvilvh.b" } },
2216 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvilvh.d" } },
2217 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvilvh.h" } },
2218 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvilvh.w" } },
2219 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpickev.b" } },
2220 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpickev.d" } },
2221 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpickev.h" } },
2222 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpickev.w" } },
2223 } } },
2224 .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{
2225 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvilvl.b" } },
2226 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvilvl.d" } },
2227 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvilvl.h" } },
2228 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvilvl.w" } },
2229 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpackod.b" } },
2230 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpackod.d" } },
2231 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpackod.h" } },
2232 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpackod.w" } },
2233 } } },
2234 .{ .value = 0x02e80000, .then = .{ .mask = 0x0003e000, .cases = .{
2235 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsgr2vr.d" } },
2236 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsgr2vr.w" } },
2237 } } },
2238 .{ .value = 0x02fc0000, .then = .{ .mask = 0x0003e000, .cases = .{
2239 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsve0.d" } },
2240 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsve0.w" } },
2241 } } },
2242 .{ .value = 0x03e00000, .then = .{ .instruction = .xvldi } },
2243 .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{
2244 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmadd.b" } },
2245 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmadd.d" } },
2246 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmadd.h" } },
2247 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmadd.w" } },
2248 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmsub.b" } },
2249 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmsub.d" } },
2250 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmsub.h" } },
2251 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmsub.w" } },
2252 } } },
2253 .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{
2254 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.w" } },
2255 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.b" } },
2256 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.d" } },
2257 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.h" } },
2258 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.w" } },
2259 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.b" } },
2260 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.d" } },
2261 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.h" } },
2262 } } },
2263 .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{
2264 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu" } },
2265 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu" } },
2266 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du" } },
2267 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu" } },
2268 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu" } },
2269 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu" } },
2270 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du" } },
2271 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu" } },
2272 } } },
2273 .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{
2274 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu.w" } },
2275 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu.b" } },
2276 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du.d" } },
2277 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu.h" } },
2278 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu.w" } },
2279 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu.b" } },
2280 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du.d" } },
2281 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu.h" } },
2282 } } },
2283 .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{
2284 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.b" } },
2285 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.d" } },
2286 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.h" } },
2287 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.w" } },
2288 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.b" } },
2289 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.d" } },
2290 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.h" } },
2291 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.w" } },
2292 } } },
2293 .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{
2294 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.bu" } },
2295 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.du" } },
2296 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.hu" } },
2297 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.wu" } },
2298 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.bu" } },
2299 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.du" } },
2300 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.hu" } },
2301 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.wu" } },
2302 } } },
2303 .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{
2304 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.b" } },
2305 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.d" } },
2306 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.h" } },
2307 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.w" } },
2308 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.b" } },
2309 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.d" } },
2310 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.h" } },
2311 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.w" } },
2312 } } },
2313 .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{
2314 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.bu" } },
2315 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.du" } },
2316 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.hu" } },
2317 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.wu" } },
2318 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.bu" } },
2319 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.du" } },
2320 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.hu" } },
2321 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.wu" } },
2322 } } },
2323 .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{
2324 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmuh.b" } },
2325 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmuh.d" } },
2326 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmuh.h" } },
2327 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmuh.w" } },
2328 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmul.b" } },
2329 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmul.d" } },
2330 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmul.h" } },
2331 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmul.w" } },
2332 } } },
2333 .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{
2334 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmuh.bu" } },
2335 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmuh.du" } },
2336 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmuh.hu" } },
2337 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmuh.wu" } },
2338 } } },
2339 .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{
2340 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.w" } },
2341 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.b" } },
2342 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.d" } },
2343 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.h" } },
2344 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.w" } },
2345 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.b" } },
2346 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.d" } },
2347 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.h" } },
2348 } } },
2349 .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{
2350 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu" } },
2351 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu" } },
2352 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du" } },
2353 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu" } },
2354 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu" } },
2355 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu" } },
2356 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du" } },
2357 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu" } },
2358 } } },
2359 .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{
2360 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu.w" } },
2361 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu.b" } },
2362 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du.d" } },
2363 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu.h" } },
2364 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu.w" } },
2365 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu.b" } },
2366 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du.d" } },
2367 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu.h" } },
2368 } } },
2369 .{ .value = 0x03dc0000, .then = .{ .instruction = .@"xvnori.b" } },
2370 .{ .value = 0x03d40000, .then = .{ .instruction = .@"xvori.b" } },
2371 .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{
2372 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpackev.b" } },
2373 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpackev.d" } },
2374 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpackev.h" } },
2375 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpackev.w" } },
2376 } } },
2377 .{ .value = 0x017c0000, .then = .{ .instruction = .@"xvperm.w" } },
2378 .{ .value = 0x03e80000, .then = .{ .instruction = .@"xvpermi.d" } },
2379 .{ .value = 0x03ec0000, .then = .{ .instruction = .@"xvpermi.q" } },
2380 .{ .value = 0x03e40000, .then = .{ .instruction = .@"xvpermi.w" } },
2381 .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{
2382 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpickod.b" } },
2383 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpickod.d" } },
2384 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpickod.h" } },
2385 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpickod.w" } },
2386 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvreplve.b" } },
2387 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve.d" } },
2388 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvreplve.h" } },
2389 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve.w" } },
2390 } } },
2391 .{ .value = 0x03000000, .then = .{ .mask = 0x0003e000, .cases = .{
2392 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve.d" } },
2393 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve.w" } },
2394 } } },
2395 .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003e000, .cases = .{
2396 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.d" } },
2397 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.w" } },
2398 } } },
2399 .{ .value = 0x02f00000, .then = .{ .mask = 0x0003e000, .cases = .{
2400 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.du" } },
2401 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.wu" } },
2402 } } },
2403 .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{
2404 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrepl128vei.b" } },
2405 .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{
2406 .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{
2407 .{ .value = 0x00001000, .then = .{ .instruction = .@"xvrepl128vei.d" } },
2408 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.w" } },
2409 } } },
2410 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.h" } },
2411 } } },
2412 } } },
2413 .{ .value = 0x03040000, .then = .{ .mask = 0x0003fc00, .cases = .{
2414 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve0.b" } },
2415 .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvreplve0.d" } },
2416 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve0.h" } },
2417 .{ .value = 0x0003f000, .then = .{ .instruction = .@"xvreplve0.q" } },
2418 .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvreplve0.w" } },
2419 } } },
2420 .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{
2421 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvrotr.b" } },
2422 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrotr.d" } },
2423 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvrotr.h" } },
2424 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvrotr.w" } },
2425 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsra.b" } },
2426 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsra.d" } },
2427 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsra.h" } },
2428 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsra.w" } },
2429 } } },
2430 .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{
2431 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2432 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2433 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrotri.b" } },
2434 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvrotri.h" } },
2435 } } },
2436 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvrotri.w" } },
2437 } } },
2438 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvrotri.d" } },
2439 } } },
2440 .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{
2441 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.b" } },
2442 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.d" } },
2443 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.h" } },
2444 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.w" } },
2445 } } },
2446 .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{
2447 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.bu" } },
2448 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.du" } },
2449 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.hu" } },
2450 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.wu" } },
2451 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.b" } },
2452 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.d" } },
2453 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.h" } },
2454 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.w" } },
2455 } } },
2456 .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{
2457 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2458 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2459 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.b" } },
2460 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.h" } },
2461 } } },
2462 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.w" } },
2463 } } },
2464 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.d" } },
2465 } } },
2466 .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{
2467 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2468 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2469 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.bu" } },
2470 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.hu" } },
2471 } } },
2472 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.wu" } },
2473 } } },
2474 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.du" } },
2475 } } },
2476 .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{
2477 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseq.b" } },
2478 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseq.d" } },
2479 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseq.h" } },
2480 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseq.w" } },
2481 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsle.b" } },
2482 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsle.d" } },
2483 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsle.h" } },
2484 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsle.w" } },
2485 } } },
2486 .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{
2487 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseqi.b" } },
2488 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseqi.d" } },
2489 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseqi.h" } },
2490 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseqi.w" } },
2491 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslei.b" } },
2492 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslei.d" } },
2493 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslei.h" } },
2494 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslei.w" } },
2495 } } },
2496 .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{
2497 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvshuf.d" } },
2498 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvshuf.h" } },
2499 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvshuf.w" } },
2500 } } },
2501 .{ .value = 0x03900000, .then = .{ .instruction = .@"xvshuf4i.b" } },
2502 .{ .value = 0x039c0000, .then = .{ .instruction = .@"xvshuf4i.d" } },
2503 .{ .value = 0x03940000, .then = .{ .instruction = .@"xvshuf4i.h" } },
2504 .{ .value = 0x03980000, .then = .{ .instruction = .@"xvshuf4i.w" } },
2505 .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{
2506 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsle.bu" } },
2507 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsle.du" } },
2508 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsle.hu" } },
2509 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsle.wu" } },
2510 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslt.b" } },
2511 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslt.d" } },
2512 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslt.h" } },
2513 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslt.w" } },
2514 } } },
2515 .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{
2516 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslei.bu" } },
2517 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslei.du" } },
2518 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslei.hu" } },
2519 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslei.wu" } },
2520 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslti.b" } },
2521 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslti.d" } },
2522 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslti.h" } },
2523 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslti.w" } },
2524 } } },
2525 .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{
2526 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsll.b" } },
2527 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsll.d" } },
2528 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsll.h" } },
2529 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsll.w" } },
2530 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrl.b" } },
2531 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrl.d" } },
2532 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrl.h" } },
2533 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrl.w" } },
2534 } } },
2535 .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{
2536 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2537 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2538 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslli.b" } },
2539 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvslli.h" } },
2540 } } },
2541 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslli.w" } },
2542 } } },
2543 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslli.d" } },
2544 } } },
2545 .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{
2546 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2547 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2548 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrai.b" } },
2549 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrai.h" } },
2550 } } },
2551 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrai.w" } },
2552 } } },
2553 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrai.d" } },
2554 } } },
2555 .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{
2556 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsran.b.h" } },
2557 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsran.h.w" } },
2558 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsran.w.d" } },
2559 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrln.b.h" } },
2560 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrln.h.w" } },
2561 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrln.w.d" } },
2562 } } },
2563 .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{
2564 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2565 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2566 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrani.b.h" } },
2567 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrani.h.w" } },
2568 } } },
2569 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrani.w.d" } },
2570 } } },
2571 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrani.d.q" } },
2572 } } },
2573 .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{
2574 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrar.b" } },
2575 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrar.d" } },
2576 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrar.h" } },
2577 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrar.w" } },
2578 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlr.b" } },
2579 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlr.d" } },
2580 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlr.h" } },
2581 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlr.w" } },
2582 } } },
2583 .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{
2584 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2585 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2586 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrari.b" } },
2587 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrari.h" } },
2588 } } },
2589 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrari.w" } },
2590 } } },
2591 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrari.d" } },
2592 } } },
2593 .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{
2594 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrarn.b.h" } },
2595 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrarn.h.w" } },
2596 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrarn.w.d" } },
2597 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrn.b.h" } },
2598 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrn.h.w" } },
2599 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlrn.w.d" } },
2600 } } },
2601 .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{
2602 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2603 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2604 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrarni.b.h" } },
2605 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrarni.h.w" } },
2606 } } },
2607 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrarni.w.d" } },
2608 } } },
2609 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrarni.d.q" } },
2610 } } },
2611 .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{
2612 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2613 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2614 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrli.b" } },
2615 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrli.h" } },
2616 } } },
2617 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrli.w" } },
2618 } } },
2619 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrli.d" } },
2620 } } },
2621 .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{
2622 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2623 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2624 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlni.b.h" } },
2625 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlni.h.w" } },
2626 } } },
2627 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlni.w.d" } },
2628 } } },
2629 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlni.d.q" } },
2630 } } },
2631 .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{
2632 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2633 .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{
2634 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlri.b" } },
2635 .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrlri.h" } },
2636 } } },
2637 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlri.w" } },
2638 } } },
2639 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlri.d" } },
2640 } } },
2641 .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{
2642 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2643 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2644 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlrni.b.h" } },
2645 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrni.h.w" } },
2646 } } },
2647 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrni.w.d" } },
2648 } } },
2649 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlrni.d.q" } },
2650 } } },
2651 .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{
2652 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.b.h" } },
2653 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.h.w" } },
2654 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.w.d" } },
2655 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.b.h" } },
2656 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.h.w" } },
2657 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.w.d" } },
2658 } } },
2659 .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{
2660 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.bu.h" } },
2661 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.hu.w" } },
2662 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.wu.d" } },
2663 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.bu.h" } },
2664 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.hu.w" } },
2665 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.wu.d" } },
2666 } } },
2667 .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{
2668 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2669 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2670 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.b.h" } },
2671 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.h.w" } },
2672 } } },
2673 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.w.d" } },
2674 } } },
2675 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.d.q" } },
2676 } } },
2677 .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{
2678 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2679 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2680 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.bu.h" } },
2681 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.hu.w" } },
2682 } } },
2683 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.wu.d" } },
2684 } } },
2685 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.du.q" } },
2686 } } },
2687 .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{
2688 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.b.h" } },
2689 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.h.w" } },
2690 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.w.d" } },
2691 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.b.h" } },
2692 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.h.w" } },
2693 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.w.d" } },
2694 } } },
2695 .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{
2696 .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.bu.h" } },
2697 .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.hu.w" } },
2698 .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.wu.d" } },
2699 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.bu.h" } },
2700 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.hu.w" } },
2701 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.wu.d" } },
2702 } } },
2703 .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{
2704 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2705 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2706 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.b.h" } },
2707 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.h.w" } },
2708 } } },
2709 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.w.d" } },
2710 } } },
2711 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.d.q" } },
2712 } } },
2713 .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{
2714 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2715 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2716 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.bu.h" } },
2717 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.hu.w" } },
2718 } } },
2719 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.wu.d" } },
2720 } } },
2721 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.du.q" } },
2722 } } },
2723 .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{
2724 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2725 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2726 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.b.h" } },
2727 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.h.w" } },
2728 } } },
2729 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.w.d" } },
2730 } } },
2731 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.d.q" } },
2732 } } },
2733 .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{
2734 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2735 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2736 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.bu.h" } },
2737 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.hu.w" } },
2738 } } },
2739 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.wu.d" } },
2740 } } },
2741 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.du.q" } },
2742 } } },
2743 .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{
2744 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2745 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2746 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.b.h" } },
2747 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.h.w" } },
2748 } } },
2749 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.w.d" } },
2750 } } },
2751 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.d.q" } },
2752 } } },
2753 .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{
2754 .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{
2755 .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{
2756 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.bu.h" } },
2757 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.hu.w" } },
2758 } } },
2759 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.wu.d" } },
2760 } } },
2761 .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.du.q" } },
2762 } } },
2763 .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{
2764 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.bu" } },
2765 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.du" } },
2766 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.hu" } },
2767 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.wu" } },
2768 } } },
2769 .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{
2770 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsub.b" } },
2771 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.d" } },
2772 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsub.h" } },
2773 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsub.w" } },
2774 } } },
2775 .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{
2776 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.w" } },
2777 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.b" } },
2778 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.d" } },
2779 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.h" } },
2780 } } },
2781 .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{
2782 .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.wu" } },
2783 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.bu" } },
2784 .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.du" } },
2785 .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.hu" } },
2786 } } },
2787 .{ .value = 0x03d80000, .then = .{ .instruction = .@"xvxori.b" } },
2788 } } },
2789 .{ .value = 0x30000000, .then = .{ .mask = 0x03800000, .cases = .{
2790 .{ .value = 0x00800000, .then = .{ .instruction = .@"vldrepl.b" } },
2791 .{ .value = 0x00000000, .then = .{ .mask = 0x00600000, .cases = .{
2792 .{ .value = 0x00000000, .then = .{ .instruction = .@"vldrepl.d" } },
2793 .{ .value = 0x00400000, .then = .{ .instruction = .@"vldrepl.h" } },
2794 .{ .value = 0x00200000, .then = .{ .instruction = .@"vldrepl.w" } },
2795 } } },
2796 .{ .value = 0x01800000, .then = .{ .instruction = .@"vstelm.b" } },
2797 .{ .value = 0x01000000, .then = .{ .mask = 0x00600000, .cases = .{
2798 .{ .value = 0x00000000, .then = .{ .instruction = .@"vstelm.d" } },
2799 .{ .value = 0x00400000, .then = .{ .instruction = .@"vstelm.h" } },
2800 .{ .value = 0x00200000, .then = .{ .instruction = .@"vstelm.w" } },
2801 } } },
2802 .{ .value = 0x02800000, .then = .{ .instruction = .@"xvldrepl.b" } },
2803 .{ .value = 0x02000000, .then = .{ .mask = 0x00600000, .cases = .{
2804 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvldrepl.d" } },
2805 .{ .value = 0x00400000, .then = .{ .instruction = .@"xvldrepl.h" } },
2806 .{ .value = 0x00200000, .then = .{ .instruction = .@"xvldrepl.w" } },
2807 } } },
2808 .{ .value = 0x03800000, .then = .{ .instruction = .@"xvstelm.b" } },
2809 .{ .value = 0x03000000, .then = .{ .mask = 0x00400000, .cases = .{
2810 .{ .value = 0x00000000, .then = .{ .mask = 0x00200000, .cases = .{
2811 .{ .value = 0x00000000, .then = .{ .instruction = .@"xvstelm.d" } },
2812 .{ .value = 0x00200000, .then = .{ .instruction = .@"xvstelm.w" } },
2813 } } },
2814 .{ .value = 0x00400000, .then = .{ .instruction = .@"xvstelm.h" } },
2815 } } },
2816 } } },
2817} }
src/codegen/loongarch/encoding.zig created+13695
...@@ -0,0 +1,13695 @@
1// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig.
2const Register = @import("bits.zig").Register;
3
4pub const Mnemonic = enum {
5 @"adc.b",
6 @"adc.d",
7 @"adc.h",
8 @"adc.w",
9 @"add.d",
10 @"add.w",
11 @"addi.d",
12 @"addi.w",
13 @"addu12i.d",
14 @"addu12i.w",
15 @"addu16i.d",
16 @"amadd.b",
17 @"amadd.d",
18 @"amadd.h",
19 @"amadd.w",
20 @"amadd_db.b",
21 @"amadd_db.d",
22 @"amadd_db.h",
23 @"amadd_db.w",
24 @"amand.d",
25 @"amand.w",
26 @"amand_db.d",
27 @"amand_db.w",
28 @"amcas.b",
29 @"amcas.d",
30 @"amcas.h",
31 @"amcas.w",
32 @"amcas_db.b",
33 @"amcas_db.d",
34 @"amcas_db.h",
35 @"amcas_db.w",
36 @"ammax.d",
37 @"ammax.du",
38 @"ammax.w",
39 @"ammax.wu",
40 @"ammax_db.d",
41 @"ammax_db.du",
42 @"ammax_db.w",
43 @"ammax_db.wu",
44 @"ammin.d",
45 @"ammin.du",
46 @"ammin.w",
47 @"ammin.wu",
48 @"ammin_db.d",
49 @"ammin_db.du",
50 @"ammin_db.w",
51 @"ammin_db.wu",
52 @"amor.d",
53 @"amor.w",
54 @"amor_db.d",
55 @"amor_db.w",
56 @"amswap.b",
57 @"amswap.d",
58 @"amswap.h",
59 @"amswap.w",
60 @"amswap_db.b",
61 @"amswap_db.d",
62 @"amswap_db.h",
63 @"amswap_db.w",
64 @"amxor.d",
65 @"amxor.w",
66 @"amxor_db.d",
67 @"amxor_db.w",
68 @"and",
69 andi,
70 andn,
71 @"armadc.w",
72 @"armadd.w",
73 @"armand.w",
74 armmfflag,
75 @"armmov.d",
76 @"armmov.w",
77 armmove,
78 armmtflag,
79 @"armnot.w",
80 @"armor.w",
81 @"armrotr.w",
82 @"armrotri.w",
83 @"armrrx.w",
84 @"armsbc.w",
85 armsetj,
86 @"armsll.w",
87 @"armslli.w",
88 @"armsra.w",
89 @"armsrai.w",
90 @"armsrl.w",
91 @"armsrli.w",
92 @"armsub.w",
93 @"armxor.w",
94 asrtgt,
95 asrtle,
96 b,
97 bceqz,
98 bcnez,
99 beq,
100 beqz,
101 bgt,
102 bgtu,
103 bl,
104 ble,
105 bleu,
106 bne,
107 bnez,
108 @"break",
109 @"bstrins.d",
110 @"bstrins.w",
111 @"bstrpick.d",
112 @"bstrpick.w",
113 cacop,
114 @"catpick.d",
115 @"catpick.w",
116 @"clo.d",
117 @"clo.w",
118 @"clz.d",
119 @"clz.w",
120 cpucfg,
121 @"crc.w.b.w",
122 @"crc.w.d.w",
123 @"crc.w.h.w",
124 @"crc.w.w.w",
125 @"crcc.w.b.w",
126 @"crcc.w.d.w",
127 @"crcc.w.h.w",
128 @"crcc.w.w.w",
129 csrrd,
130 csrwr,
131 csrxchg,
132 @"cto.d",
133 @"cto.w",
134 @"ctz.d",
135 @"ctz.w",
136 @"cu32i.d",
137 @"cu52i.d",
138 dbar,
139 dbgcall,
140 @"div.d",
141 @"div.du",
142 @"div.w",
143 @"div.wu",
144 eret,
145 @"fabs.d",
146 @"fabs.s",
147 @"fadd.d",
148 @"fadd.s",
149 @"fclass.d",
150 @"fclass.s",
151 @"fcmp.caf.d",
152 @"fcmp.caf.s",
153 @"fcmp.ceq.d",
154 @"fcmp.ceq.s",
155 @"fcmp.cle.d",
156 @"fcmp.cle.s",
157 @"fcmp.clt.d",
158 @"fcmp.clt.s",
159 @"fcmp.cne.d",
160 @"fcmp.cne.s",
161 @"fcmp.cor.d",
162 @"fcmp.cor.s",
163 @"fcmp.cueq.d",
164 @"fcmp.cueq.s",
165 @"fcmp.cule.d",
166 @"fcmp.cule.s",
167 @"fcmp.cult.d",
168 @"fcmp.cult.s",
169 @"fcmp.cun.d",
170 @"fcmp.cun.s",
171 @"fcmp.cune.d",
172 @"fcmp.cune.s",
173 @"fcmp.saf.d",
174 @"fcmp.saf.s",
175 @"fcmp.seq.d",
176 @"fcmp.seq.s",
177 @"fcmp.sle.d",
178 @"fcmp.sle.s",
179 @"fcmp.slt.d",
180 @"fcmp.slt.s",
181 @"fcmp.sne.d",
182 @"fcmp.sne.s",
183 @"fcmp.sor.d",
184 @"fcmp.sor.s",
185 @"fcmp.sueq.d",
186 @"fcmp.sueq.s",
187 @"fcmp.sule.d",
188 @"fcmp.sule.s",
189 @"fcmp.sult.d",
190 @"fcmp.sult.s",
191 @"fcmp.sun.d",
192 @"fcmp.sun.s",
193 @"fcmp.sune.d",
194 @"fcmp.sune.s",
195 @"fcopysign.d",
196 @"fcopysign.s",
197 fcsrrd,
198 fcsrwr,
199 @"fcvt.d.ld",
200 @"fcvt.d.s",
201 @"fcvt.ld.d",
202 @"fcvt.s.d",
203 @"fcvt.ud.d",
204 @"fdiv.d",
205 @"fdiv.s",
206 @"ffint.d.l",
207 @"ffint.d.w",
208 @"ffint.s.l",
209 @"ffint.s.w",
210 @"fld.d",
211 @"fld.s",
212 @"fldgt.d",
213 @"fldgt.s",
214 @"fldle.d",
215 @"fldle.s",
216 @"fldx.d",
217 @"fldx.s",
218 @"flogb.d",
219 @"flogb.s",
220 @"fmadd.d",
221 @"fmadd.s",
222 @"fmax.d",
223 @"fmax.s",
224 @"fmaxa.d",
225 @"fmaxa.s",
226 @"fmin.d",
227 @"fmin.s",
228 @"fmina.d",
229 @"fmina.s",
230 @"fmov.d",
231 @"fmov.s",
232 @"fmsub.d",
233 @"fmsub.s",
234 @"fmul.d",
235 @"fmul.s",
236 @"fneg.d",
237 @"fneg.s",
238 @"fnmadd.d",
239 @"fnmadd.s",
240 @"fnmsub.d",
241 @"fnmsub.s",
242 @"frecip.d",
243 @"frecip.s",
244 @"frecipe.d",
245 @"frecipe.s",
246 @"frint.d",
247 @"frint.s",
248 @"frsqrt.d",
249 @"frsqrt.s",
250 @"frsqrte.d",
251 @"frsqrte.s",
252 @"fscaleb.d",
253 @"fscaleb.s",
254 fsel,
255 @"fsqrt.d",
256 @"fsqrt.s",
257 @"fst.d",
258 @"fst.s",
259 @"fstgt.d",
260 @"fstgt.s",
261 @"fstle.d",
262 @"fstle.s",
263 @"fstx.d",
264 @"fstx.s",
265 @"fsub.d",
266 @"fsub.s",
267 @"ftint.l.d",
268 @"ftint.l.s",
269 @"ftint.w.d",
270 @"ftint.w.s",
271 @"ftintrm.l.d",
272 @"ftintrm.l.s",
273 @"ftintrm.w.d",
274 @"ftintrm.w.s",
275 @"ftintrne.l.d",
276 @"ftintrne.l.s",
277 @"ftintrne.w.d",
278 @"ftintrne.w.s",
279 @"ftintrp.l.d",
280 @"ftintrp.l.s",
281 @"ftintrp.w.d",
282 @"ftintrp.w.s",
283 @"ftintrz.l.d",
284 @"ftintrz.l.s",
285 @"ftintrz.w.d",
286 @"ftintrz.w.s",
287 gcsrrd,
288 gcsrwr,
289 gcsrxchg,
290 gtlbclr,
291 gtlbfill,
292 gtlbflush,
293 gtlbrd,
294 gtlbsrch,
295 gtlbwr,
296 hypcall,
297 ibar,
298 idle,
299 @"iocsrrd.b",
300 @"iocsrrd.d",
301 @"iocsrrd.h",
302 @"iocsrrd.w",
303 @"iocsrwr.b",
304 @"iocsrwr.d",
305 @"iocsrwr.h",
306 @"iocsrwr.w",
307 jirl,
308 jiscr0,
309 jiscr1,
310 @"ld.b",
311 @"ld.bu",
312 @"ld.d",
313 @"ld.h",
314 @"ld.hu",
315 @"ld.w",
316 @"ld.wu",
317 lddir,
318 @"ldgt.b",
319 @"ldgt.d",
320 @"ldgt.h",
321 @"ldgt.w",
322 @"ldl.d",
323 @"ldl.w",
324 @"ldle.b",
325 @"ldle.d",
326 @"ldle.h",
327 @"ldle.w",
328 @"ldox4.d",
329 @"ldox4.w",
330 ldpte,
331 @"ldr.d",
332 @"ldr.w",
333 @"ldx.b",
334 @"ldx.bu",
335 @"ldx.d",
336 @"ldx.h",
337 @"ldx.hu",
338 @"ldx.w",
339 @"ldx.wu",
340 @"ll.d",
341 @"ll.w",
342 @"llacq.d",
343 @"llacq.w",
344 @"lu12i.w",
345 maskeqz,
346 masknez,
347 @"mod.d",
348 @"mod.du",
349 @"mod.w",
350 @"mod.wu",
351 movfcc2fr,
352 movfcc2gr,
353 movfr2fcc,
354 @"movfr2gr.d",
355 @"movfr2gr.s",
356 @"movfrh2gr.s",
357 movgr2fcc,
358 @"movgr2fr.d",
359 @"movgr2fr.w",
360 @"movgr2frh.w",
361 movgr2scr,
362 movscr2gr,
363 @"mul.d",
364 @"mul.w",
365 @"mulh.d",
366 @"mulh.du",
367 @"mulh.w",
368 @"mulh.wu",
369 @"mulw.d.w",
370 @"mulw.d.wu",
371 nor,
372 @"or",
373 ori,
374 orn,
375 pcaddu12i,
376 pcaddu18i,
377 pcaddu2i,
378 pcalau12i,
379 preld,
380 preldx,
381 @"rcr.b",
382 @"rcr.d",
383 @"rcr.h",
384 @"rcr.w",
385 @"rcri.b",
386 @"rcri.d",
387 @"rcri.h",
388 @"rcri.w",
389 @"rdtime.d",
390 @"rdtimeh.w",
391 @"rdtimel.w",
392 @"revb.2h",
393 @"revb.2w",
394 @"revb.4h",
395 @"revb.d",
396 @"revbit.4b",
397 @"revbit.8b",
398 @"revbit.d",
399 @"revbit.w",
400 @"revh.2w",
401 @"revh.d",
402 @"rotr.b",
403 @"rotr.d",
404 @"rotr.h",
405 @"rotr.w",
406 @"rotri.b",
407 @"rotri.d",
408 @"rotri.h",
409 @"rotri.w",
410 @"sbc.b",
411 @"sbc.d",
412 @"sbc.h",
413 @"sbc.w",
414 @"sc.d",
415 @"sc.q",
416 @"sc.w",
417 @"screl.d",
418 @"screl.w",
419 @"sext.b",
420 @"sext.h",
421 @"sladd.d",
422 @"sladd.w",
423 @"sladd.wu",
424 @"sll.d",
425 @"sll.w",
426 @"slli.d",
427 @"slli.w",
428 slt,
429 slti,
430 sltu,
431 sltui,
432 @"sra.d",
433 @"sra.w",
434 @"srai.d",
435 @"srai.w",
436 @"srl.d",
437 @"srl.w",
438 @"srli.d",
439 @"srli.w",
440 @"st.b",
441 @"st.d",
442 @"st.h",
443 @"st.w",
444 @"stgt.b",
445 @"stgt.d",
446 @"stgt.h",
447 @"stgt.w",
448 @"stl.d",
449 @"stl.w",
450 @"stle.b",
451 @"stle.d",
452 @"stle.h",
453 @"stle.w",
454 @"stox4.d",
455 @"stox4.w",
456 @"str.d",
457 @"str.w",
458 @"stx.b",
459 @"stx.d",
460 @"stx.h",
461 @"stx.w",
462 @"sub.d",
463 @"sub.w",
464 syscall,
465 tlbclr,
466 tlbfill,
467 tlbflush,
468 tlbinv,
469 tlbrd,
470 tlbsrch,
471 tlbwr,
472 @"vabsd.b",
473 @"vabsd.bu",
474 @"vabsd.d",
475 @"vabsd.du",
476 @"vabsd.h",
477 @"vabsd.hu",
478 @"vabsd.w",
479 @"vabsd.wu",
480 @"vadd.b",
481 @"vadd.d",
482 @"vadd.h",
483 @"vadd.q",
484 @"vadd.w",
485 @"vadda.b",
486 @"vadda.d",
487 @"vadda.h",
488 @"vadda.w",
489 @"vaddi.bu",
490 @"vaddi.du",
491 @"vaddi.hu",
492 @"vaddi.wu",
493 @"vaddwev.d.w",
494 @"vaddwev.d.wu",
495 @"vaddwev.d.wu.w",
496 @"vaddwev.h.b",
497 @"vaddwev.h.bu",
498 @"vaddwev.h.bu.b",
499 @"vaddwev.q.d",
500 @"vaddwev.q.du",
501 @"vaddwev.q.du.d",
502 @"vaddwev.w.h",
503 @"vaddwev.w.hu",
504 @"vaddwev.w.hu.h",
505 @"vaddwod.d.w",
506 @"vaddwod.d.wu",
507 @"vaddwod.d.wu.w",
508 @"vaddwod.h.b",
509 @"vaddwod.h.bu",
510 @"vaddwod.h.bu.b",
511 @"vaddwod.q.d",
512 @"vaddwod.q.du",
513 @"vaddwod.q.du.d",
514 @"vaddwod.w.h",
515 @"vaddwod.w.hu",
516 @"vaddwod.w.hu.h",
517 @"vand.v",
518 @"vandi.b",
519 @"vandn.v",
520 @"vavg.b",
521 @"vavg.bu",
522 @"vavg.d",
523 @"vavg.du",
524 @"vavg.h",
525 @"vavg.hu",
526 @"vavg.w",
527 @"vavg.wu",
528 @"vavgr.b",
529 @"vavgr.bu",
530 @"vavgr.d",
531 @"vavgr.du",
532 @"vavgr.h",
533 @"vavgr.hu",
534 @"vavgr.w",
535 @"vavgr.wu",
536 @"vbitclr.b",
537 @"vbitclr.d",
538 @"vbitclr.h",
539 @"vbitclr.w",
540 @"vbitclri.b",
541 @"vbitclri.d",
542 @"vbitclri.h",
543 @"vbitclri.w",
544 @"vbitrev.b",
545 @"vbitrev.d",
546 @"vbitrev.h",
547 @"vbitrev.w",
548 @"vbitrevi.b",
549 @"vbitrevi.d",
550 @"vbitrevi.h",
551 @"vbitrevi.w",
552 @"vbitsel.v",
553 @"vbitseli.b",
554 @"vbitset.b",
555 @"vbitset.d",
556 @"vbitset.h",
557 @"vbitset.w",
558 @"vbitseti.b",
559 @"vbitseti.d",
560 @"vbitseti.h",
561 @"vbitseti.w",
562 @"vbsll.v",
563 @"vbsrl.v",
564 @"vclo.b",
565 @"vclo.d",
566 @"vclo.h",
567 @"vclo.w",
568 @"vclz.b",
569 @"vclz.d",
570 @"vclz.h",
571 @"vclz.w",
572 @"vdiv.b",
573 @"vdiv.bu",
574 @"vdiv.d",
575 @"vdiv.du",
576 @"vdiv.h",
577 @"vdiv.hu",
578 @"vdiv.w",
579 @"vdiv.wu",
580 @"vext2xv.d.b",
581 @"vext2xv.d.h",
582 @"vext2xv.d.w",
583 @"vext2xv.du.bu",
584 @"vext2xv.du.hu",
585 @"vext2xv.du.wu",
586 @"vext2xv.h.b",
587 @"vext2xv.hu.bu",
588 @"vext2xv.w.b",
589 @"vext2xv.w.h",
590 @"vext2xv.wu.bu",
591 @"vext2xv.wu.hu",
592 @"vexth.d.w",
593 @"vexth.du.wu",
594 @"vexth.h.b",
595 @"vexth.hu.bu",
596 @"vexth.q.d",
597 @"vexth.qu.du",
598 @"vexth.w.h",
599 @"vexth.wu.hu",
600 @"vextl.q.d",
601 @"vextl.qu.du",
602 @"vextrins.b",
603 @"vextrins.d",
604 @"vextrins.h",
605 @"vextrins.w",
606 @"vfadd.d",
607 @"vfadd.s",
608 @"vfclass.d",
609 @"vfclass.s",
610 @"vfcmp.caf.d",
611 @"vfcmp.caf.s",
612 @"vfcmp.ceq.d",
613 @"vfcmp.ceq.s",
614 @"vfcmp.cle.d",
615 @"vfcmp.cle.s",
616 @"vfcmp.clt.d",
617 @"vfcmp.clt.s",
618 @"vfcmp.cne.d",
619 @"vfcmp.cne.s",
620 @"vfcmp.cor.d",
621 @"vfcmp.cor.s",
622 @"vfcmp.cueq.d",
623 @"vfcmp.cueq.s",
624 @"vfcmp.cule.d",
625 @"vfcmp.cule.s",
626 @"vfcmp.cult.d",
627 @"vfcmp.cult.s",
628 @"vfcmp.cun.d",
629 @"vfcmp.cun.s",
630 @"vfcmp.cune.d",
631 @"vfcmp.cune.s",
632 @"vfcmp.saf.d",
633 @"vfcmp.saf.s",
634 @"vfcmp.seq.d",
635 @"vfcmp.seq.s",
636 @"vfcmp.sle.d",
637 @"vfcmp.sle.s",
638 @"vfcmp.slt.d",
639 @"vfcmp.slt.s",
640 @"vfcmp.sne.d",
641 @"vfcmp.sne.s",
642 @"vfcmp.sor.d",
643 @"vfcmp.sor.s",
644 @"vfcmp.sueq.d",
645 @"vfcmp.sueq.s",
646 @"vfcmp.sule.d",
647 @"vfcmp.sule.s",
648 @"vfcmp.sult.d",
649 @"vfcmp.sult.s",
650 @"vfcmp.sun.d",
651 @"vfcmp.sun.s",
652 @"vfcmp.sune.d",
653 @"vfcmp.sune.s",
654 @"vfcvt.h.s",
655 @"vfcvt.s.d",
656 @"vfcvth.d.s",
657 @"vfcvth.s.h",
658 @"vfcvtl.d.s",
659 @"vfcvtl.s.h",
660 @"vfdiv.d",
661 @"vfdiv.s",
662 @"vffint.d.l",
663 @"vffint.d.lu",
664 @"vffint.s.l",
665 @"vffint.s.w",
666 @"vffint.s.wu",
667 @"vffinth.d.w",
668 @"vffintl.d.w",
669 @"vflogb.d",
670 @"vflogb.s",
671 @"vfmadd.d",
672 @"vfmadd.s",
673 @"vfmax.d",
674 @"vfmax.s",
675 @"vfmaxa.d",
676 @"vfmaxa.s",
677 @"vfmin.d",
678 @"vfmin.s",
679 @"vfmina.d",
680 @"vfmina.s",
681 @"vfmsub.d",
682 @"vfmsub.s",
683 @"vfmul.d",
684 @"vfmul.s",
685 @"vfnmadd.d",
686 @"vfnmadd.s",
687 @"vfnmsub.d",
688 @"vfnmsub.s",
689 @"vfrecip.d",
690 @"vfrecip.s",
691 @"vfrecipe.d",
692 @"vfrecipe.s",
693 @"vfrint.d",
694 @"vfrint.s",
695 @"vfrintrm.d",
696 @"vfrintrm.s",
697 @"vfrintrne.d",
698 @"vfrintrne.s",
699 @"vfrintrp.d",
700 @"vfrintrp.s",
701 @"vfrintrz.d",
702 @"vfrintrz.s",
703 @"vfrsqrt.d",
704 @"vfrsqrt.s",
705 @"vfrsqrte.d",
706 @"vfrsqrte.s",
707 @"vfrstp.b",
708 @"vfrstp.h",
709 @"vfrstpi.b",
710 @"vfrstpi.h",
711 @"vfsqrt.d",
712 @"vfsqrt.s",
713 @"vfsub.d",
714 @"vfsub.s",
715 @"vftint.l.d",
716 @"vftint.lu.d",
717 @"vftint.w.d",
718 @"vftint.w.s",
719 @"vftint.wu.s",
720 @"vftinth.l.s",
721 @"vftintl.l.s",
722 @"vftintrm.l.d",
723 @"vftintrm.w.d",
724 @"vftintrm.w.s",
725 @"vftintrmh.l.s",
726 @"vftintrml.l.s",
727 @"vftintrne.l.d",
728 @"vftintrne.w.d",
729 @"vftintrne.w.s",
730 @"vftintrneh.l.s",
731 @"vftintrnel.l.s",
732 @"vftintrp.l.d",
733 @"vftintrp.w.d",
734 @"vftintrp.w.s",
735 @"vftintrph.l.s",
736 @"vftintrpl.l.s",
737 @"vftintrz.l.d",
738 @"vftintrz.lu.d",
739 @"vftintrz.w.d",
740 @"vftintrz.w.s",
741 @"vftintrz.wu.s",
742 @"vftintrzh.l.s",
743 @"vftintrzl.l.s",
744 @"vhaddw.d.w",
745 @"vhaddw.du.wu",
746 @"vhaddw.h.b",
747 @"vhaddw.hu.bu",
748 @"vhaddw.q.d",
749 @"vhaddw.qu.du",
750 @"vhaddw.w.h",
751 @"vhaddw.wu.hu",
752 @"vhsubw.d.w",
753 @"vhsubw.du.wu",
754 @"vhsubw.h.b",
755 @"vhsubw.hu.bu",
756 @"vhsubw.q.d",
757 @"vhsubw.qu.du",
758 @"vhsubw.w.h",
759 @"vhsubw.wu.hu",
760 @"vilvh.b",
761 @"vilvh.d",
762 @"vilvh.h",
763 @"vilvh.w",
764 @"vilvl.b",
765 @"vilvl.d",
766 @"vilvl.h",
767 @"vilvl.w",
768 @"vinsgr2vr.b",
769 @"vinsgr2vr.d",
770 @"vinsgr2vr.h",
771 @"vinsgr2vr.w",
772 vld,
773 vldi,
774 @"vldrepl.b",
775 @"vldrepl.d",
776 @"vldrepl.h",
777 @"vldrepl.w",
778 vldx,
779 @"vmadd.b",
780 @"vmadd.d",
781 @"vmadd.h",
782 @"vmadd.w",
783 @"vmaddwev.d.w",
784 @"vmaddwev.d.wu",
785 @"vmaddwev.d.wu.w",
786 @"vmaddwev.h.b",
787 @"vmaddwev.h.bu",
788 @"vmaddwev.h.bu.b",
789 @"vmaddwev.q.d",
790 @"vmaddwev.q.du",
791 @"vmaddwev.q.du.d",
792 @"vmaddwev.w.h",
793 @"vmaddwev.w.hu",
794 @"vmaddwev.w.hu.h",
795 @"vmaddwod.d.w",
796 @"vmaddwod.d.wu",
797 @"vmaddwod.d.wu.w",
798 @"vmaddwod.h.b",
799 @"vmaddwod.h.bu",
800 @"vmaddwod.h.bu.b",
801 @"vmaddwod.q.d",
802 @"vmaddwod.q.du",
803 @"vmaddwod.q.du.d",
804 @"vmaddwod.w.h",
805 @"vmaddwod.w.hu",
806 @"vmaddwod.w.hu.h",
807 @"vmax.b",
808 @"vmax.bu",
809 @"vmax.d",
810 @"vmax.du",
811 @"vmax.h",
812 @"vmax.hu",
813 @"vmax.w",
814 @"vmax.wu",
815 @"vmaxi.b",
816 @"vmaxi.bu",
817 @"vmaxi.d",
818 @"vmaxi.du",
819 @"vmaxi.h",
820 @"vmaxi.hu",
821 @"vmaxi.w",
822 @"vmaxi.wu",
823 @"vmepatmsk.v",
824 @"vmin.b",
825 @"vmin.bu",
826 @"vmin.d",
827 @"vmin.du",
828 @"vmin.h",
829 @"vmin.hu",
830 @"vmin.w",
831 @"vmin.wu",
832 @"vmini.b",
833 @"vmini.bu",
834 @"vmini.d",
835 @"vmini.du",
836 @"vmini.h",
837 @"vmini.hu",
838 @"vmini.w",
839 @"vmini.wu",
840 @"vmod.b",
841 @"vmod.bu",
842 @"vmod.d",
843 @"vmod.du",
844 @"vmod.h",
845 @"vmod.hu",
846 @"vmod.w",
847 @"vmod.wu",
848 @"vmskgez.b",
849 @"vmskltz.b",
850 @"vmskltz.d",
851 @"vmskltz.h",
852 @"vmskltz.w",
853 @"vmsknz.b",
854 @"vmsub.b",
855 @"vmsub.d",
856 @"vmsub.h",
857 @"vmsub.w",
858 @"vmuh.b",
859 @"vmuh.bu",
860 @"vmuh.d",
861 @"vmuh.du",
862 @"vmuh.h",
863 @"vmuh.hu",
864 @"vmuh.w",
865 @"vmuh.wu",
866 @"vmul.b",
867 @"vmul.d",
868 @"vmul.h",
869 @"vmul.w",
870 @"vmulwev.d.w",
871 @"vmulwev.d.wu",
872 @"vmulwev.d.wu.w",
873 @"vmulwev.h.b",
874 @"vmulwev.h.bu",
875 @"vmulwev.h.bu.b",
876 @"vmulwev.q.d",
877 @"vmulwev.q.du",
878 @"vmulwev.q.du.d",
879 @"vmulwev.w.h",
880 @"vmulwev.w.hu",
881 @"vmulwev.w.hu.h",
882 @"vmulwod.d.w",
883 @"vmulwod.d.wu",
884 @"vmulwod.d.wu.w",
885 @"vmulwod.h.b",
886 @"vmulwod.h.bu",
887 @"vmulwod.h.bu.b",
888 @"vmulwod.q.d",
889 @"vmulwod.q.du",
890 @"vmulwod.q.du.d",
891 @"vmulwod.w.h",
892 @"vmulwod.w.hu",
893 @"vmulwod.w.hu.h",
894 @"vneg.b",
895 @"vneg.d",
896 @"vneg.h",
897 @"vneg.w",
898 @"vnor.v",
899 @"vnori.b",
900 @"vor.v",
901 @"vori.b",
902 @"vorn.v",
903 @"vpackev.b",
904 @"vpackev.d",
905 @"vpackev.h",
906 @"vpackev.w",
907 @"vpackod.b",
908 @"vpackod.d",
909 @"vpackod.h",
910 @"vpackod.w",
911 @"vpcnt.b",
912 @"vpcnt.d",
913 @"vpcnt.h",
914 @"vpcnt.w",
915 @"vpermi.w",
916 @"vpickev.b",
917 @"vpickev.d",
918 @"vpickev.h",
919 @"vpickev.w",
920 @"vpickod.b",
921 @"vpickod.d",
922 @"vpickod.h",
923 @"vpickod.w",
924 @"vpickve2gr.b",
925 @"vpickve2gr.bu",
926 @"vpickve2gr.d",
927 @"vpickve2gr.du",
928 @"vpickve2gr.h",
929 @"vpickve2gr.hu",
930 @"vpickve2gr.w",
931 @"vpickve2gr.wu",
932 @"vreplgr2vr.b",
933 @"vreplgr2vr.d",
934 @"vreplgr2vr.h",
935 @"vreplgr2vr.w",
936 @"vreplve.b",
937 @"vreplve.d",
938 @"vreplve.h",
939 @"vreplve.w",
940 @"vreplvei.b",
941 @"vreplvei.d",
942 @"vreplvei.h",
943 @"vreplvei.w",
944 @"vrotr.b",
945 @"vrotr.d",
946 @"vrotr.h",
947 @"vrotr.w",
948 @"vrotri.b",
949 @"vrotri.d",
950 @"vrotri.h",
951 @"vrotri.w",
952 @"vsadd.b",
953 @"vsadd.bu",
954 @"vsadd.d",
955 @"vsadd.du",
956 @"vsadd.h",
957 @"vsadd.hu",
958 @"vsadd.w",
959 @"vsadd.wu",
960 @"vsat.b",
961 @"vsat.bu",
962 @"vsat.d",
963 @"vsat.du",
964 @"vsat.h",
965 @"vsat.hu",
966 @"vsat.w",
967 @"vsat.wu",
968 @"vseq.b",
969 @"vseq.d",
970 @"vseq.h",
971 @"vseq.w",
972 @"vseqi.b",
973 @"vseqi.d",
974 @"vseqi.h",
975 @"vseqi.w",
976 @"vsetallnez.b",
977 @"vsetallnez.d",
978 @"vsetallnez.h",
979 @"vsetallnez.w",
980 @"vsetanyeqz.b",
981 @"vsetanyeqz.d",
982 @"vsetanyeqz.h",
983 @"vsetanyeqz.w",
984 @"vseteqz.v",
985 @"vsetnez.v",
986 @"vshuf.b",
987 @"vshuf.d",
988 @"vshuf.h",
989 @"vshuf.w",
990 @"vshuf4i.b",
991 @"vshuf4i.d",
992 @"vshuf4i.h",
993 @"vshuf4i.w",
994 @"vsigncov.b",
995 @"vsigncov.d",
996 @"vsigncov.h",
997 @"vsigncov.w",
998 @"vsle.b",
999 @"vsle.bu",
1000 @"vsle.d",
1001 @"vsle.du",
1002 @"vsle.h",
1003 @"vsle.hu",
1004 @"vsle.w",
1005 @"vsle.wu",
1006 @"vslei.b",
1007 @"vslei.bu",
1008 @"vslei.d",
1009 @"vslei.du",
1010 @"vslei.h",
1011 @"vslei.hu",
1012 @"vslei.w",
1013 @"vslei.wu",
1014 @"vsll.b",
1015 @"vsll.d",
1016 @"vsll.h",
1017 @"vsll.w",
1018 @"vslli.b",
1019 @"vslli.d",
1020 @"vslli.h",
1021 @"vslli.w",
1022 @"vsllwil.d.w",
1023 @"vsllwil.du.wu",
1024 @"vsllwil.h.b",
1025 @"vsllwil.hu.bu",
1026 @"vsllwil.w.h",
1027 @"vsllwil.wu.hu",
1028 @"vslt.b",
1029 @"vslt.bu",
1030 @"vslt.d",
1031 @"vslt.du",
1032 @"vslt.h",
1033 @"vslt.hu",
1034 @"vslt.w",
1035 @"vslt.wu",
1036 @"vslti.b",
1037 @"vslti.bu",
1038 @"vslti.d",
1039 @"vslti.du",
1040 @"vslti.h",
1041 @"vslti.hu",
1042 @"vslti.w",
1043 @"vslti.wu",
1044 @"vsra.b",
1045 @"vsra.d",
1046 @"vsra.h",
1047 @"vsra.w",
1048 @"vsrai.b",
1049 @"vsrai.d",
1050 @"vsrai.h",
1051 @"vsrai.w",
1052 @"vsran.b.h",
1053 @"vsran.h.w",
1054 @"vsran.w.d",
1055 @"vsrani.b.h",
1056 @"vsrani.d.q",
1057 @"vsrani.h.w",
1058 @"vsrani.w.d",
1059 @"vsrar.b",
1060 @"vsrar.d",
1061 @"vsrar.h",
1062 @"vsrar.w",
1063 @"vsrari.b",
1064 @"vsrari.d",
1065 @"vsrari.h",
1066 @"vsrari.w",
1067 @"vsrarn.b.h",
1068 @"vsrarn.h.w",
1069 @"vsrarn.w.d",
1070 @"vsrarni.b.h",
1071 @"vsrarni.d.q",
1072 @"vsrarni.h.w",
1073 @"vsrarni.w.d",
1074 @"vsrl.b",
1075 @"vsrl.d",
1076 @"vsrl.h",
1077 @"vsrl.w",
1078 @"vsrli.b",
1079 @"vsrli.d",
1080 @"vsrli.h",
1081 @"vsrli.w",
1082 @"vsrln.b.h",
1083 @"vsrln.h.w",
1084 @"vsrln.w.d",
1085 @"vsrlni.b.h",
1086 @"vsrlni.d.q",
1087 @"vsrlni.h.w",
1088 @"vsrlni.w.d",
1089 @"vsrlr.b",
1090 @"vsrlr.d",
1091 @"vsrlr.h",
1092 @"vsrlr.w",
1093 @"vsrlri.b",
1094 @"vsrlri.d",
1095 @"vsrlri.h",
1096 @"vsrlri.w",
1097 @"vsrlrn.b.h",
1098 @"vsrlrn.h.w",
1099 @"vsrlrn.w.d",
1100 @"vsrlrni.b.h",
1101 @"vsrlrni.d.q",
1102 @"vsrlrni.h.w",
1103 @"vsrlrni.w.d",
1104 @"vssran.b.h",
1105 @"vssran.bu.h",
1106 @"vssran.h.w",
1107 @"vssran.hu.w",
1108 @"vssran.w.d",
1109 @"vssran.wu.d",
1110 @"vssrani.b.h",
1111 @"vssrani.bu.h",
1112 @"vssrani.d.q",
1113 @"vssrani.du.q",
1114 @"vssrani.h.w",
1115 @"vssrani.hu.w",
1116 @"vssrani.w.d",
1117 @"vssrani.wu.d",
1118 @"vssrarn.b.h",
1119 @"vssrarn.bu.h",
1120 @"vssrarn.h.w",
1121 @"vssrarn.hu.w",
1122 @"vssrarn.w.d",
1123 @"vssrarn.wu.d",
1124 @"vssrarni.b.h",
1125 @"vssrarni.bu.h",
1126 @"vssrarni.d.q",
1127 @"vssrarni.du.q",
1128 @"vssrarni.h.w",
1129 @"vssrarni.hu.w",
1130 @"vssrarni.w.d",
1131 @"vssrarni.wu.d",
1132 @"vssrln.b.h",
1133 @"vssrln.bu.h",
1134 @"vssrln.h.w",
1135 @"vssrln.hu.w",
1136 @"vssrln.w.d",
1137 @"vssrln.wu.d",
1138 @"vssrlni.b.h",
1139 @"vssrlni.bu.h",
1140 @"vssrlni.d.q",
1141 @"vssrlni.du.q",
1142 @"vssrlni.h.w",
1143 @"vssrlni.hu.w",
1144 @"vssrlni.w.d",
1145 @"vssrlni.wu.d",
1146 @"vssrlrn.b.h",
1147 @"vssrlrn.bu.h",
1148 @"vssrlrn.h.w",
1149 @"vssrlrn.hu.w",
1150 @"vssrlrn.w.d",
1151 @"vssrlrn.wu.d",
1152 @"vssrlrni.b.h",
1153 @"vssrlrni.bu.h",
1154 @"vssrlrni.d.q",
1155 @"vssrlrni.du.q",
1156 @"vssrlrni.h.w",
1157 @"vssrlrni.hu.w",
1158 @"vssrlrni.w.d",
1159 @"vssrlrni.wu.d",
1160 @"vssub.b",
1161 @"vssub.bu",
1162 @"vssub.d",
1163 @"vssub.du",
1164 @"vssub.h",
1165 @"vssub.hu",
1166 @"vssub.w",
1167 @"vssub.wu",
1168 vst,
1169 @"vstelm.b",
1170 @"vstelm.d",
1171 @"vstelm.h",
1172 @"vstelm.w",
1173 vstx,
1174 @"vsub.b",
1175 @"vsub.d",
1176 @"vsub.h",
1177 @"vsub.q",
1178 @"vsub.w",
1179 @"vsubi.bu",
1180 @"vsubi.du",
1181 @"vsubi.hu",
1182 @"vsubi.wu",
1183 @"vsubwev.d.w",
1184 @"vsubwev.d.wu",
1185 @"vsubwev.h.b",
1186 @"vsubwev.h.bu",
1187 @"vsubwev.q.d",
1188 @"vsubwev.q.du",
1189 @"vsubwev.w.h",
1190 @"vsubwev.w.hu",
1191 @"vsubwod.d.w",
1192 @"vsubwod.d.wu",
1193 @"vsubwod.h.b",
1194 @"vsubwod.h.bu",
1195 @"vsubwod.q.d",
1196 @"vsubwod.q.du",
1197 @"vsubwod.w.h",
1198 @"vsubwod.w.hu",
1199 @"vxor.v",
1200 @"vxori.b",
1201 @"x86adc.b",
1202 @"x86adc.d",
1203 @"x86adc.h",
1204 @"x86adc.w",
1205 @"x86add.b",
1206 @"x86add.d",
1207 @"x86add.du",
1208 @"x86add.h",
1209 @"x86add.w",
1210 @"x86add.wu",
1211 @"x86and.b",
1212 @"x86and.d",
1213 @"x86and.h",
1214 @"x86and.w",
1215 x86clrtm,
1216 @"x86dec.b",
1217 @"x86dec.d",
1218 @"x86dec.h",
1219 @"x86dec.w",
1220 x86dectop,
1221 @"x86inc.b",
1222 @"x86inc.d",
1223 @"x86inc.h",
1224 @"x86inc.w",
1225 x86inctop,
1226 x86mfflag,
1227 x86mftop,
1228 x86mtflag,
1229 x86mttop,
1230 @"x86mul.b",
1231 @"x86mul.bu",
1232 @"x86mul.d",
1233 @"x86mul.du",
1234 @"x86mul.h",
1235 @"x86mul.hu",
1236 @"x86mul.w",
1237 @"x86mul.wu",
1238 @"x86or.b",
1239 @"x86or.d",
1240 @"x86or.h",
1241 @"x86or.w",
1242 @"x86rcl.b",
1243 @"x86rcl.d",
1244 @"x86rcl.h",
1245 @"x86rcl.w",
1246 @"x86rcli.b",
1247 @"x86rcli.d",
1248 @"x86rcli.h",
1249 @"x86rcli.w",
1250 @"x86rcr.b",
1251 @"x86rcr.d",
1252 @"x86rcr.h",
1253 @"x86rcr.w",
1254 @"x86rcri.b",
1255 @"x86rcri.d",
1256 @"x86rcri.h",
1257 @"x86rcri.w",
1258 @"x86rotl.b",
1259 @"x86rotl.d",
1260 @"x86rotl.h",
1261 @"x86rotl.w",
1262 @"x86rotli.b",
1263 @"x86rotli.d",
1264 @"x86rotli.h",
1265 @"x86rotli.w",
1266 @"x86rotr.b",
1267 @"x86rotr.d",
1268 @"x86rotr.h",
1269 @"x86rotr.w",
1270 @"x86rotri.b",
1271 @"x86rotri.d",
1272 @"x86rotri.h",
1273 @"x86rotri.w",
1274 @"x86sbc.b",
1275 @"x86sbc.d",
1276 @"x86sbc.h",
1277 @"x86sbc.w",
1278 x86setj,
1279 x86setloope,
1280 x86setloopne,
1281 x86settag,
1282 x86settm,
1283 @"x86sll.b",
1284 @"x86sll.d",
1285 @"x86sll.h",
1286 @"x86sll.w",
1287 @"x86slli.b",
1288 @"x86slli.d",
1289 @"x86slli.h",
1290 @"x86slli.w",
1291 @"x86sra.b",
1292 @"x86sra.d",
1293 @"x86sra.h",
1294 @"x86sra.w",
1295 @"x86srai.b",
1296 @"x86srai.d",
1297 @"x86srai.h",
1298 @"x86srai.w",
1299 @"x86srl.b",
1300 @"x86srl.d",
1301 @"x86srl.h",
1302 @"x86srl.w",
1303 @"x86srli.b",
1304 @"x86srli.d",
1305 @"x86srli.h",
1306 @"x86srli.w",
1307 @"x86sub.b",
1308 @"x86sub.d",
1309 @"x86sub.du",
1310 @"x86sub.h",
1311 @"x86sub.w",
1312 @"x86sub.wu",
1313 @"x86xor.b",
1314 @"x86xor.d",
1315 @"x86xor.h",
1316 @"x86xor.w",
1317 xor,
1318 xori,
1319 @"xvabsd.b",
1320 @"xvabsd.bu",
1321 @"xvabsd.d",
1322 @"xvabsd.du",
1323 @"xvabsd.h",
1324 @"xvabsd.hu",
1325 @"xvabsd.w",
1326 @"xvabsd.wu",
1327 @"xvadd.b",
1328 @"xvadd.d",
1329 @"xvadd.h",
1330 @"xvadd.q",
1331 @"xvadd.w",
1332 @"xvadda.b",
1333 @"xvadda.d",
1334 @"xvadda.h",
1335 @"xvadda.w",
1336 @"xvaddi.bu",
1337 @"xvaddi.du",
1338 @"xvaddi.hu",
1339 @"xvaddi.wu",
1340 @"xvaddwev.d.w",
1341 @"xvaddwev.d.wu",
1342 @"xvaddwev.d.wu.w",
1343 @"xvaddwev.h.b",
1344 @"xvaddwev.h.bu",
1345 @"xvaddwev.h.bu.b",
1346 @"xvaddwev.q.d",
1347 @"xvaddwev.q.du",
1348 @"xvaddwev.q.du.d",
1349 @"xvaddwev.w.h",
1350 @"xvaddwev.w.hu",
1351 @"xvaddwev.w.hu.h",
1352 @"xvaddwod.d.w",
1353 @"xvaddwod.d.wu",
1354 @"xvaddwod.d.wu.w",
1355 @"xvaddwod.h.b",
1356 @"xvaddwod.h.bu",
1357 @"xvaddwod.h.bu.b",
1358 @"xvaddwod.q.d",
1359 @"xvaddwod.q.du",
1360 @"xvaddwod.q.du.d",
1361 @"xvaddwod.w.h",
1362 @"xvaddwod.w.hu",
1363 @"xvaddwod.w.hu.h",
1364 @"xvand.v",
1365 @"xvandi.b",
1366 @"xvandn.v",
1367 @"xvavg.b",
1368 @"xvavg.bu",
1369 @"xvavg.d",
1370 @"xvavg.du",
1371 @"xvavg.h",
1372 @"xvavg.hu",
1373 @"xvavg.w",
1374 @"xvavg.wu",
1375 @"xvavgr.b",
1376 @"xvavgr.bu",
1377 @"xvavgr.d",
1378 @"xvavgr.du",
1379 @"xvavgr.h",
1380 @"xvavgr.hu",
1381 @"xvavgr.w",
1382 @"xvavgr.wu",
1383 @"xvbitclr.b",
1384 @"xvbitclr.d",
1385 @"xvbitclr.h",
1386 @"xvbitclr.w",
1387 @"xvbitclri.b",
1388 @"xvbitclri.d",
1389 @"xvbitclri.h",
1390 @"xvbitclri.w",
1391 @"xvbitrev.b",
1392 @"xvbitrev.d",
1393 @"xvbitrev.h",
1394 @"xvbitrev.w",
1395 @"xvbitrevi.b",
1396 @"xvbitrevi.d",
1397 @"xvbitrevi.h",
1398 @"xvbitrevi.w",
1399 @"xvbitsel.v",
1400 @"xvbitseli.b",
1401 @"xvbitset.b",
1402 @"xvbitset.d",
1403 @"xvbitset.h",
1404 @"xvbitset.w",
1405 @"xvbitseti.b",
1406 @"xvbitseti.d",
1407 @"xvbitseti.h",
1408 @"xvbitseti.w",
1409 @"xvbsll.v",
1410 @"xvbsrl.v",
1411 @"xvclo.b",
1412 @"xvclo.d",
1413 @"xvclo.h",
1414 @"xvclo.w",
1415 @"xvclz.b",
1416 @"xvclz.d",
1417 @"xvclz.h",
1418 @"xvclz.w",
1419 @"xvdiv.b",
1420 @"xvdiv.bu",
1421 @"xvdiv.d",
1422 @"xvdiv.du",
1423 @"xvdiv.h",
1424 @"xvdiv.hu",
1425 @"xvdiv.w",
1426 @"xvdiv.wu",
1427 @"xvexth.d.w",
1428 @"xvexth.du.wu",
1429 @"xvexth.h.b",
1430 @"xvexth.hu.bu",
1431 @"xvexth.q.d",
1432 @"xvexth.qu.du",
1433 @"xvexth.w.h",
1434 @"xvexth.wu.hu",
1435 @"xvextl.q.d",
1436 @"xvextl.qu.du",
1437 @"xvextrins.b",
1438 @"xvextrins.d",
1439 @"xvextrins.h",
1440 @"xvextrins.w",
1441 @"xvfadd.d",
1442 @"xvfadd.s",
1443 @"xvfclass.d",
1444 @"xvfclass.s",
1445 @"xvfcmp.caf.d",
1446 @"xvfcmp.caf.s",
1447 @"xvfcmp.ceq.d",
1448 @"xvfcmp.ceq.s",
1449 @"xvfcmp.cle.d",
1450 @"xvfcmp.cle.s",
1451 @"xvfcmp.clt.d",
1452 @"xvfcmp.clt.s",
1453 @"xvfcmp.cne.d",
1454 @"xvfcmp.cne.s",
1455 @"xvfcmp.cor.d",
1456 @"xvfcmp.cor.s",
1457 @"xvfcmp.cueq.d",
1458 @"xvfcmp.cueq.s",
1459 @"xvfcmp.cule.d",
1460 @"xvfcmp.cule.s",
1461 @"xvfcmp.cult.d",
1462 @"xvfcmp.cult.s",
1463 @"xvfcmp.cun.d",
1464 @"xvfcmp.cun.s",
1465 @"xvfcmp.cune.d",
1466 @"xvfcmp.cune.s",
1467 @"xvfcmp.saf.d",
1468 @"xvfcmp.saf.s",
1469 @"xvfcmp.seq.d",
1470 @"xvfcmp.seq.s",
1471 @"xvfcmp.sle.d",
1472 @"xvfcmp.sle.s",
1473 @"xvfcmp.slt.d",
1474 @"xvfcmp.slt.s",
1475 @"xvfcmp.sne.d",
1476 @"xvfcmp.sne.s",
1477 @"xvfcmp.sor.d",
1478 @"xvfcmp.sor.s",
1479 @"xvfcmp.sueq.d",
1480 @"xvfcmp.sueq.s",
1481 @"xvfcmp.sule.d",
1482 @"xvfcmp.sule.s",
1483 @"xvfcmp.sult.d",
1484 @"xvfcmp.sult.s",
1485 @"xvfcmp.sun.d",
1486 @"xvfcmp.sun.s",
1487 @"xvfcmp.sune.d",
1488 @"xvfcmp.sune.s",
1489 @"xvfcvt.h.s",
1490 @"xvfcvt.s.d",
1491 @"xvfcvth.d.s",
1492 @"xvfcvth.s.h",
1493 @"xvfcvtl.d.s",
1494 @"xvfcvtl.s.h",
1495 @"xvfdiv.d",
1496 @"xvfdiv.s",
1497 @"xvffint.d.l",
1498 @"xvffint.d.lu",
1499 @"xvffint.s.l",
1500 @"xvffint.s.w",
1501 @"xvffint.s.wu",
1502 @"xvffinth.d.w",
1503 @"xvffintl.d.w",
1504 @"xvflogb.d",
1505 @"xvflogb.s",
1506 @"xvfmadd.d",
1507 @"xvfmadd.s",
1508 @"xvfmax.d",
1509 @"xvfmax.s",
1510 @"xvfmaxa.d",
1511 @"xvfmaxa.s",
1512 @"xvfmin.d",
1513 @"xvfmin.s",
1514 @"xvfmina.d",
1515 @"xvfmina.s",
1516 @"xvfmsub.d",
1517 @"xvfmsub.s",
1518 @"xvfmul.d",
1519 @"xvfmul.s",
1520 @"xvfnmadd.d",
1521 @"xvfnmadd.s",
1522 @"xvfnmsub.d",
1523 @"xvfnmsub.s",
1524 @"xvfrecip.d",
1525 @"xvfrecip.s",
1526 @"xvfrecipe.d",
1527 @"xvfrecipe.s",
1528 @"xvfrint.d",
1529 @"xvfrint.s",
1530 @"xvfrintrm.d",
1531 @"xvfrintrm.s",
1532 @"xvfrintrne.d",
1533 @"xvfrintrne.s",
1534 @"xvfrintrp.d",
1535 @"xvfrintrp.s",
1536 @"xvfrintrz.d",
1537 @"xvfrintrz.s",
1538 @"xvfrsqrt.d",
1539 @"xvfrsqrt.s",
1540 @"xvfrsqrte.d",
1541 @"xvfrsqrte.s",
1542 @"xvfrstp.b",
1543 @"xvfrstp.h",
1544 @"xvfrstpi.b",
1545 @"xvfrstpi.h",
1546 @"xvfsqrt.d",
1547 @"xvfsqrt.s",
1548 @"xvfsub.d",
1549 @"xvfsub.s",
1550 @"xvftint.l.d",
1551 @"xvftint.lu.d",
1552 @"xvftint.w.d",
1553 @"xvftint.w.s",
1554 @"xvftint.wu.s",
1555 @"xvftinth.l.s",
1556 @"xvftintl.l.s",
1557 @"xvftintrm.l.d",
1558 @"xvftintrm.w.d",
1559 @"xvftintrm.w.s",
1560 @"xvftintrmh.l.s",
1561 @"xvftintrml.l.s",
1562 @"xvftintrne.l.d",
1563 @"xvftintrne.w.d",
1564 @"xvftintrne.w.s",
1565 @"xvftintrneh.l.s",
1566 @"xvftintrnel.l.s",
1567 @"xvftintrp.l.d",
1568 @"xvftintrp.w.d",
1569 @"xvftintrp.w.s",
1570 @"xvftintrph.l.s",
1571 @"xvftintrpl.l.s",
1572 @"xvftintrz.l.d",
1573 @"xvftintrz.lu.d",
1574 @"xvftintrz.w.d",
1575 @"xvftintrz.w.s",
1576 @"xvftintrz.wu.s",
1577 @"xvftintrzh.l.s",
1578 @"xvftintrzl.l.s",
1579 @"xvhaddw.d.w",
1580 @"xvhaddw.du.wu",
1581 @"xvhaddw.h.b",
1582 @"xvhaddw.hu.bu",
1583 @"xvhaddw.q.d",
1584 @"xvhaddw.qu.du",
1585 @"xvhaddw.w.h",
1586 @"xvhaddw.wu.hu",
1587 @"xvhsubw.d.w",
1588 @"xvhsubw.du.wu",
1589 @"xvhsubw.h.b",
1590 @"xvhsubw.hu.bu",
1591 @"xvhsubw.q.d",
1592 @"xvhsubw.qu.du",
1593 @"xvhsubw.w.h",
1594 @"xvhsubw.wu.hu",
1595 @"xvilvh.b",
1596 @"xvilvh.d",
1597 @"xvilvh.h",
1598 @"xvilvh.w",
1599 @"xvilvl.b",
1600 @"xvilvl.d",
1601 @"xvilvl.h",
1602 @"xvilvl.w",
1603 @"xvinsgr2vr.d",
1604 @"xvinsgr2vr.w",
1605 @"xvinsve0.d",
1606 @"xvinsve0.w",
1607 xvld,
1608 xvldi,
1609 @"xvldrepl.b",
1610 @"xvldrepl.d",
1611 @"xvldrepl.h",
1612 @"xvldrepl.w",
1613 xvldx,
1614 @"xvmadd.b",
1615 @"xvmadd.d",
1616 @"xvmadd.h",
1617 @"xvmadd.w",
1618 @"xvmaddwev.d.w",
1619 @"xvmaddwev.d.wu",
1620 @"xvmaddwev.d.wu.w",
1621 @"xvmaddwev.h.b",
1622 @"xvmaddwev.h.bu",
1623 @"xvmaddwev.h.bu.b",
1624 @"xvmaddwev.q.d",
1625 @"xvmaddwev.q.du",
1626 @"xvmaddwev.q.du.d",
1627 @"xvmaddwev.w.h",
1628 @"xvmaddwev.w.hu",
1629 @"xvmaddwev.w.hu.h",
1630 @"xvmaddwod.d.w",
1631 @"xvmaddwod.d.wu",
1632 @"xvmaddwod.d.wu.w",
1633 @"xvmaddwod.h.b",
1634 @"xvmaddwod.h.bu",
1635 @"xvmaddwod.h.bu.b",
1636 @"xvmaddwod.q.d",
1637 @"xvmaddwod.q.du",
1638 @"xvmaddwod.q.du.d",
1639 @"xvmaddwod.w.h",
1640 @"xvmaddwod.w.hu",
1641 @"xvmaddwod.w.hu.h",
1642 @"xvmax.b",
1643 @"xvmax.bu",
1644 @"xvmax.d",
1645 @"xvmax.du",
1646 @"xvmax.h",
1647 @"xvmax.hu",
1648 @"xvmax.w",
1649 @"xvmax.wu",
1650 @"xvmaxi.b",
1651 @"xvmaxi.bu",
1652 @"xvmaxi.d",
1653 @"xvmaxi.du",
1654 @"xvmaxi.h",
1655 @"xvmaxi.hu",
1656 @"xvmaxi.w",
1657 @"xvmaxi.wu",
1658 @"xvmepatmsk.v",
1659 @"xvmin.b",
1660 @"xvmin.bu",
1661 @"xvmin.d",
1662 @"xvmin.du",
1663 @"xvmin.h",
1664 @"xvmin.hu",
1665 @"xvmin.w",
1666 @"xvmin.wu",
1667 @"xvmini.b",
1668 @"xvmini.bu",
1669 @"xvmini.d",
1670 @"xvmini.du",
1671 @"xvmini.h",
1672 @"xvmini.hu",
1673 @"xvmini.w",
1674 @"xvmini.wu",
1675 @"xvmod.b",
1676 @"xvmod.bu",
1677 @"xvmod.d",
1678 @"xvmod.du",
1679 @"xvmod.h",
1680 @"xvmod.hu",
1681 @"xvmod.w",
1682 @"xvmod.wu",
1683 @"xvmskgez.b",
1684 @"xvmskltz.b",
1685 @"xvmskltz.d",
1686 @"xvmskltz.h",
1687 @"xvmskltz.w",
1688 @"xvmsknz.b",
1689 @"xvmsub.b",
1690 @"xvmsub.d",
1691 @"xvmsub.h",
1692 @"xvmsub.w",
1693 @"xvmuh.b",
1694 @"xvmuh.bu",
1695 @"xvmuh.d",
1696 @"xvmuh.du",
1697 @"xvmuh.h",
1698 @"xvmuh.hu",
1699 @"xvmuh.w",
1700 @"xvmuh.wu",
1701 @"xvmul.b",
1702 @"xvmul.d",
1703 @"xvmul.h",
1704 @"xvmul.w",
1705 @"xvmulwev.d.w",
1706 @"xvmulwev.d.wu",
1707 @"xvmulwev.d.wu.w",
1708 @"xvmulwev.h.b",
1709 @"xvmulwev.h.bu",
1710 @"xvmulwev.h.bu.b",
1711 @"xvmulwev.q.d",
1712 @"xvmulwev.q.du",
1713 @"xvmulwev.q.du.d",
1714 @"xvmulwev.w.h",
1715 @"xvmulwev.w.hu",
1716 @"xvmulwev.w.hu.h",
1717 @"xvmulwod.d.w",
1718 @"xvmulwod.d.wu",
1719 @"xvmulwod.d.wu.w",
1720 @"xvmulwod.h.b",
1721 @"xvmulwod.h.bu",
1722 @"xvmulwod.h.bu.b",
1723 @"xvmulwod.q.d",
1724 @"xvmulwod.q.du",
1725 @"xvmulwod.q.du.d",
1726 @"xvmulwod.w.h",
1727 @"xvmulwod.w.hu",
1728 @"xvmulwod.w.hu.h",
1729 @"xvneg.b",
1730 @"xvneg.d",
1731 @"xvneg.h",
1732 @"xvneg.w",
1733 @"xvnor.v",
1734 @"xvnori.b",
1735 @"xvor.v",
1736 @"xvori.b",
1737 @"xvorn.v",
1738 @"xvpackev.b",
1739 @"xvpackev.d",
1740 @"xvpackev.h",
1741 @"xvpackev.w",
1742 @"xvpackod.b",
1743 @"xvpackod.d",
1744 @"xvpackod.h",
1745 @"xvpackod.w",
1746 @"xvpcnt.b",
1747 @"xvpcnt.d",
1748 @"xvpcnt.h",
1749 @"xvpcnt.w",
1750 @"xvperm.w",
1751 @"xvpermi.d",
1752 @"xvpermi.q",
1753 @"xvpermi.w",
1754 @"xvpickev.b",
1755 @"xvpickev.d",
1756 @"xvpickev.h",
1757 @"xvpickev.w",
1758 @"xvpickod.b",
1759 @"xvpickod.d",
1760 @"xvpickod.h",
1761 @"xvpickod.w",
1762 @"xvpickve.d",
1763 @"xvpickve.w",
1764 @"xvpickve2gr.d",
1765 @"xvpickve2gr.du",
1766 @"xvpickve2gr.w",
1767 @"xvpickve2gr.wu",
1768 @"xvrepl128vei.b",
1769 @"xvrepl128vei.d",
1770 @"xvrepl128vei.h",
1771 @"xvrepl128vei.w",
1772 @"xvreplgr2vr.b",
1773 @"xvreplgr2vr.d",
1774 @"xvreplgr2vr.h",
1775 @"xvreplgr2vr.w",
1776 @"xvreplve.b",
1777 @"xvreplve.d",
1778 @"xvreplve.h",
1779 @"xvreplve.w",
1780 @"xvreplve0.b",
1781 @"xvreplve0.d",
1782 @"xvreplve0.h",
1783 @"xvreplve0.q",
1784 @"xvreplve0.w",
1785 @"xvrotr.b",
1786 @"xvrotr.d",
1787 @"xvrotr.h",
1788 @"xvrotr.w",
1789 @"xvrotri.b",
1790 @"xvrotri.d",
1791 @"xvrotri.h",
1792 @"xvrotri.w",
1793 @"xvsadd.b",
1794 @"xvsadd.bu",
1795 @"xvsadd.d",
1796 @"xvsadd.du",
1797 @"xvsadd.h",
1798 @"xvsadd.hu",
1799 @"xvsadd.w",
1800 @"xvsadd.wu",
1801 @"xvsat.b",
1802 @"xvsat.bu",
1803 @"xvsat.d",
1804 @"xvsat.du",
1805 @"xvsat.h",
1806 @"xvsat.hu",
1807 @"xvsat.w",
1808 @"xvsat.wu",
1809 @"xvseq.b",
1810 @"xvseq.d",
1811 @"xvseq.h",
1812 @"xvseq.w",
1813 @"xvseqi.b",
1814 @"xvseqi.d",
1815 @"xvseqi.h",
1816 @"xvseqi.w",
1817 @"xvsetallnez.b",
1818 @"xvsetallnez.d",
1819 @"xvsetallnez.h",
1820 @"xvsetallnez.w",
1821 @"xvsetanyeqz.b",
1822 @"xvsetanyeqz.d",
1823 @"xvsetanyeqz.h",
1824 @"xvsetanyeqz.w",
1825 @"xvseteqz.v",
1826 @"xvsetnez.v",
1827 @"xvshuf.b",
1828 @"xvshuf.d",
1829 @"xvshuf.h",
1830 @"xvshuf.w",
1831 @"xvshuf4i.b",
1832 @"xvshuf4i.d",
1833 @"xvshuf4i.h",
1834 @"xvshuf4i.w",
1835 @"xvsigncov.b",
1836 @"xvsigncov.d",
1837 @"xvsigncov.h",
1838 @"xvsigncov.w",
1839 @"xvsle.b",
1840 @"xvsle.bu",
1841 @"xvsle.d",
1842 @"xvsle.du",
1843 @"xvsle.h",
1844 @"xvsle.hu",
1845 @"xvsle.w",
1846 @"xvsle.wu",
1847 @"xvslei.b",
1848 @"xvslei.bu",
1849 @"xvslei.d",
1850 @"xvslei.du",
1851 @"xvslei.h",
1852 @"xvslei.hu",
1853 @"xvslei.w",
1854 @"xvslei.wu",
1855 @"xvsll.b",
1856 @"xvsll.d",
1857 @"xvsll.h",
1858 @"xvsll.w",
1859 @"xvslli.b",
1860 @"xvslli.d",
1861 @"xvslli.h",
1862 @"xvslli.w",
1863 @"xvsllwil.d.w",
1864 @"xvsllwil.du.wu",
1865 @"xvsllwil.h.b",
1866 @"xvsllwil.hu.bu",
1867 @"xvsllwil.w.h",
1868 @"xvsllwil.wu.hu",
1869 @"xvslt.b",
1870 @"xvslt.bu",
1871 @"xvslt.d",
1872 @"xvslt.du",
1873 @"xvslt.h",
1874 @"xvslt.hu",
1875 @"xvslt.w",
1876 @"xvslt.wu",
1877 @"xvslti.b",
1878 @"xvslti.bu",
1879 @"xvslti.d",
1880 @"xvslti.du",
1881 @"xvslti.h",
1882 @"xvslti.hu",
1883 @"xvslti.w",
1884 @"xvslti.wu",
1885 @"xvsra.b",
1886 @"xvsra.d",
1887 @"xvsra.h",
1888 @"xvsra.w",
1889 @"xvsrai.b",
1890 @"xvsrai.d",
1891 @"xvsrai.h",
1892 @"xvsrai.w",
1893 @"xvsran.b.h",
1894 @"xvsran.h.w",
1895 @"xvsran.w.d",
1896 @"xvsrani.b.h",
1897 @"xvsrani.d.q",
1898 @"xvsrani.h.w",
1899 @"xvsrani.w.d",
1900 @"xvsrar.b",
1901 @"xvsrar.d",
1902 @"xvsrar.h",
1903 @"xvsrar.w",
1904 @"xvsrari.b",
1905 @"xvsrari.d",
1906 @"xvsrari.h",
1907 @"xvsrari.w",
1908 @"xvsrarn.b.h",
1909 @"xvsrarn.h.w",
1910 @"xvsrarn.w.d",
1911 @"xvsrarni.b.h",
1912 @"xvsrarni.d.q",
1913 @"xvsrarni.h.w",
1914 @"xvsrarni.w.d",
1915 @"xvsrl.b",
1916 @"xvsrl.d",
1917 @"xvsrl.h",
1918 @"xvsrl.w",
1919 @"xvsrli.b",
1920 @"xvsrli.d",
1921 @"xvsrli.h",
1922 @"xvsrli.w",
1923 @"xvsrln.b.h",
1924 @"xvsrln.h.w",
1925 @"xvsrln.w.d",
1926 @"xvsrlni.b.h",
1927 @"xvsrlni.d.q",
1928 @"xvsrlni.h.w",
1929 @"xvsrlni.w.d",
1930 @"xvsrlr.b",
1931 @"xvsrlr.d",
1932 @"xvsrlr.h",
1933 @"xvsrlr.w",
1934 @"xvsrlri.b",
1935 @"xvsrlri.d",
1936 @"xvsrlri.h",
1937 @"xvsrlri.w",
1938 @"xvsrlrn.b.h",
1939 @"xvsrlrn.h.w",
1940 @"xvsrlrn.w.d",
1941 @"xvsrlrni.b.h",
1942 @"xvsrlrni.d.q",
1943 @"xvsrlrni.h.w",
1944 @"xvsrlrni.w.d",
1945 @"xvssran.b.h",
1946 @"xvssran.bu.h",
1947 @"xvssran.h.w",
1948 @"xvssran.hu.w",
1949 @"xvssran.w.d",
1950 @"xvssran.wu.d",
1951 @"xvssrani.b.h",
1952 @"xvssrani.bu.h",
1953 @"xvssrani.d.q",
1954 @"xvssrani.du.q",
1955 @"xvssrani.h.w",
1956 @"xvssrani.hu.w",
1957 @"xvssrani.w.d",
1958 @"xvssrani.wu.d",
1959 @"xvssrarn.b.h",
1960 @"xvssrarn.bu.h",
1961 @"xvssrarn.h.w",
1962 @"xvssrarn.hu.w",
1963 @"xvssrarn.w.d",
1964 @"xvssrarn.wu.d",
1965 @"xvssrarni.b.h",
1966 @"xvssrarni.bu.h",
1967 @"xvssrarni.d.q",
1968 @"xvssrarni.du.q",
1969 @"xvssrarni.h.w",
1970 @"xvssrarni.hu.w",
1971 @"xvssrarni.w.d",
1972 @"xvssrarni.wu.d",
1973 @"xvssrln.b.h",
1974 @"xvssrln.bu.h",
1975 @"xvssrln.h.w",
1976 @"xvssrln.hu.w",
1977 @"xvssrln.w.d",
1978 @"xvssrln.wu.d",
1979 @"xvssrlni.b.h",
1980 @"xvssrlni.bu.h",
1981 @"xvssrlni.d.q",
1982 @"xvssrlni.du.q",
1983 @"xvssrlni.h.w",
1984 @"xvssrlni.hu.w",
1985 @"xvssrlni.w.d",
1986 @"xvssrlni.wu.d",
1987 @"xvssrlrn.b.h",
1988 @"xvssrlrn.bu.h",
1989 @"xvssrlrn.h.w",
1990 @"xvssrlrn.hu.w",
1991 @"xvssrlrn.w.d",
1992 @"xvssrlrn.wu.d",
1993 @"xvssrlrni.b.h",
1994 @"xvssrlrni.bu.h",
1995 @"xvssrlrni.d.q",
1996 @"xvssrlrni.du.q",
1997 @"xvssrlrni.h.w",
1998 @"xvssrlrni.hu.w",
1999 @"xvssrlrni.w.d",
2000 @"xvssrlrni.wu.d",
2001 @"xvssub.b",
2002 @"xvssub.bu",
2003 @"xvssub.d",
2004 @"xvssub.du",
2005 @"xvssub.h",
2006 @"xvssub.hu",
2007 @"xvssub.w",
2008 @"xvssub.wu",
2009 xvst,
2010 @"xvstelm.b",
2011 @"xvstelm.d",
2012 @"xvstelm.h",
2013 @"xvstelm.w",
2014 xvstx,
2015 @"xvsub.b",
2016 @"xvsub.d",
2017 @"xvsub.h",
2018 @"xvsub.q",
2019 @"xvsub.w",
2020 @"xvsubi.bu",
2021 @"xvsubi.du",
2022 @"xvsubi.hu",
2023 @"xvsubi.wu",
2024 @"xvsubwev.d.w",
2025 @"xvsubwev.d.wu",
2026 @"xvsubwev.h.b",
2027 @"xvsubwev.h.bu",
2028 @"xvsubwev.q.d",
2029 @"xvsubwev.q.du",
2030 @"xvsubwev.w.h",
2031 @"xvsubwev.w.hu",
2032 @"xvsubwod.d.w",
2033 @"xvsubwod.d.wu",
2034 @"xvsubwod.h.b",
2035 @"xvsubwod.h.bu",
2036 @"xvsubwod.q.d",
2037 @"xvsubwod.q.du",
2038 @"xvsubwod.w.h",
2039 @"xvsubwod.w.hu",
2040 @"xvxor.v",
2041 @"xvxori.b",
2042 @"xxx.unknown.1",
2043};
2044
2045pub const Instruction = packed union {
2046 word: u32,
2047 /// Fields of a `CdFj` instruction.
2048 CdFj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 },
2049 /// Fields of a `CdFjFk` instruction.
2050 CdFjFk: packed struct { rd: u3, funct3: u2, rj: u5, rk: u5, funct15: u17 },
2051 /// Fields of a `CdJ` instruction.
2052 CdJ: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 },
2053 /// Fields of a `CdVj` instruction.
2054 CdVj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 },
2055 /// Fields of a `CdXj` instruction.
2056 CdXj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 },
2057 /// Fields of a `CjSd5k16` instruction.
2058 CjSd5k16: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 },
2059 /// Fields of a `CjSd5k16ps2` instruction.
2060 CjSd5k16ps2: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 },
2061 /// Fields of a `D` instruction.
2062 D: packed struct { rd: u5, funct5: u27 },
2063 /// Fields of a `DCj` instruction.
2064 DCj: packed struct { rd: u5, rj: u3, funct8: u24 },
2065 /// Fields of a `DFj` instruction.
2066 DFj: packed struct { rd: u5, rj: u5, funct10: u22 },
2067 /// Fields of a `DJ` instruction.
2068 DJ: packed struct { rd: u5, rj: u5, funct10: u22 },
2069 /// Fields of a `DJK` instruction.
2070 DJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2071 /// Fields of a `DJKUa2` instruction.
2072 DJKUa2: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 },
2073 /// Fields of a `DJKUa2pp1` instruction.
2074 DJKUa2pp1: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 },
2075 /// Fields of a `DJKUa3` instruction.
2076 DJKUa3: packed struct { rd: u5, rj: u5, rk: u5, ui3: u3, funct18: u14 },
2077 /// Fields of a `DJSk12` instruction.
2078 DJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 },
2079 /// Fields of a `DJSk14` instruction.
2080 DJSk14: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 },
2081 /// Fields of a `DJSk14ps2` instruction.
2082 DJSk14ps2: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 },
2083 /// Fields of a `DJSk16` instruction.
2084 DJSk16: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 },
2085 /// Fields of a `DJSk16ps2` instruction.
2086 DJSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 },
2087 /// Fields of a `DJSk5` instruction.
2088 DJSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 },
2089 /// Fields of a `DJUk12` instruction.
2090 DJUk12: packed struct { rd: u5, rj: u5, ui12: u12, funct22: u10 },
2091 /// Fields of a `DJUk14` instruction.
2092 DJUk14: packed struct { rd: u5, rj: u5, ui14: u14, funct24: u8 },
2093 /// Fields of a `DJUk3` instruction.
2094 DJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2095 /// Fields of a `DJUk4` instruction.
2096 DJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 },
2097 /// Fields of a `DJUk5` instruction.
2098 DJUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 },
2099 /// Fields of a `DJUk5Um5` instruction.
2100 DJUk5Um5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 },
2101 /// Fields of a `DJUk6` instruction.
2102 DJUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 },
2103 /// Fields of a `DJUk6Um6` instruction.
2104 DJUk6Um6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 },
2105 /// Fields of a `DJUk8` instruction.
2106 DJUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 },
2107 /// Fields of a `DJUm5Uk5` instruction.
2108 DJUm5Uk5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 },
2109 /// Fields of a `DJUm6Uk6` instruction.
2110 DJUm6Uk6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 },
2111 /// Fields of a `DKJ` instruction.
2112 DKJ: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2113 /// Fields of a `DSj20` instruction.
2114 DSj20: packed struct { rd: u5, si20: i20, funct25: u7 },
2115 /// Fields of a `DTj` instruction.
2116 DTj: packed struct { rd: u5, rj: u5, funct10: u22 },
2117 /// Fields of a `DUj5` instruction.
2118 DUj5: packed struct { rd: u5, ui5: u5, funct10: u22 },
2119 /// Fields of a `DUj5Uk8` instruction.
2120 DUj5Uk8: packed struct { rd: u5, ui5: u5, ui8: u8, funct18: u14 },
2121 /// Fields of a `DUk14` instruction.
2122 DUk14: packed struct { rd: u5, funct5: u5, ui14: u14, funct24: u8 },
2123 /// Fields of a `DUk4` instruction.
2124 DUk4: packed struct { rd: u5, funct5: u5, ui4: u4, funct14: u18 },
2125 /// Fields of a `DUk8` instruction.
2126 DUk8: packed struct { rd: u5, funct5: u5, ui8: u8, funct18: u14 },
2127 /// Fields of a `DVjUk1` instruction.
2128 DVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 },
2129 /// Fields of a `DVjUk2` instruction.
2130 DVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2131 /// Fields of a `DVjUk3` instruction.
2132 DVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2133 /// Fields of a `DVjUk4` instruction.
2134 DVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 },
2135 /// Fields of a `DXjUk2` instruction.
2136 DXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2137 /// Fields of a `DXjUk3` instruction.
2138 DXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2139 /// Fields of a `FdCj` instruction.
2140 FdCj: packed struct { rd: u5, rj: u3, funct8: u24 },
2141 /// Fields of a `FdFj` instruction.
2142 FdFj: packed struct { rd: u5, rj: u5, funct10: u22 },
2143 /// Fields of a `FdFjFk` instruction.
2144 FdFjFk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2145 /// Fields of a `FdFjFkCa` instruction.
2146 FdFjFkCa: packed struct { rd: u5, rj: u5, rk: u5, ra: u3, funct18: u14 },
2147 /// Fields of a `FdFjFkFa` instruction.
2148 FdFjFkFa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 },
2149 /// Fields of a `FdJ` instruction.
2150 FdJ: packed struct { rd: u5, rj: u5, funct10: u22 },
2151 /// Fields of a `FdJK` instruction.
2152 FdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2153 /// Fields of a `FdJSk12` instruction.
2154 FdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 },
2155 /// Fields of a `J` instruction.
2156 J: packed struct { funct0: u5, rj: u5, funct10: u22 },
2157 /// Fields of a `JDSk16ps2` instruction.
2158 JDSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 },
2159 /// Fields of a `JK` instruction.
2160 JK: packed struct { funct0: u5, rj: u5, rk: u5, funct15: u17 },
2161 /// Fields of a `JKUd4` instruction.
2162 JKUd4: packed struct { ui4: u4, funct4: u1, rj: u5, rk: u5, funct15: u17 },
2163 /// Fields of a `JKUd5` instruction.
2164 JKUd5: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 },
2165 /// Fields of a `JSd5k16` instruction.
2166 JSd5k16: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 },
2167 /// Fields of a `JSd5k16ps2` instruction.
2168 JSd5k16ps2: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 },
2169 /// Fields of a `JUd4Uk5` instruction.
2170 JUd4Uk5: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 },
2171 /// Fields of a `JUd5` instruction.
2172 JUd5: packed struct { ui5: u5, rj: u5, funct10: u22 },
2173 /// Fields of a `JUd5Sk12` instruction.
2174 JUd5Sk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 },
2175 /// Fields of a `JUk3` instruction.
2176 JUk3: packed struct { funct0: u5, rj: u5, ui3: u3, funct13: u19 },
2177 /// Fields of a `JUk4` instruction.
2178 JUk4: packed struct { funct0: u5, rj: u5, ui4: u4, funct14: u18 },
2179 /// Fields of a `JUk5` instruction.
2180 JUk5: packed struct { funct0: u5, rj: u5, ui5: u5, funct15: u17 },
2181 /// Fields of a `JUk5Ud4` instruction.
2182 JUk5Ud4: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 },
2183 /// Fields of a `JUk6` instruction.
2184 JUk6: packed struct { funct0: u5, rj: u5, ui6: u6, funct16: u16 },
2185 /// Fields of a `JUk8` instruction.
2186 JUk8: packed struct { funct0: u5, rj: u5, ui8: u8, funct18: u14 },
2187 /// Fields of a `Sd10k16` instruction.
2188 Sd10k16: packed struct { si10: i10, si16: i16, funct26: u6 },
2189 /// Fields of a `Sd10k16ps2` instruction.
2190 Sd10k16ps2: packed struct { si10: i10, si16: i16, funct26: u6 },
2191 /// Fields of a `Sd5k16` instruction.
2192 Sd5k16: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 },
2193 /// Fields of a `Sd5k16ps2` instruction.
2194 Sd5k16ps2: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 },
2195 /// Fields of a `TdJ` instruction.
2196 TdJ: packed struct { rd: u5, rj: u5, funct10: u22 },
2197 /// Fields of a `Ud15` instruction.
2198 Ud15: packed struct { ui15: u15, funct15: u17 },
2199 /// Fields of a `Ud5JK` instruction.
2200 Ud5JK: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 },
2201 /// Fields of a `Ud5JSk12` instruction.
2202 Ud5JSk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 },
2203 /// Fields of a `Uj3` instruction.
2204 Uj3: packed struct { funct0: u5, ui3: u3, funct8: u24 },
2205 /// Fields of a `VdJ` instruction.
2206 VdJ: packed struct { rd: u5, rj: u5, funct10: u22 },
2207 /// Fields of a `VdJK` instruction.
2208 VdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2209 /// Fields of a `VdJSk10` instruction.
2210 VdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 },
2211 /// Fields of a `VdJSk10ps2` instruction.
2212 VdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 },
2213 /// Fields of a `VdJSk11` instruction.
2214 VdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 },
2215 /// Fields of a `VdJSk11ps1` instruction.
2216 VdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 },
2217 /// Fields of a `VdJSk12` instruction.
2218 VdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 },
2219 /// Fields of a `VdJSk8Un1` instruction.
2220 VdJSk8Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 },
2221 /// Fields of a `VdJSk8Un2` instruction.
2222 VdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 },
2223 /// Fields of a `VdJSk8Un3` instruction.
2224 VdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 },
2225 /// Fields of a `VdJSk8Un4` instruction.
2226 VdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 },
2227 /// Fields of a `VdJSk8ps1Un3` instruction.
2228 VdJSk8ps1Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 },
2229 /// Fields of a `VdJSk8ps2Un2` instruction.
2230 VdJSk8ps2Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 },
2231 /// Fields of a `VdJSk8ps3Un1` instruction.
2232 VdJSk8ps3Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 },
2233 /// Fields of a `VdJSk9` instruction.
2234 VdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 },
2235 /// Fields of a `VdJSk9ps3` instruction.
2236 VdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 },
2237 /// Fields of a `VdJUk1` instruction.
2238 VdJUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 },
2239 /// Fields of a `VdJUk2` instruction.
2240 VdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2241 /// Fields of a `VdJUk3` instruction.
2242 VdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2243 /// Fields of a `VdJUk4` instruction.
2244 VdJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 },
2245 /// Fields of a `VdSj13` instruction.
2246 VdSj13: packed struct { rd: u5, si13: i13, funct18: u14 },
2247 /// Fields of a `VdUj5Uk5` instruction.
2248 VdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 },
2249 /// Fields of a `VdVj` instruction.
2250 VdVj: packed struct { rd: u5, rj: u5, funct10: u22 },
2251 /// Fields of a `VdVjK` instruction.
2252 VdVjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2253 /// Fields of a `VdVjSk5` instruction.
2254 VdVjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 },
2255 /// Fields of a `VdVjUk1` instruction.
2256 VdVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 },
2257 /// Fields of a `VdVjUk2` instruction.
2258 VdVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2259 /// Fields of a `VdVjUk3` instruction.
2260 VdVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2261 /// Fields of a `VdVjUk4` instruction.
2262 VdVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 },
2263 /// Fields of a `VdVjUk5` instruction.
2264 VdVjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 },
2265 /// Fields of a `VdVjUk6` instruction.
2266 VdVjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 },
2267 /// Fields of a `VdVjUk7` instruction.
2268 VdVjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 },
2269 /// Fields of a `VdVjUk8` instruction.
2270 VdVjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 },
2271 /// Fields of a `VdVjVk` instruction.
2272 VdVjVk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2273 /// Fields of a `VdVjVkVa` instruction.
2274 VdVjVkVa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 },
2275 /// Fields of a `XdJ` instruction.
2276 XdJ: packed struct { rd: u5, rj: u5, funct10: u22 },
2277 /// Fields of a `XdJK` instruction.
2278 XdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2279 /// Fields of a `XdJSk10` instruction.
2280 XdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 },
2281 /// Fields of a `XdJSk10ps2` instruction.
2282 XdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 },
2283 /// Fields of a `XdJSk11` instruction.
2284 XdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 },
2285 /// Fields of a `XdJSk11ps1` instruction.
2286 XdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 },
2287 /// Fields of a `XdJSk12` instruction.
2288 XdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 },
2289 /// Fields of a `XdJSk8Un2` instruction.
2290 XdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 },
2291 /// Fields of a `XdJSk8Un3` instruction.
2292 XdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 },
2293 /// Fields of a `XdJSk8Un4` instruction.
2294 XdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 },
2295 /// Fields of a `XdJSk8Un5` instruction.
2296 XdJSk8Un5: packed struct { rd: u5, rj: u5, si8: i8, ui5: u5, funct23: u9 },
2297 /// Fields of a `XdJSk8ps1Un4` instruction.
2298 XdJSk8ps1Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 },
2299 /// Fields of a `XdJSk8ps2Un3` instruction.
2300 XdJSk8ps2Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 },
2301 /// Fields of a `XdJSk8ps3Un2` instruction.
2302 XdJSk8ps3Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 },
2303 /// Fields of a `XdJSk9` instruction.
2304 XdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 },
2305 /// Fields of a `XdJSk9ps3` instruction.
2306 XdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 },
2307 /// Fields of a `XdJUk2` instruction.
2308 XdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2309 /// Fields of a `XdJUk3` instruction.
2310 XdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2311 /// Fields of a `XdSj13` instruction.
2312 XdSj13: packed struct { rd: u5, si13: i13, funct18: u14 },
2313 /// Fields of a `XdUj5Uk5` instruction.
2314 XdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 },
2315 /// Fields of a `XdXj` instruction.
2316 XdXj: packed struct { rd: u5, rj: u5, funct10: u22 },
2317 /// Fields of a `XdXjK` instruction.
2318 XdXjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2319 /// Fields of a `XdXjSk5` instruction.
2320 XdXjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 },
2321 /// Fields of a `XdXjUk1` instruction.
2322 XdXjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 },
2323 /// Fields of a `XdXjUk2` instruction.
2324 XdXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 },
2325 /// Fields of a `XdXjUk3` instruction.
2326 XdXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 },
2327 /// Fields of a `XdXjUk4` instruction.
2328 XdXjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 },
2329 /// Fields of a `XdXjUk5` instruction.
2330 XdXjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 },
2331 /// Fields of a `XdXjUk6` instruction.
2332 XdXjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 },
2333 /// Fields of a `XdXjUk7` instruction.
2334 XdXjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 },
2335 /// Fields of a `XdXjUk8` instruction.
2336 XdXjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 },
2337 /// Fields of a `XdXjXk` instruction.
2338 XdXjXk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 },
2339 /// Fields of a `XdXjXkXa` instruction.
2340 XdXjXkXa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 },
2341
2342 /// Encodes a `CdFj` instruction.
2343 pub inline fn encodeCdFj(word: u32, p0: Register, p1: Register) Instruction {
2344 return .{ .word = word |
2345 (@as(u32, p0.encode()) << 0) |
2346 (@as(u32, p1.encode()) << 5) };
2347 }
2348
2349 /// Encodes a `CdFjFk` instruction.
2350 pub inline fn encodeCdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2351 return .{ .word = word |
2352 (@as(u32, p0.encode()) << 0) |
2353 (@as(u32, p1.encode()) << 5) |
2354 (@as(u32, p2.encode()) << 10) };
2355 }
2356
2357 /// Encodes a `CdJ` instruction.
2358 pub inline fn encodeCdJ(word: u32, p0: Register, p1: Register) Instruction {
2359 return .{ .word = word |
2360 (@as(u32, p0.encode()) << 0) |
2361 (@as(u32, p1.encode()) << 5) };
2362 }
2363
2364 /// Encodes a `CdVj` instruction.
2365 pub inline fn encodeCdVj(word: u32, p0: Register, p1: Register) Instruction {
2366 return .{ .word = word |
2367 (@as(u32, p0.encode()) << 0) |
2368 (@as(u32, p1.encode()) << 5) };
2369 }
2370
2371 /// Encodes a `CdXj` instruction.
2372 pub inline fn encodeCdXj(word: u32, p0: Register, p1: Register) Instruction {
2373 return .{ .word = word |
2374 (@as(u32, p0.encode()) << 0) |
2375 (@as(u32, p1.encode()) << 5) };
2376 }
2377
2378 /// Encodes a `CjSd5k16` instruction.
2379 pub inline fn encodeCjSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction {
2380 return .{ .word = word |
2381 (@as(u32, p0.encode()) << 5) |
2382 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) |
2383 ((@as(u32, @as(u16, @bitCast(p2)))) << 10) };
2384 }
2385
2386 /// Encodes a `CjSd5k16ps2` instruction.
2387 pub inline fn encodeCjSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction {
2388 return .{ .word = word |
2389 (@as(u32, p0.encode()) << 5) |
2390 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) |
2391 ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) };
2392 }
2393
2394 /// Encodes a `D` instruction.
2395 pub inline fn encodeD(word: u32, p0: Register) Instruction {
2396 return .{ .word = word |
2397 (@as(u32, p0.encode()) << 0) };
2398 }
2399
2400 /// Encodes a `DCj` instruction.
2401 pub inline fn encodeDCj(word: u32, p0: Register, p1: Register) Instruction {
2402 return .{ .word = word |
2403 (@as(u32, p0.encode()) << 0) |
2404 (@as(u32, p1.encode()) << 5) };
2405 }
2406
2407 /// Encodes a `DFj` instruction.
2408 pub inline fn encodeDFj(word: u32, p0: Register, p1: Register) Instruction {
2409 return .{ .word = word |
2410 (@as(u32, p0.encode()) << 0) |
2411 (@as(u32, p1.encode()) << 5) };
2412 }
2413
2414 /// Encodes a `DJ` instruction.
2415 pub inline fn encodeDJ(word: u32, p0: Register, p1: Register) Instruction {
2416 return .{ .word = word |
2417 (@as(u32, p0.encode()) << 0) |
2418 (@as(u32, p1.encode()) << 5) };
2419 }
2420
2421 /// Encodes a `DJK` instruction.
2422 pub inline fn encodeDJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2423 return .{ .word = word |
2424 (@as(u32, p0.encode()) << 0) |
2425 (@as(u32, p1.encode()) << 5) |
2426 (@as(u32, p2.encode()) << 10) };
2427 }
2428
2429 /// Encodes a `DJKUa2` instruction.
2430 pub inline fn encodeDJKUa2(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
2431 return .{ .word = word |
2432 (@as(u32, p0.encode()) << 0) |
2433 (@as(u32, p1.encode()) << 5) |
2434 (@as(u32, p2.encode()) << 10) |
2435 ((@as(u32, @as(u2, @bitCast(p3)))) << 15) };
2436 }
2437
2438 /// Encodes a `DJKUa2pp1` instruction.
2439 pub inline fn encodeDJKUa2pp1(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
2440 return .{ .word = word |
2441 (@as(u32, p0.encode()) << 0) |
2442 (@as(u32, p1.encode()) << 5) |
2443 (@as(u32, p2.encode()) << 10) |
2444 ((@as(u32, @as(u2, @bitCast(p3))) - 1) << 15) };
2445 }
2446
2447 /// Encodes a `DJKUa3` instruction.
2448 pub inline fn encodeDJKUa3(word: u32, p0: Register, p1: Register, p2: Register, p3: u3) Instruction {
2449 return .{ .word = word |
2450 (@as(u32, p0.encode()) << 0) |
2451 (@as(u32, p1.encode()) << 5) |
2452 (@as(u32, p2.encode()) << 10) |
2453 ((@as(u32, @as(u3, @bitCast(p3)))) << 15) };
2454 }
2455
2456 /// Encodes a `DJSk12` instruction.
2457 pub inline fn encodeDJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction {
2458 return .{ .word = word |
2459 (@as(u32, p0.encode()) << 0) |
2460 (@as(u32, p1.encode()) << 5) |
2461 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
2462 }
2463
2464 /// Encodes a `DJSk14` instruction.
2465 pub inline fn encodeDJSk14(word: u32, p0: Register, p1: Register, p2: i14) Instruction {
2466 return .{ .word = word |
2467 (@as(u32, p0.encode()) << 0) |
2468 (@as(u32, p1.encode()) << 5) |
2469 ((@as(u32, @as(u14, @bitCast(p2)))) << 10) };
2470 }
2471
2472 /// Encodes a `DJSk14ps2` instruction.
2473 pub inline fn encodeDJSk14ps2(word: u32, p0: Register, p1: Register, p2: i14) Instruction {
2474 return .{ .word = word |
2475 (@as(u32, p0.encode()) << 0) |
2476 (@as(u32, p1.encode()) << 5) |
2477 ((@as(u32, @as(u14, @bitCast(p2))) >> 2) << 10) };
2478 }
2479
2480 /// Encodes a `DJSk16` instruction.
2481 pub inline fn encodeDJSk16(word: u32, p0: Register, p1: Register, p2: i16) Instruction {
2482 return .{ .word = word |
2483 (@as(u32, p0.encode()) << 0) |
2484 (@as(u32, p1.encode()) << 5) |
2485 ((@as(u32, @as(u16, @bitCast(p2)))) << 10) };
2486 }
2487
2488 /// Encodes a `DJSk16ps2` instruction.
2489 pub inline fn encodeDJSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction {
2490 return .{ .word = word |
2491 (@as(u32, p0.encode()) << 0) |
2492 (@as(u32, p1.encode()) << 5) |
2493 ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) };
2494 }
2495
2496 /// Encodes a `DJSk5` instruction.
2497 pub inline fn encodeDJSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction {
2498 return .{ .word = word |
2499 (@as(u32, p0.encode()) << 0) |
2500 (@as(u32, p1.encode()) << 5) |
2501 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
2502 }
2503
2504 /// Encodes a `DJUk12` instruction.
2505 pub inline fn encodeDJUk12(word: u32, p0: Register, p1: Register, p2: u12) Instruction {
2506 return .{ .word = word |
2507 (@as(u32, p0.encode()) << 0) |
2508 (@as(u32, p1.encode()) << 5) |
2509 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
2510 }
2511
2512 /// Encodes a `DJUk14` instruction.
2513 pub inline fn encodeDJUk14(word: u32, p0: Register, p1: Register, p2: u14) Instruction {
2514 return .{ .word = word |
2515 (@as(u32, p0.encode()) << 0) |
2516 (@as(u32, p1.encode()) << 5) |
2517 ((@as(u32, @as(u14, @bitCast(p2)))) << 10) };
2518 }
2519
2520 /// Encodes a `DJUk3` instruction.
2521 pub inline fn encodeDJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
2522 return .{ .word = word |
2523 (@as(u32, p0.encode()) << 0) |
2524 (@as(u32, p1.encode()) << 5) |
2525 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
2526 }
2527
2528 /// Encodes a `DJUk4` instruction.
2529 pub inline fn encodeDJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
2530 return .{ .word = word |
2531 (@as(u32, p0.encode()) << 0) |
2532 (@as(u32, p1.encode()) << 5) |
2533 ((@as(u32, @as(u4, @bitCast(p2)))) << 10) };
2534 }
2535
2536 /// Encodes a `DJUk5` instruction.
2537 pub inline fn encodeDJUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction {
2538 return .{ .word = word |
2539 (@as(u32, p0.encode()) << 0) |
2540 (@as(u32, p1.encode()) << 5) |
2541 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
2542 }
2543
2544 /// Encodes a `DJUk5Um5` instruction.
2545 pub inline fn encodeDJUk5Um5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction {
2546 return .{ .word = word |
2547 (@as(u32, p0.encode()) << 0) |
2548 (@as(u32, p1.encode()) << 5) |
2549 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) |
2550 ((@as(u32, @as(u5, @bitCast(p3)))) << 16) };
2551 }
2552
2553 /// Encodes a `DJUk6` instruction.
2554 pub inline fn encodeDJUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction {
2555 return .{ .word = word |
2556 (@as(u32, p0.encode()) << 0) |
2557 (@as(u32, p1.encode()) << 5) |
2558 ((@as(u32, @as(u6, @bitCast(p2)))) << 10) };
2559 }
2560
2561 /// Encodes a `DJUk6Um6` instruction.
2562 pub inline fn encodeDJUk6Um6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction {
2563 return .{ .word = word |
2564 (@as(u32, p0.encode()) << 0) |
2565 (@as(u32, p1.encode()) << 5) |
2566 ((@as(u32, @as(u6, @bitCast(p2)))) << 10) |
2567 ((@as(u32, @as(u6, @bitCast(p3)))) << 16) };
2568 }
2569
2570 /// Encodes a `DJUk8` instruction.
2571 pub inline fn encodeDJUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction {
2572 return .{ .word = word |
2573 (@as(u32, p0.encode()) << 0) |
2574 (@as(u32, p1.encode()) << 5) |
2575 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) };
2576 }
2577
2578 /// Encodes a `DJUm5Uk5` instruction.
2579 pub inline fn encodeDJUm5Uk5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction {
2580 return .{ .word = word |
2581 (@as(u32, p0.encode()) << 0) |
2582 (@as(u32, p1.encode()) << 5) |
2583 ((@as(u32, @as(u5, @bitCast(p2)))) << 16) |
2584 ((@as(u32, @as(u5, @bitCast(p3)))) << 10) };
2585 }
2586
2587 /// Encodes a `DJUm6Uk6` instruction.
2588 pub inline fn encodeDJUm6Uk6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction {
2589 return .{ .word = word |
2590 (@as(u32, p0.encode()) << 0) |
2591 (@as(u32, p1.encode()) << 5) |
2592 ((@as(u32, @as(u6, @bitCast(p2)))) << 16) |
2593 ((@as(u32, @as(u6, @bitCast(p3)))) << 10) };
2594 }
2595
2596 /// Encodes a `DKJ` instruction.
2597 pub inline fn encodeDKJ(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2598 return .{ .word = word |
2599 (@as(u32, p0.encode()) << 0) |
2600 (@as(u32, p1.encode()) << 10) |
2601 (@as(u32, p2.encode()) << 5) };
2602 }
2603
2604 /// Encodes a `DSj20` instruction.
2605 pub inline fn encodeDSj20(word: u32, p0: Register, p1: i20) Instruction {
2606 return .{ .word = word |
2607 (@as(u32, p0.encode()) << 0) |
2608 ((@as(u32, @as(u20, @bitCast(p1)))) << 5) };
2609 }
2610
2611 /// Encodes a `DTj` instruction.
2612 pub inline fn encodeDTj(word: u32, p0: Register, p1: Register) Instruction {
2613 return .{ .word = word |
2614 (@as(u32, p0.encode()) << 0) |
2615 (@as(u32, p1.encode()) << 5) };
2616 }
2617
2618 /// Encodes a `DUj5` instruction.
2619 pub inline fn encodeDUj5(word: u32, p0: Register, p1: u5) Instruction {
2620 return .{ .word = word |
2621 (@as(u32, p0.encode()) << 0) |
2622 ((@as(u32, @as(u5, @bitCast(p1)))) << 5) };
2623 }
2624
2625 /// Encodes a `DUj5Uk8` instruction.
2626 pub inline fn encodeDUj5Uk8(word: u32, p0: Register, p1: u5, p2: u8) Instruction {
2627 return .{ .word = word |
2628 (@as(u32, p0.encode()) << 0) |
2629 ((@as(u32, @as(u5, @bitCast(p1)))) << 5) |
2630 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) };
2631 }
2632
2633 /// Encodes a `DUk14` instruction.
2634 pub inline fn encodeDUk14(word: u32, p0: Register, p1: u14) Instruction {
2635 return .{ .word = word |
2636 (@as(u32, p0.encode()) << 0) |
2637 ((@as(u32, @as(u14, @bitCast(p1)))) << 10) };
2638 }
2639
2640 /// Encodes a `DUk4` instruction.
2641 pub inline fn encodeDUk4(word: u32, p0: Register, p1: u4) Instruction {
2642 return .{ .word = word |
2643 (@as(u32, p0.encode()) << 0) |
2644 ((@as(u32, @as(u4, @bitCast(p1)))) << 10) };
2645 }
2646
2647 /// Encodes a `DUk8` instruction.
2648 pub inline fn encodeDUk8(word: u32, p0: Register, p1: u8) Instruction {
2649 return .{ .word = word |
2650 (@as(u32, p0.encode()) << 0) |
2651 ((@as(u32, @as(u8, @bitCast(p1)))) << 10) };
2652 }
2653
2654 /// Encodes a `DVjUk1` instruction.
2655 pub inline fn encodeDVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction {
2656 return .{ .word = word |
2657 (@as(u32, p0.encode()) << 0) |
2658 (@as(u32, p1.encode()) << 5) |
2659 ((@as(u32, @as(u1, @bitCast(p2)))) << 10) };
2660 }
2661
2662 /// Encodes a `DVjUk2` instruction.
2663 pub inline fn encodeDVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
2664 return .{ .word = word |
2665 (@as(u32, p0.encode()) << 0) |
2666 (@as(u32, p1.encode()) << 5) |
2667 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
2668 }
2669
2670 /// Encodes a `DVjUk3` instruction.
2671 pub inline fn encodeDVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
2672 return .{ .word = word |
2673 (@as(u32, p0.encode()) << 0) |
2674 (@as(u32, p1.encode()) << 5) |
2675 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
2676 }
2677
2678 /// Encodes a `DVjUk4` instruction.
2679 pub inline fn encodeDVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
2680 return .{ .word = word |
2681 (@as(u32, p0.encode()) << 0) |
2682 (@as(u32, p1.encode()) << 5) |
2683 ((@as(u32, @as(u4, @bitCast(p2)))) << 10) };
2684 }
2685
2686 /// Encodes a `DXjUk2` instruction.
2687 pub inline fn encodeDXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
2688 return .{ .word = word |
2689 (@as(u32, p0.encode()) << 0) |
2690 (@as(u32, p1.encode()) << 5) |
2691 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
2692 }
2693
2694 /// Encodes a `DXjUk3` instruction.
2695 pub inline fn encodeDXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
2696 return .{ .word = word |
2697 (@as(u32, p0.encode()) << 0) |
2698 (@as(u32, p1.encode()) << 5) |
2699 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
2700 }
2701
2702 /// Encodes a `EMPTY` instruction.
2703 pub inline fn encodeEMPTY(word: u32) Instruction {
2704 return .{ .word = word };
2705 }
2706
2707 /// Encodes a `FdCj` instruction.
2708 pub inline fn encodeFdCj(word: u32, p0: Register, p1: Register) Instruction {
2709 return .{ .word = word |
2710 (@as(u32, p0.encode()) << 0) |
2711 (@as(u32, p1.encode()) << 5) };
2712 }
2713
2714 /// Encodes a `FdFj` instruction.
2715 pub inline fn encodeFdFj(word: u32, p0: Register, p1: Register) Instruction {
2716 return .{ .word = word |
2717 (@as(u32, p0.encode()) << 0) |
2718 (@as(u32, p1.encode()) << 5) };
2719 }
2720
2721 /// Encodes a `FdFjFk` instruction.
2722 pub inline fn encodeFdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2723 return .{ .word = word |
2724 (@as(u32, p0.encode()) << 0) |
2725 (@as(u32, p1.encode()) << 5) |
2726 (@as(u32, p2.encode()) << 10) };
2727 }
2728
2729 /// Encodes a `FdFjFkCa` instruction.
2730 pub inline fn encodeFdFjFkCa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
2731 return .{ .word = word |
2732 (@as(u32, p0.encode()) << 0) |
2733 (@as(u32, p1.encode()) << 5) |
2734 (@as(u32, p2.encode()) << 10) |
2735 (@as(u32, p3.encode()) << 15) };
2736 }
2737
2738 /// Encodes a `FdFjFkFa` instruction.
2739 pub inline fn encodeFdFjFkFa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
2740 return .{ .word = word |
2741 (@as(u32, p0.encode()) << 0) |
2742 (@as(u32, p1.encode()) << 5) |
2743 (@as(u32, p2.encode()) << 10) |
2744 (@as(u32, p3.encode()) << 15) };
2745 }
2746
2747 /// Encodes a `FdJ` instruction.
2748 pub inline fn encodeFdJ(word: u32, p0: Register, p1: Register) Instruction {
2749 return .{ .word = word |
2750 (@as(u32, p0.encode()) << 0) |
2751 (@as(u32, p1.encode()) << 5) };
2752 }
2753
2754 /// Encodes a `FdJK` instruction.
2755 pub inline fn encodeFdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2756 return .{ .word = word |
2757 (@as(u32, p0.encode()) << 0) |
2758 (@as(u32, p1.encode()) << 5) |
2759 (@as(u32, p2.encode()) << 10) };
2760 }
2761
2762 /// Encodes a `FdJSk12` instruction.
2763 pub inline fn encodeFdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction {
2764 return .{ .word = word |
2765 (@as(u32, p0.encode()) << 0) |
2766 (@as(u32, p1.encode()) << 5) |
2767 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
2768 }
2769
2770 /// Encodes a `J` instruction.
2771 pub inline fn encodeJ(word: u32, p0: Register) Instruction {
2772 return .{ .word = word |
2773 (@as(u32, p0.encode()) << 5) };
2774 }
2775
2776 /// Encodes a `JDSk16ps2` instruction.
2777 pub inline fn encodeJDSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction {
2778 return .{ .word = word |
2779 (@as(u32, p0.encode()) << 5) |
2780 (@as(u32, p1.encode()) << 0) |
2781 ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) };
2782 }
2783
2784 /// Encodes a `JK` instruction.
2785 pub inline fn encodeJK(word: u32, p0: Register, p1: Register) Instruction {
2786 return .{ .word = word |
2787 (@as(u32, p0.encode()) << 5) |
2788 (@as(u32, p1.encode()) << 10) };
2789 }
2790
2791 /// Encodes a `JKUd4` instruction.
2792 pub inline fn encodeJKUd4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
2793 return .{ .word = word |
2794 (@as(u32, p0.encode()) << 5) |
2795 (@as(u32, p1.encode()) << 10) |
2796 ((@as(u32, @as(u4, @bitCast(p2)))) << 0) };
2797 }
2798
2799 /// Encodes a `JKUd5` instruction.
2800 pub inline fn encodeJKUd5(word: u32, p0: Register, p1: Register, p2: u5) Instruction {
2801 return .{ .word = word |
2802 (@as(u32, p0.encode()) << 5) |
2803 (@as(u32, p1.encode()) << 10) |
2804 ((@as(u32, @as(u5, @bitCast(p2)))) << 0) };
2805 }
2806
2807 /// Encodes a `JSd5k16` instruction.
2808 pub inline fn encodeJSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction {
2809 return .{ .word = word |
2810 (@as(u32, p0.encode()) << 5) |
2811 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) |
2812 ((@as(u32, @as(u16, @bitCast(p2)))) << 10) };
2813 }
2814
2815 /// Encodes a `JSd5k16ps2` instruction.
2816 pub inline fn encodeJSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction {
2817 return .{ .word = word |
2818 (@as(u32, p0.encode()) << 5) |
2819 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) |
2820 ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) };
2821 }
2822
2823 /// Encodes a `JUd4Uk5` instruction.
2824 pub inline fn encodeJUd4Uk5(word: u32, p0: Register, p1: u4, p2: u5) Instruction {
2825 return .{ .word = word |
2826 (@as(u32, p0.encode()) << 5) |
2827 ((@as(u32, @as(u4, @bitCast(p1)))) << 0) |
2828 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
2829 }
2830
2831 /// Encodes a `JUd5` instruction.
2832 pub inline fn encodeJUd5(word: u32, p0: Register, p1: u5) Instruction {
2833 return .{ .word = word |
2834 (@as(u32, p0.encode()) << 5) |
2835 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) };
2836 }
2837
2838 /// Encodes a `JUd5Sk12` instruction.
2839 pub inline fn encodeJUd5Sk12(word: u32, p0: Register, p1: u5, p2: i12) Instruction {
2840 return .{ .word = word |
2841 (@as(u32, p0.encode()) << 5) |
2842 ((@as(u32, @as(u5, @bitCast(p1)))) << 0) |
2843 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
2844 }
2845
2846 /// Encodes a `JUk3` instruction.
2847 pub inline fn encodeJUk3(word: u32, p0: Register, p1: u3) Instruction {
2848 return .{ .word = word |
2849 (@as(u32, p0.encode()) << 5) |
2850 ((@as(u32, @as(u3, @bitCast(p1)))) << 10) };
2851 }
2852
2853 /// Encodes a `JUk4` instruction.
2854 pub inline fn encodeJUk4(word: u32, p0: Register, p1: u4) Instruction {
2855 return .{ .word = word |
2856 (@as(u32, p0.encode()) << 5) |
2857 ((@as(u32, @as(u4, @bitCast(p1)))) << 10) };
2858 }
2859
2860 /// Encodes a `JUk5` instruction.
2861 pub inline fn encodeJUk5(word: u32, p0: Register, p1: u5) Instruction {
2862 return .{ .word = word |
2863 (@as(u32, p0.encode()) << 5) |
2864 ((@as(u32, @as(u5, @bitCast(p1)))) << 10) };
2865 }
2866
2867 /// Encodes a `JUk5Ud4` instruction.
2868 pub inline fn encodeJUk5Ud4(word: u32, p0: Register, p1: u5, p2: u4) Instruction {
2869 return .{ .word = word |
2870 (@as(u32, p0.encode()) << 5) |
2871 ((@as(u32, @as(u5, @bitCast(p1)))) << 10) |
2872 ((@as(u32, @as(u4, @bitCast(p2)))) << 0) };
2873 }
2874
2875 /// Encodes a `JUk6` instruction.
2876 pub inline fn encodeJUk6(word: u32, p0: Register, p1: u6) Instruction {
2877 return .{ .word = word |
2878 (@as(u32, p0.encode()) << 5) |
2879 ((@as(u32, @as(u6, @bitCast(p1)))) << 10) };
2880 }
2881
2882 /// Encodes a `JUk8` instruction.
2883 pub inline fn encodeJUk8(word: u32, p0: Register, p1: u8) Instruction {
2884 return .{ .word = word |
2885 (@as(u32, p0.encode()) << 5) |
2886 ((@as(u32, @as(u8, @bitCast(p1)))) << 10) };
2887 }
2888
2889 /// Encodes a `Sd10k16` instruction.
2890 pub inline fn encodeSd10k16(word: u32, p0: i10, p1: i16) Instruction {
2891 return .{ .word = word |
2892 ((@as(u32, @as(u10, @bitCast(p0)))) << 0) |
2893 ((@as(u32, @as(u16, @bitCast(p1)))) << 10) };
2894 }
2895
2896 /// Encodes a `Sd10k16ps2` instruction.
2897 pub inline fn encodeSd10k16ps2(word: u32, p0: i10, p1: i16) Instruction {
2898 return .{ .word = word |
2899 ((@as(u32, @as(u10, @bitCast(p0)))) << 0) |
2900 ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) };
2901 }
2902
2903 /// Encodes a `Sd5k16` instruction.
2904 pub inline fn encodeSd5k16(word: u32, p0: i5, p1: i16) Instruction {
2905 return .{ .word = word |
2906 ((@as(u32, @as(u5, @bitCast(p0)))) << 0) |
2907 ((@as(u32, @as(u16, @bitCast(p1)))) << 10) };
2908 }
2909
2910 /// Encodes a `Sd5k16ps2` instruction.
2911 pub inline fn encodeSd5k16ps2(word: u32, p0: i5, p1: i16) Instruction {
2912 return .{ .word = word |
2913 ((@as(u32, @as(u5, @bitCast(p0)))) << 0) |
2914 ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) };
2915 }
2916
2917 /// Encodes a `TdJ` instruction.
2918 pub inline fn encodeTdJ(word: u32, p0: Register, p1: Register) Instruction {
2919 return .{ .word = word |
2920 (@as(u32, p0.encode()) << 0) |
2921 (@as(u32, p1.encode()) << 5) };
2922 }
2923
2924 /// Encodes a `Ud15` instruction.
2925 pub inline fn encodeUd15(word: u32, p0: u15) Instruction {
2926 return .{ .word = word |
2927 ((@as(u32, @as(u15, @bitCast(p0)))) << 0) };
2928 }
2929
2930 /// Encodes a `Ud5JK` instruction.
2931 pub inline fn encodeUd5JK(word: u32, p0: u5, p1: Register, p2: Register) Instruction {
2932 return .{ .word = word |
2933 ((@as(u32, @as(u5, @bitCast(p0)))) << 0) |
2934 (@as(u32, p1.encode()) << 5) |
2935 (@as(u32, p2.encode()) << 10) };
2936 }
2937
2938 /// Encodes a `Ud5JSk12` instruction.
2939 pub inline fn encodeUd5JSk12(word: u32, p0: u5, p1: Register, p2: i12) Instruction {
2940 return .{ .word = word |
2941 ((@as(u32, @as(u5, @bitCast(p0)))) << 0) |
2942 (@as(u32, p1.encode()) << 5) |
2943 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
2944 }
2945
2946 /// Encodes a `Uj3` instruction.
2947 pub inline fn encodeUj3(word: u32, p0: u3) Instruction {
2948 return .{ .word = word |
2949 ((@as(u32, @as(u3, @bitCast(p0)))) << 5) };
2950 }
2951
2952 /// Encodes a `VdJ` instruction.
2953 pub inline fn encodeVdJ(word: u32, p0: Register, p1: Register) Instruction {
2954 return .{ .word = word |
2955 (@as(u32, p0.encode()) << 0) |
2956 (@as(u32, p1.encode()) << 5) };
2957 }
2958
2959 /// Encodes a `VdJK` instruction.
2960 pub inline fn encodeVdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
2961 return .{ .word = word |
2962 (@as(u32, p0.encode()) << 0) |
2963 (@as(u32, p1.encode()) << 5) |
2964 (@as(u32, p2.encode()) << 10) };
2965 }
2966
2967 /// Encodes a `VdJSk10` instruction.
2968 pub inline fn encodeVdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction {
2969 return .{ .word = word |
2970 (@as(u32, p0.encode()) << 0) |
2971 (@as(u32, p1.encode()) << 5) |
2972 ((@as(u32, @as(u10, @bitCast(p2)))) << 10) };
2973 }
2974
2975 /// Encodes a `VdJSk10ps2` instruction.
2976 pub inline fn encodeVdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction {
2977 return .{ .word = word |
2978 (@as(u32, p0.encode()) << 0) |
2979 (@as(u32, p1.encode()) << 5) |
2980 ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) };
2981 }
2982
2983 /// Encodes a `VdJSk11` instruction.
2984 pub inline fn encodeVdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction {
2985 return .{ .word = word |
2986 (@as(u32, p0.encode()) << 0) |
2987 (@as(u32, p1.encode()) << 5) |
2988 ((@as(u32, @as(u11, @bitCast(p2)))) << 10) };
2989 }
2990
2991 /// Encodes a `VdJSk11ps1` instruction.
2992 pub inline fn encodeVdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction {
2993 return .{ .word = word |
2994 (@as(u32, p0.encode()) << 0) |
2995 (@as(u32, p1.encode()) << 5) |
2996 ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) };
2997 }
2998
2999 /// Encodes a `VdJSk12` instruction.
3000 pub inline fn encodeVdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction {
3001 return .{ .word = word |
3002 (@as(u32, p0.encode()) << 0) |
3003 (@as(u32, p1.encode()) << 5) |
3004 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
3005 }
3006
3007 /// Encodes a `VdJSk8Un1` instruction.
3008 pub inline fn encodeVdJSk8Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction {
3009 return .{ .word = word |
3010 (@as(u32, p0.encode()) << 0) |
3011 (@as(u32, p1.encode()) << 5) |
3012 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3013 ((@as(u32, @as(u1, @bitCast(p3)))) << 18) };
3014 }
3015
3016 /// Encodes a `VdJSk8Un2` instruction.
3017 pub inline fn encodeVdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
3018 return .{ .word = word |
3019 (@as(u32, p0.encode()) << 0) |
3020 (@as(u32, p1.encode()) << 5) |
3021 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3022 ((@as(u32, @as(u2, @bitCast(p3)))) << 18) };
3023 }
3024
3025 /// Encodes a `VdJSk8Un3` instruction.
3026 pub inline fn encodeVdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
3027 return .{ .word = word |
3028 (@as(u32, p0.encode()) << 0) |
3029 (@as(u32, p1.encode()) << 5) |
3030 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3031 ((@as(u32, @as(u3, @bitCast(p3)))) << 18) };
3032 }
3033
3034 /// Encodes a `VdJSk8Un4` instruction.
3035 pub inline fn encodeVdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction {
3036 return .{ .word = word |
3037 (@as(u32, p0.encode()) << 0) |
3038 (@as(u32, p1.encode()) << 5) |
3039 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3040 ((@as(u32, @as(u4, @bitCast(p3)))) << 18) };
3041 }
3042
3043 /// Encodes a `VdJSk8ps1Un3` instruction.
3044 pub inline fn encodeVdJSk8ps1Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
3045 return .{ .word = word |
3046 (@as(u32, p0.encode()) << 0) |
3047 (@as(u32, p1.encode()) << 5) |
3048 ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) |
3049 ((@as(u32, @as(u3, @bitCast(p3)))) << 18) };
3050 }
3051
3052 /// Encodes a `VdJSk8ps2Un2` instruction.
3053 pub inline fn encodeVdJSk8ps2Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
3054 return .{ .word = word |
3055 (@as(u32, p0.encode()) << 0) |
3056 (@as(u32, p1.encode()) << 5) |
3057 ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) |
3058 ((@as(u32, @as(u2, @bitCast(p3)))) << 18) };
3059 }
3060
3061 /// Encodes a `VdJSk8ps3Un1` instruction.
3062 pub inline fn encodeVdJSk8ps3Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction {
3063 return .{ .word = word |
3064 (@as(u32, p0.encode()) << 0) |
3065 (@as(u32, p1.encode()) << 5) |
3066 ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) |
3067 ((@as(u32, @as(u1, @bitCast(p3)))) << 18) };
3068 }
3069
3070 /// Encodes a `VdJSk9` instruction.
3071 pub inline fn encodeVdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction {
3072 return .{ .word = word |
3073 (@as(u32, p0.encode()) << 0) |
3074 (@as(u32, p1.encode()) << 5) |
3075 ((@as(u32, @as(u9, @bitCast(p2)))) << 10) };
3076 }
3077
3078 /// Encodes a `VdJSk9ps3` instruction.
3079 pub inline fn encodeVdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction {
3080 return .{ .word = word |
3081 (@as(u32, p0.encode()) << 0) |
3082 (@as(u32, p1.encode()) << 5) |
3083 ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) };
3084 }
3085
3086 /// Encodes a `VdJUk1` instruction.
3087 pub inline fn encodeVdJUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction {
3088 return .{ .word = word |
3089 (@as(u32, p0.encode()) << 0) |
3090 (@as(u32, p1.encode()) << 5) |
3091 ((@as(u32, @as(u1, @bitCast(p2)))) << 10) };
3092 }
3093
3094 /// Encodes a `VdJUk2` instruction.
3095 pub inline fn encodeVdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
3096 return .{ .word = word |
3097 (@as(u32, p0.encode()) << 0) |
3098 (@as(u32, p1.encode()) << 5) |
3099 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
3100 }
3101
3102 /// Encodes a `VdJUk3` instruction.
3103 pub inline fn encodeVdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
3104 return .{ .word = word |
3105 (@as(u32, p0.encode()) << 0) |
3106 (@as(u32, p1.encode()) << 5) |
3107 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
3108 }
3109
3110 /// Encodes a `VdJUk4` instruction.
3111 pub inline fn encodeVdJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
3112 return .{ .word = word |
3113 (@as(u32, p0.encode()) << 0) |
3114 (@as(u32, p1.encode()) << 5) |
3115 ((@as(u32, @as(u4, @bitCast(p2)))) << 10) };
3116 }
3117
3118 /// Encodes a `VdSj13` instruction.
3119 pub inline fn encodeVdSj13(word: u32, p0: Register, p1: i13) Instruction {
3120 return .{ .word = word |
3121 (@as(u32, p0.encode()) << 0) |
3122 ((@as(u32, @as(u13, @bitCast(p1)))) << 5) };
3123 }
3124
3125 /// Encodes a `VdUj5Uk5` instruction.
3126 pub inline fn encodeVdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction {
3127 return .{ .word = word |
3128 (@as(u32, p0.encode()) << 0) |
3129 ((@as(u32, @as(u5, @bitCast(p1)))) << 5) |
3130 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3131 }
3132
3133 /// Encodes a `VdVj` instruction.
3134 pub inline fn encodeVdVj(word: u32, p0: Register, p1: Register) Instruction {
3135 return .{ .word = word |
3136 (@as(u32, p0.encode()) << 0) |
3137 (@as(u32, p1.encode()) << 5) };
3138 }
3139
3140 /// Encodes a `VdVjK` instruction.
3141 pub inline fn encodeVdVjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
3142 return .{ .word = word |
3143 (@as(u32, p0.encode()) << 0) |
3144 (@as(u32, p1.encode()) << 5) |
3145 (@as(u32, p2.encode()) << 10) };
3146 }
3147
3148 /// Encodes a `VdVjSk5` instruction.
3149 pub inline fn encodeVdVjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction {
3150 return .{ .word = word |
3151 (@as(u32, p0.encode()) << 0) |
3152 (@as(u32, p1.encode()) << 5) |
3153 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3154 }
3155
3156 /// Encodes a `VdVjUk1` instruction.
3157 pub inline fn encodeVdVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction {
3158 return .{ .word = word |
3159 (@as(u32, p0.encode()) << 0) |
3160 (@as(u32, p1.encode()) << 5) |
3161 ((@as(u32, @as(u1, @bitCast(p2)))) << 10) };
3162 }
3163
3164 /// Encodes a `VdVjUk2` instruction.
3165 pub inline fn encodeVdVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
3166 return .{ .word = word |
3167 (@as(u32, p0.encode()) << 0) |
3168 (@as(u32, p1.encode()) << 5) |
3169 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
3170 }
3171
3172 /// Encodes a `VdVjUk3` instruction.
3173 pub inline fn encodeVdVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
3174 return .{ .word = word |
3175 (@as(u32, p0.encode()) << 0) |
3176 (@as(u32, p1.encode()) << 5) |
3177 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
3178 }
3179
3180 /// Encodes a `VdVjUk4` instruction.
3181 pub inline fn encodeVdVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
3182 return .{ .word = word |
3183 (@as(u32, p0.encode()) << 0) |
3184 (@as(u32, p1.encode()) << 5) |
3185 ((@as(u32, @as(u4, @bitCast(p2)))) << 10) };
3186 }
3187
3188 /// Encodes a `VdVjUk5` instruction.
3189 pub inline fn encodeVdVjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction {
3190 return .{ .word = word |
3191 (@as(u32, p0.encode()) << 0) |
3192 (@as(u32, p1.encode()) << 5) |
3193 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3194 }
3195
3196 /// Encodes a `VdVjUk6` instruction.
3197 pub inline fn encodeVdVjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction {
3198 return .{ .word = word |
3199 (@as(u32, p0.encode()) << 0) |
3200 (@as(u32, p1.encode()) << 5) |
3201 ((@as(u32, @as(u6, @bitCast(p2)))) << 10) };
3202 }
3203
3204 /// Encodes a `VdVjUk7` instruction.
3205 pub inline fn encodeVdVjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction {
3206 return .{ .word = word |
3207 (@as(u32, p0.encode()) << 0) |
3208 (@as(u32, p1.encode()) << 5) |
3209 ((@as(u32, @as(u7, @bitCast(p2)))) << 10) };
3210 }
3211
3212 /// Encodes a `VdVjUk8` instruction.
3213 pub inline fn encodeVdVjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction {
3214 return .{ .word = word |
3215 (@as(u32, p0.encode()) << 0) |
3216 (@as(u32, p1.encode()) << 5) |
3217 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) };
3218 }
3219
3220 /// Encodes a `VdVjVk` instruction.
3221 pub inline fn encodeVdVjVk(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
3222 return .{ .word = word |
3223 (@as(u32, p0.encode()) << 0) |
3224 (@as(u32, p1.encode()) << 5) |
3225 (@as(u32, p2.encode()) << 10) };
3226 }
3227
3228 /// Encodes a `VdVjVkVa` instruction.
3229 pub inline fn encodeVdVjVkVa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
3230 return .{ .word = word |
3231 (@as(u32, p0.encode()) << 0) |
3232 (@as(u32, p1.encode()) << 5) |
3233 (@as(u32, p2.encode()) << 10) |
3234 (@as(u32, p3.encode()) << 15) };
3235 }
3236
3237 /// Encodes a `XdJ` instruction.
3238 pub inline fn encodeXdJ(word: u32, p0: Register, p1: Register) Instruction {
3239 return .{ .word = word |
3240 (@as(u32, p0.encode()) << 0) |
3241 (@as(u32, p1.encode()) << 5) };
3242 }
3243
3244 /// Encodes a `XdJK` instruction.
3245 pub inline fn encodeXdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
3246 return .{ .word = word |
3247 (@as(u32, p0.encode()) << 0) |
3248 (@as(u32, p1.encode()) << 5) |
3249 (@as(u32, p2.encode()) << 10) };
3250 }
3251
3252 /// Encodes a `XdJSk10` instruction.
3253 pub inline fn encodeXdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction {
3254 return .{ .word = word |
3255 (@as(u32, p0.encode()) << 0) |
3256 (@as(u32, p1.encode()) << 5) |
3257 ((@as(u32, @as(u10, @bitCast(p2)))) << 10) };
3258 }
3259
3260 /// Encodes a `XdJSk10ps2` instruction.
3261 pub inline fn encodeXdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction {
3262 return .{ .word = word |
3263 (@as(u32, p0.encode()) << 0) |
3264 (@as(u32, p1.encode()) << 5) |
3265 ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) };
3266 }
3267
3268 /// Encodes a `XdJSk11` instruction.
3269 pub inline fn encodeXdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction {
3270 return .{ .word = word |
3271 (@as(u32, p0.encode()) << 0) |
3272 (@as(u32, p1.encode()) << 5) |
3273 ((@as(u32, @as(u11, @bitCast(p2)))) << 10) };
3274 }
3275
3276 /// Encodes a `XdJSk11ps1` instruction.
3277 pub inline fn encodeXdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction {
3278 return .{ .word = word |
3279 (@as(u32, p0.encode()) << 0) |
3280 (@as(u32, p1.encode()) << 5) |
3281 ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) };
3282 }
3283
3284 /// Encodes a `XdJSk12` instruction.
3285 pub inline fn encodeXdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction {
3286 return .{ .word = word |
3287 (@as(u32, p0.encode()) << 0) |
3288 (@as(u32, p1.encode()) << 5) |
3289 ((@as(u32, @as(u12, @bitCast(p2)))) << 10) };
3290 }
3291
3292 /// Encodes a `XdJSk8Un2` instruction.
3293 pub inline fn encodeXdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
3294 return .{ .word = word |
3295 (@as(u32, p0.encode()) << 0) |
3296 (@as(u32, p1.encode()) << 5) |
3297 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3298 ((@as(u32, @as(u2, @bitCast(p3)))) << 18) };
3299 }
3300
3301 /// Encodes a `XdJSk8Un3` instruction.
3302 pub inline fn encodeXdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
3303 return .{ .word = word |
3304 (@as(u32, p0.encode()) << 0) |
3305 (@as(u32, p1.encode()) << 5) |
3306 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3307 ((@as(u32, @as(u3, @bitCast(p3)))) << 18) };
3308 }
3309
3310 /// Encodes a `XdJSk8Un4` instruction.
3311 pub inline fn encodeXdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction {
3312 return .{ .word = word |
3313 (@as(u32, p0.encode()) << 0) |
3314 (@as(u32, p1.encode()) << 5) |
3315 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3316 ((@as(u32, @as(u4, @bitCast(p3)))) << 18) };
3317 }
3318
3319 /// Encodes a `XdJSk8Un5` instruction.
3320 pub inline fn encodeXdJSk8Un5(word: u32, p0: Register, p1: Register, p2: i8, p3: u5) Instruction {
3321 return .{ .word = word |
3322 (@as(u32, p0.encode()) << 0) |
3323 (@as(u32, p1.encode()) << 5) |
3324 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) |
3325 ((@as(u32, @as(u5, @bitCast(p3)))) << 18) };
3326 }
3327
3328 /// Encodes a `XdJSk8ps1Un4` instruction.
3329 pub inline fn encodeXdJSk8ps1Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction {
3330 return .{ .word = word |
3331 (@as(u32, p0.encode()) << 0) |
3332 (@as(u32, p1.encode()) << 5) |
3333 ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) |
3334 ((@as(u32, @as(u4, @bitCast(p3)))) << 18) };
3335 }
3336
3337 /// Encodes a `XdJSk8ps2Un3` instruction.
3338 pub inline fn encodeXdJSk8ps2Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
3339 return .{ .word = word |
3340 (@as(u32, p0.encode()) << 0) |
3341 (@as(u32, p1.encode()) << 5) |
3342 ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) |
3343 ((@as(u32, @as(u3, @bitCast(p3)))) << 18) };
3344 }
3345
3346 /// Encodes a `XdJSk8ps3Un2` instruction.
3347 pub inline fn encodeXdJSk8ps3Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
3348 return .{ .word = word |
3349 (@as(u32, p0.encode()) << 0) |
3350 (@as(u32, p1.encode()) << 5) |
3351 ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) |
3352 ((@as(u32, @as(u2, @bitCast(p3)))) << 18) };
3353 }
3354
3355 /// Encodes a `XdJSk9` instruction.
3356 pub inline fn encodeXdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction {
3357 return .{ .word = word |
3358 (@as(u32, p0.encode()) << 0) |
3359 (@as(u32, p1.encode()) << 5) |
3360 ((@as(u32, @as(u9, @bitCast(p2)))) << 10) };
3361 }
3362
3363 /// Encodes a `XdJSk9ps3` instruction.
3364 pub inline fn encodeXdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction {
3365 return .{ .word = word |
3366 (@as(u32, p0.encode()) << 0) |
3367 (@as(u32, p1.encode()) << 5) |
3368 ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) };
3369 }
3370
3371 /// Encodes a `XdJUk2` instruction.
3372 pub inline fn encodeXdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
3373 return .{ .word = word |
3374 (@as(u32, p0.encode()) << 0) |
3375 (@as(u32, p1.encode()) << 5) |
3376 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
3377 }
3378
3379 /// Encodes a `XdJUk3` instruction.
3380 pub inline fn encodeXdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
3381 return .{ .word = word |
3382 (@as(u32, p0.encode()) << 0) |
3383 (@as(u32, p1.encode()) << 5) |
3384 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
3385 }
3386
3387 /// Encodes a `XdSj13` instruction.
3388 pub inline fn encodeXdSj13(word: u32, p0: Register, p1: i13) Instruction {
3389 return .{ .word = word |
3390 (@as(u32, p0.encode()) << 0) |
3391 ((@as(u32, @as(u13, @bitCast(p1)))) << 5) };
3392 }
3393
3394 /// Encodes a `XdUj5Uk5` instruction.
3395 pub inline fn encodeXdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction {
3396 return .{ .word = word |
3397 (@as(u32, p0.encode()) << 0) |
3398 ((@as(u32, @as(u5, @bitCast(p1)))) << 5) |
3399 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3400 }
3401
3402 /// Encodes a `XdXj` instruction.
3403 pub inline fn encodeXdXj(word: u32, p0: Register, p1: Register) Instruction {
3404 return .{ .word = word |
3405 (@as(u32, p0.encode()) << 0) |
3406 (@as(u32, p1.encode()) << 5) };
3407 }
3408
3409 /// Encodes a `XdXjK` instruction.
3410 pub inline fn encodeXdXjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
3411 return .{ .word = word |
3412 (@as(u32, p0.encode()) << 0) |
3413 (@as(u32, p1.encode()) << 5) |
3414 (@as(u32, p2.encode()) << 10) };
3415 }
3416
3417 /// Encodes a `XdXjSk5` instruction.
3418 pub inline fn encodeXdXjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction {
3419 return .{ .word = word |
3420 (@as(u32, p0.encode()) << 0) |
3421 (@as(u32, p1.encode()) << 5) |
3422 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3423 }
3424
3425 /// Encodes a `XdXjUk1` instruction.
3426 pub inline fn encodeXdXjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction {
3427 return .{ .word = word |
3428 (@as(u32, p0.encode()) << 0) |
3429 (@as(u32, p1.encode()) << 5) |
3430 ((@as(u32, @as(u1, @bitCast(p2)))) << 10) };
3431 }
3432
3433 /// Encodes a `XdXjUk2` instruction.
3434 pub inline fn encodeXdXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction {
3435 return .{ .word = word |
3436 (@as(u32, p0.encode()) << 0) |
3437 (@as(u32, p1.encode()) << 5) |
3438 ((@as(u32, @as(u2, @bitCast(p2)))) << 10) };
3439 }
3440
3441 /// Encodes a `XdXjUk3` instruction.
3442 pub inline fn encodeXdXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction {
3443 return .{ .word = word |
3444 (@as(u32, p0.encode()) << 0) |
3445 (@as(u32, p1.encode()) << 5) |
3446 ((@as(u32, @as(u3, @bitCast(p2)))) << 10) };
3447 }
3448
3449 /// Encodes a `XdXjUk4` instruction.
3450 pub inline fn encodeXdXjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction {
3451 return .{ .word = word |
3452 (@as(u32, p0.encode()) << 0) |
3453 (@as(u32, p1.encode()) << 5) |
3454 ((@as(u32, @as(u4, @bitCast(p2)))) << 10) };
3455 }
3456
3457 /// Encodes a `XdXjUk5` instruction.
3458 pub inline fn encodeXdXjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction {
3459 return .{ .word = word |
3460 (@as(u32, p0.encode()) << 0) |
3461 (@as(u32, p1.encode()) << 5) |
3462 ((@as(u32, @as(u5, @bitCast(p2)))) << 10) };
3463 }
3464
3465 /// Encodes a `XdXjUk6` instruction.
3466 pub inline fn encodeXdXjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction {
3467 return .{ .word = word |
3468 (@as(u32, p0.encode()) << 0) |
3469 (@as(u32, p1.encode()) << 5) |
3470 ((@as(u32, @as(u6, @bitCast(p2)))) << 10) };
3471 }
3472
3473 /// Encodes a `XdXjUk7` instruction.
3474 pub inline fn encodeXdXjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction {
3475 return .{ .word = word |
3476 (@as(u32, p0.encode()) << 0) |
3477 (@as(u32, p1.encode()) << 5) |
3478 ((@as(u32, @as(u7, @bitCast(p2)))) << 10) };
3479 }
3480
3481 /// Encodes a `XdXjUk8` instruction.
3482 pub inline fn encodeXdXjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction {
3483 return .{ .word = word |
3484 (@as(u32, p0.encode()) << 0) |
3485 (@as(u32, p1.encode()) << 5) |
3486 ((@as(u32, @as(u8, @bitCast(p2)))) << 10) };
3487 }
3488
3489 /// Encodes a `XdXjXk` instruction.
3490 pub inline fn encodeXdXjXk(word: u32, p0: Register, p1: Register, p2: Register) Instruction {
3491 return .{ .word = word |
3492 (@as(u32, p0.encode()) << 0) |
3493 (@as(u32, p1.encode()) << 5) |
3494 (@as(u32, p2.encode()) << 10) };
3495 }
3496
3497 /// Encodes a `XdXjXkXa` instruction.
3498 pub inline fn encodeXdXjXkXa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
3499 return .{ .word = word |
3500 (@as(u32, p0.encode()) << 0) |
3501 (@as(u32, p1.encode()) << 5) |
3502 (@as(u32, p2.encode()) << 10) |
3503 (@as(u32, p3.encode()) << 15) };
3504 }
3505
3506 /// Encodes a `adc.b` instruction (requires 64bit).
3507 pub inline fn @"adc.b"(p0: Register, p1: Register, p2: Register) Instruction {
3508 return encodeDJK(0x00300000, p0, p1, p2);
3509 }
3510
3511 /// Encodes a `adc.d` instruction (requires 64bit).
3512 pub inline fn @"adc.d"(p0: Register, p1: Register, p2: Register) Instruction {
3513 return encodeDJK(0x00318000, p0, p1, p2);
3514 }
3515
3516 /// Encodes a `adc.h` instruction (requires 64bit).
3517 pub inline fn @"adc.h"(p0: Register, p1: Register, p2: Register) Instruction {
3518 return encodeDJK(0x00308000, p0, p1, p2);
3519 }
3520
3521 /// Encodes a `adc.w` instruction (requires 64bit).
3522 pub inline fn @"adc.w"(p0: Register, p1: Register, p2: Register) Instruction {
3523 return encodeDJK(0x00310000, p0, p1, p2);
3524 }
3525
3526 /// Encodes a `add.d` instruction (requires 64bit).
3527 pub inline fn @"add.d"(p0: Register, p1: Register, p2: Register) Instruction {
3528 return encodeDJK(0x00108000, p0, p1, p2);
3529 }
3530
3531 /// Encodes a `add.w` instruction (requires 32bit).
3532 pub inline fn @"add.w"(p0: Register, p1: Register, p2: Register) Instruction {
3533 return encodeDJK(0x00100000, p0, p1, p2);
3534 }
3535
3536 /// Encodes a `addi.d` instruction (requires 64bit).
3537 pub inline fn @"addi.d"(p0: Register, p1: Register, p2: i12) Instruction {
3538 return encodeDJSk12(0x02c00000, p0, p1, p2);
3539 }
3540
3541 /// Encodes a `addi.w` instruction (requires 32bit).
3542 pub inline fn @"addi.w"(p0: Register, p1: Register, p2: i12) Instruction {
3543 return encodeDJSk12(0x02800000, p0, p1, p2);
3544 }
3545
3546 /// Encodes a `addu12i.d` instruction (requires 64bit).
3547 pub inline fn @"addu12i.d"(p0: Register, p1: Register, p2: i5) Instruction {
3548 return encodeDJSk5(0x00298000, p0, p1, p2);
3549 }
3550
3551 /// Encodes a `addu12i.w` instruction (requires 64bit).
3552 pub inline fn @"addu12i.w"(p0: Register, p1: Register, p2: i5) Instruction {
3553 return encodeDJSk5(0x00290000, p0, p1, p2);
3554 }
3555
3556 /// Encodes a `addu16i.d` instruction (requires 64bit).
3557 pub inline fn @"addu16i.d"(p0: Register, p1: Register, p2: i16) Instruction {
3558 return encodeDJSk16(0x10000000, p0, p1, p2);
3559 }
3560
3561 /// Encodes a `amadd.b` instruction (requires 64bit).
3562 pub inline fn @"amadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
3563 return encodeDKJ(0x385d0000, p0, p1, p2);
3564 }
3565
3566 /// Encodes a `amadd.d` instruction (requires 64bit).
3567 pub inline fn @"amadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
3568 return encodeDKJ(0x38618000, p0, p1, p2);
3569 }
3570
3571 /// Encodes a `amadd.h` instruction (requires 64bit).
3572 pub inline fn @"amadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
3573 return encodeDKJ(0x385d8000, p0, p1, p2);
3574 }
3575
3576 /// Encodes a `amadd.w` instruction (requires 64bit).
3577 pub inline fn @"amadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
3578 return encodeDKJ(0x38610000, p0, p1, p2);
3579 }
3580
3581 /// Encodes a `amadd_db.b` instruction (requires 64bit).
3582 pub inline fn @"amadd_db.b"(p0: Register, p1: Register, p2: Register) Instruction {
3583 return encodeDKJ(0x385f0000, p0, p1, p2);
3584 }
3585
3586 /// Encodes a `amadd_db.d` instruction (requires 64bit).
3587 pub inline fn @"amadd_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3588 return encodeDKJ(0x386a8000, p0, p1, p2);
3589 }
3590
3591 /// Encodes a `amadd_db.h` instruction (requires 64bit).
3592 pub inline fn @"amadd_db.h"(p0: Register, p1: Register, p2: Register) Instruction {
3593 return encodeDKJ(0x385f8000, p0, p1, p2);
3594 }
3595
3596 /// Encodes a `amadd_db.w` instruction (requires 64bit).
3597 pub inline fn @"amadd_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3598 return encodeDKJ(0x386a0000, p0, p1, p2);
3599 }
3600
3601 /// Encodes a `amand.d` instruction (requires 64bit).
3602 pub inline fn @"amand.d"(p0: Register, p1: Register, p2: Register) Instruction {
3603 return encodeDKJ(0x38628000, p0, p1, p2);
3604 }
3605
3606 /// Encodes a `amand.w` instruction (requires 64bit).
3607 pub inline fn @"amand.w"(p0: Register, p1: Register, p2: Register) Instruction {
3608 return encodeDKJ(0x38620000, p0, p1, p2);
3609 }
3610
3611 /// Encodes a `amand_db.d` instruction (requires 64bit).
3612 pub inline fn @"amand_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3613 return encodeDKJ(0x386b8000, p0, p1, p2);
3614 }
3615
3616 /// Encodes a `amand_db.w` instruction (requires 64bit).
3617 pub inline fn @"amand_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3618 return encodeDKJ(0x386b0000, p0, p1, p2);
3619 }
3620
3621 /// Encodes a `amcas.b` instruction (requires 64bit).
3622 pub inline fn @"amcas.b"(p0: Register, p1: Register, p2: Register) Instruction {
3623 return encodeDKJ(0x38580000, p0, p1, p2);
3624 }
3625
3626 /// Encodes a `amcas.d` instruction (requires 64bit).
3627 pub inline fn @"amcas.d"(p0: Register, p1: Register, p2: Register) Instruction {
3628 return encodeDKJ(0x38598000, p0, p1, p2);
3629 }
3630
3631 /// Encodes a `amcas.h` instruction (requires 64bit).
3632 pub inline fn @"amcas.h"(p0: Register, p1: Register, p2: Register) Instruction {
3633 return encodeDKJ(0x38588000, p0, p1, p2);
3634 }
3635
3636 /// Encodes a `amcas.w` instruction (requires 64bit).
3637 pub inline fn @"amcas.w"(p0: Register, p1: Register, p2: Register) Instruction {
3638 return encodeDKJ(0x38590000, p0, p1, p2);
3639 }
3640
3641 /// Encodes a `amcas_db.b` instruction (requires 64bit).
3642 pub inline fn @"amcas_db.b"(p0: Register, p1: Register, p2: Register) Instruction {
3643 return encodeDKJ(0x385a0000, p0, p1, p2);
3644 }
3645
3646 /// Encodes a `amcas_db.d` instruction (requires 64bit).
3647 pub inline fn @"amcas_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3648 return encodeDKJ(0x385b8000, p0, p1, p2);
3649 }
3650
3651 /// Encodes a `amcas_db.h` instruction (requires 64bit).
3652 pub inline fn @"amcas_db.h"(p0: Register, p1: Register, p2: Register) Instruction {
3653 return encodeDKJ(0x385a8000, p0, p1, p2);
3654 }
3655
3656 /// Encodes a `amcas_db.w` instruction (requires 64bit).
3657 pub inline fn @"amcas_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3658 return encodeDKJ(0x385b0000, p0, p1, p2);
3659 }
3660
3661 /// Encodes a `ammax.d` instruction (requires 64bit).
3662 pub inline fn @"ammax.d"(p0: Register, p1: Register, p2: Register) Instruction {
3663 return encodeDKJ(0x38658000, p0, p1, p2);
3664 }
3665
3666 /// Encodes a `ammax.du` instruction (requires 64bit).
3667 pub inline fn @"ammax.du"(p0: Register, p1: Register, p2: Register) Instruction {
3668 return encodeDKJ(0x38678000, p0, p1, p2);
3669 }
3670
3671 /// Encodes a `ammax.w` instruction (requires 64bit).
3672 pub inline fn @"ammax.w"(p0: Register, p1: Register, p2: Register) Instruction {
3673 return encodeDKJ(0x38650000, p0, p1, p2);
3674 }
3675
3676 /// Encodes a `ammax.wu` instruction (requires 64bit).
3677 pub inline fn @"ammax.wu"(p0: Register, p1: Register, p2: Register) Instruction {
3678 return encodeDKJ(0x38670000, p0, p1, p2);
3679 }
3680
3681 /// Encodes a `ammax_db.d` instruction (requires 64bit).
3682 pub inline fn @"ammax_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3683 return encodeDKJ(0x386e8000, p0, p1, p2);
3684 }
3685
3686 /// Encodes a `ammax_db.du` instruction (requires 64bit).
3687 pub inline fn @"ammax_db.du"(p0: Register, p1: Register, p2: Register) Instruction {
3688 return encodeDKJ(0x38708000, p0, p1, p2);
3689 }
3690
3691 /// Encodes a `ammax_db.w` instruction (requires 64bit).
3692 pub inline fn @"ammax_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3693 return encodeDKJ(0x386e0000, p0, p1, p2);
3694 }
3695
3696 /// Encodes a `ammax_db.wu` instruction (requires 64bit).
3697 pub inline fn @"ammax_db.wu"(p0: Register, p1: Register, p2: Register) Instruction {
3698 return encodeDKJ(0x38700000, p0, p1, p2);
3699 }
3700
3701 /// Encodes a `ammin.d` instruction (requires 64bit).
3702 pub inline fn @"ammin.d"(p0: Register, p1: Register, p2: Register) Instruction {
3703 return encodeDKJ(0x38668000, p0, p1, p2);
3704 }
3705
3706 /// Encodes a `ammin.du` instruction (requires 64bit).
3707 pub inline fn @"ammin.du"(p0: Register, p1: Register, p2: Register) Instruction {
3708 return encodeDKJ(0x38688000, p0, p1, p2);
3709 }
3710
3711 /// Encodes a `ammin.w` instruction (requires 64bit).
3712 pub inline fn @"ammin.w"(p0: Register, p1: Register, p2: Register) Instruction {
3713 return encodeDKJ(0x38660000, p0, p1, p2);
3714 }
3715
3716 /// Encodes a `ammin.wu` instruction (requires 64bit).
3717 pub inline fn @"ammin.wu"(p0: Register, p1: Register, p2: Register) Instruction {
3718 return encodeDKJ(0x38680000, p0, p1, p2);
3719 }
3720
3721 /// Encodes a `ammin_db.d` instruction (requires 64bit).
3722 pub inline fn @"ammin_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3723 return encodeDKJ(0x386f8000, p0, p1, p2);
3724 }
3725
3726 /// Encodes a `ammin_db.du` instruction (requires 64bit).
3727 pub inline fn @"ammin_db.du"(p0: Register, p1: Register, p2: Register) Instruction {
3728 return encodeDKJ(0x38718000, p0, p1, p2);
3729 }
3730
3731 /// Encodes a `ammin_db.w` instruction (requires 64bit).
3732 pub inline fn @"ammin_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3733 return encodeDKJ(0x386f0000, p0, p1, p2);
3734 }
3735
3736 /// Encodes a `ammin_db.wu` instruction (requires 64bit).
3737 pub inline fn @"ammin_db.wu"(p0: Register, p1: Register, p2: Register) Instruction {
3738 return encodeDKJ(0x38710000, p0, p1, p2);
3739 }
3740
3741 /// Encodes a `amor.d` instruction (requires 64bit).
3742 pub inline fn @"amor.d"(p0: Register, p1: Register, p2: Register) Instruction {
3743 return encodeDKJ(0x38638000, p0, p1, p2);
3744 }
3745
3746 /// Encodes a `amor.w` instruction (requires 64bit).
3747 pub inline fn @"amor.w"(p0: Register, p1: Register, p2: Register) Instruction {
3748 return encodeDKJ(0x38630000, p0, p1, p2);
3749 }
3750
3751 /// Encodes a `amor_db.d` instruction (requires 64bit).
3752 pub inline fn @"amor_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3753 return encodeDKJ(0x386c8000, p0, p1, p2);
3754 }
3755
3756 /// Encodes a `amor_db.w` instruction (requires 64bit).
3757 pub inline fn @"amor_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3758 return encodeDKJ(0x386c0000, p0, p1, p2);
3759 }
3760
3761 /// Encodes a `amswap.b` instruction (requires 64bit).
3762 pub inline fn @"amswap.b"(p0: Register, p1: Register, p2: Register) Instruction {
3763 return encodeDKJ(0x385c0000, p0, p1, p2);
3764 }
3765
3766 /// Encodes a `amswap.d` instruction (requires 64bit).
3767 pub inline fn @"amswap.d"(p0: Register, p1: Register, p2: Register) Instruction {
3768 return encodeDKJ(0x38608000, p0, p1, p2);
3769 }
3770
3771 /// Encodes a `amswap.h` instruction (requires 64bit).
3772 pub inline fn @"amswap.h"(p0: Register, p1: Register, p2: Register) Instruction {
3773 return encodeDKJ(0x385c8000, p0, p1, p2);
3774 }
3775
3776 /// Encodes a `amswap.w` instruction (requires 64bit).
3777 pub inline fn @"amswap.w"(p0: Register, p1: Register, p2: Register) Instruction {
3778 return encodeDKJ(0x38600000, p0, p1, p2);
3779 }
3780
3781 /// Encodes a `amswap_db.b` instruction (requires 64bit).
3782 pub inline fn @"amswap_db.b"(p0: Register, p1: Register, p2: Register) Instruction {
3783 return encodeDKJ(0x385e0000, p0, p1, p2);
3784 }
3785
3786 /// Encodes a `amswap_db.d` instruction (requires 64bit).
3787 pub inline fn @"amswap_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3788 return encodeDKJ(0x38698000, p0, p1, p2);
3789 }
3790
3791 /// Encodes a `amswap_db.h` instruction (requires 64bit).
3792 pub inline fn @"amswap_db.h"(p0: Register, p1: Register, p2: Register) Instruction {
3793 return encodeDKJ(0x385e8000, p0, p1, p2);
3794 }
3795
3796 /// Encodes a `amswap_db.w` instruction (requires 64bit).
3797 pub inline fn @"amswap_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3798 return encodeDKJ(0x38690000, p0, p1, p2);
3799 }
3800
3801 /// Encodes a `amxor.d` instruction (requires 64bit).
3802 pub inline fn @"amxor.d"(p0: Register, p1: Register, p2: Register) Instruction {
3803 return encodeDKJ(0x38648000, p0, p1, p2);
3804 }
3805
3806 /// Encodes a `amxor.w` instruction (requires 64bit).
3807 pub inline fn @"amxor.w"(p0: Register, p1: Register, p2: Register) Instruction {
3808 return encodeDKJ(0x38640000, p0, p1, p2);
3809 }
3810
3811 /// Encodes a `amxor_db.d` instruction (requires 64bit).
3812 pub inline fn @"amxor_db.d"(p0: Register, p1: Register, p2: Register) Instruction {
3813 return encodeDKJ(0x386d8000, p0, p1, p2);
3814 }
3815
3816 /// Encodes a `amxor_db.w` instruction (requires 64bit).
3817 pub inline fn @"amxor_db.w"(p0: Register, p1: Register, p2: Register) Instruction {
3818 return encodeDKJ(0x386d0000, p0, p1, p2);
3819 }
3820
3821 /// Encodes a `and` instruction (requires 32bit).
3822 pub inline fn @"and"(p0: Register, p1: Register, p2: Register) Instruction {
3823 return encodeDJK(0x00148000, p0, p1, p2);
3824 }
3825
3826 /// Encodes a `andi` instruction (requires 32bit).
3827 pub inline fn andi(p0: Register, p1: Register, p2: u12) Instruction {
3828 return encodeDJUk12(0x03400000, p0, p1, p2);
3829 }
3830
3831 /// Encodes a `andn` instruction (requires 32bit).
3832 pub inline fn andn(p0: Register, p1: Register, p2: Register) Instruction {
3833 return encodeDJK(0x00168000, p0, p1, p2);
3834 }
3835
3836 /// Encodes a `armadc.w` instruction (requires 64bit).
3837 pub inline fn @"armadc.w"(p0: Register, p1: Register, p2: u4) Instruction {
3838 return encodeJKUd4(0x00380010, p0, p1, p2);
3839 }
3840
3841 /// Encodes a `armadd.w` instruction (requires 64bit).
3842 pub inline fn @"armadd.w"(p0: Register, p1: Register, p2: u4) Instruction {
3843 return encodeJKUd4(0x00370010, p0, p1, p2);
3844 }
3845
3846 /// Encodes a `armand.w` instruction (requires 64bit).
3847 pub inline fn @"armand.w"(p0: Register, p1: Register, p2: u4) Instruction {
3848 return encodeJKUd4(0x00390010, p0, p1, p2);
3849 }
3850
3851 /// Encodes a `armmfflag` instruction (requires 64bit).
3852 pub inline fn armmfflag(p0: Register, p1: u8) Instruction {
3853 return encodeDUk8(0x005c0040, p0, p1);
3854 }
3855
3856 /// Encodes a `armmov.d` instruction (requires 64bit).
3857 pub inline fn @"armmov.d"(p0: Register, p1: u4) Instruction {
3858 return encodeJUk4(0x003fc01e, p0, p1);
3859 }
3860
3861 /// Encodes a `armmov.w` instruction (requires 64bit).
3862 pub inline fn @"armmov.w"(p0: Register, p1: u4) Instruction {
3863 return encodeJUk4(0x003fc01d, p0, p1);
3864 }
3865
3866 /// Encodes a `armmove` instruction (requires 64bit).
3867 pub inline fn armmove(p0: Register, p1: Register, p2: u4) Instruction {
3868 return encodeDJUk4(0x00364000, p0, p1, p2);
3869 }
3870
3871 /// Encodes a `armmtflag` instruction (requires 64bit).
3872 pub inline fn armmtflag(p0: Register, p1: u8) Instruction {
3873 return encodeDUk8(0x005c0060, p0, p1);
3874 }
3875
3876 /// Encodes a `armnot.w` instruction (requires 64bit).
3877 pub inline fn @"armnot.w"(p0: Register, p1: u4) Instruction {
3878 return encodeJUk4(0x003fc01c, p0, p1);
3879 }
3880
3881 /// Encodes a `armor.w` instruction (requires 64bit).
3882 pub inline fn @"armor.w"(p0: Register, p1: Register, p2: u4) Instruction {
3883 return encodeJKUd4(0x00398010, p0, p1, p2);
3884 }
3885
3886 /// Encodes a `armrotr.w` instruction (requires 64bit).
3887 pub inline fn @"armrotr.w"(p0: Register, p1: Register, p2: u4) Instruction {
3888 return encodeJKUd4(0x003c0010, p0, p1, p2);
3889 }
3890
3891 /// Encodes a `armrotri.w` instruction (requires 64bit).
3892 pub inline fn @"armrotri.w"(p0: Register, p1: u5, p2: u4) Instruction {
3893 return encodeJUk5Ud4(0x003e0010, p0, p1, p2);
3894 }
3895
3896 /// Encodes a `armrrx.w` instruction (requires 64bit).
3897 pub inline fn @"armrrx.w"(p0: Register, p1: u4) Instruction {
3898 return encodeJUk4(0x003fc01f, p0, p1);
3899 }
3900
3901 /// Encodes a `armsbc.w` instruction (requires 64bit).
3902 pub inline fn @"armsbc.w"(p0: Register, p1: Register, p2: u4) Instruction {
3903 return encodeJKUd4(0x00388010, p0, p1, p2);
3904 }
3905
3906 /// Encodes a `armsetj` instruction (requires 64bit).
3907 pub inline fn armsetj(p0: Register, p1: u4) Instruction {
3908 return encodeDUk4(0x0036c000, p0, p1);
3909 }
3910
3911 /// Encodes a `armsll.w` instruction (requires 64bit).
3912 pub inline fn @"armsll.w"(p0: Register, p1: Register, p2: u4) Instruction {
3913 return encodeJKUd4(0x003a8010, p0, p1, p2);
3914 }
3915
3916 /// Encodes a `armslli.w` instruction (requires 64bit).
3917 pub inline fn @"armslli.w"(p0: Register, p1: u5, p2: u4) Instruction {
3918 return encodeJUk5Ud4(0x003c8010, p0, p1, p2);
3919 }
3920
3921 /// Encodes a `armsra.w` instruction (requires 64bit).
3922 pub inline fn @"armsra.w"(p0: Register, p1: Register, p2: u4) Instruction {
3923 return encodeJKUd4(0x003b8010, p0, p1, p2);
3924 }
3925
3926 /// Encodes a `armsrai.w` instruction (requires 64bit).
3927 pub inline fn @"armsrai.w"(p0: Register, p1: u5, p2: u4) Instruction {
3928 return encodeJUk5Ud4(0x003d8010, p0, p1, p2);
3929 }
3930
3931 /// Encodes a `armsrl.w` instruction (requires 64bit).
3932 pub inline fn @"armsrl.w"(p0: Register, p1: Register, p2: u4) Instruction {
3933 return encodeJKUd4(0x003b0010, p0, p1, p2);
3934 }
3935
3936 /// Encodes a `armsrli.w` instruction (requires 64bit).
3937 pub inline fn @"armsrli.w"(p0: Register, p1: u5, p2: u4) Instruction {
3938 return encodeJUk5Ud4(0x003d0010, p0, p1, p2);
3939 }
3940
3941 /// Encodes a `armsub.w` instruction (requires 64bit).
3942 pub inline fn @"armsub.w"(p0: Register, p1: Register, p2: u4) Instruction {
3943 return encodeJKUd4(0x00378010, p0, p1, p2);
3944 }
3945
3946 /// Encodes a `armxor.w` instruction (requires 64bit).
3947 pub inline fn @"armxor.w"(p0: Register, p1: Register, p2: u4) Instruction {
3948 return encodeJKUd4(0x003a0010, p0, p1, p2);
3949 }
3950
3951 /// Encodes a `asrtgt` instruction (requires 64bit).
3952 pub inline fn asrtgt(p0: Register, p1: Register) Instruction {
3953 return encodeJK(0x00018000, p0, p1);
3954 }
3955
3956 /// Encodes a `asrtle` instruction (requires 64bit).
3957 pub inline fn asrtle(p0: Register, p1: Register) Instruction {
3958 return encodeJK(0x00010000, p0, p1);
3959 }
3960
3961 /// Encodes a `b` instruction (requires 32bit).
3962 pub inline fn b(p0: i10, p1: i16) Instruction {
3963 return encodeSd10k16ps2(0x50000000, p0, p1);
3964 }
3965
3966 /// Encodes a `bceqz` instruction (requires f).
3967 pub inline fn bceqz(p0: Register, p1: i5, p2: i16) Instruction {
3968 return encodeCjSd5k16ps2(0x48000000, p0, p1, p2);
3969 }
3970
3971 /// Encodes a `bcnez` instruction (requires f).
3972 pub inline fn bcnez(p0: Register, p1: i5, p2: i16) Instruction {
3973 return encodeCjSd5k16ps2(0x48000100, p0, p1, p2);
3974 }
3975
3976 /// Encodes a `beq` instruction (requires 32bit).
3977 pub inline fn beq(p0: Register, p1: Register, p2: i16) Instruction {
3978 return encodeJDSk16ps2(0x58000000, p0, p1, p2);
3979 }
3980
3981 /// Encodes a `beqz` instruction (requires 32s).
3982 pub inline fn beqz(p0: Register, p1: i5, p2: i16) Instruction {
3983 return encodeJSd5k16ps2(0x40000000, p0, p1, p2);
3984 }
3985
3986 /// Encodes a `bgt` instruction (requires 32bit).
3987 pub inline fn bgt(p0: Register, p1: Register, p2: i16) Instruction {
3988 return encodeDJSk16(0x60000000, p0, p1, p2);
3989 }
3990
3991 /// Encodes a `bgtu` instruction (requires 32bit).
3992 pub inline fn bgtu(p0: Register, p1: Register, p2: i16) Instruction {
3993 return encodeDJSk16(0x68000000, p0, p1, p2);
3994 }
3995
3996 /// Encodes a `bl` instruction (requires 32bit).
3997 pub inline fn bl(p0: i10, p1: i16) Instruction {
3998 return encodeSd10k16ps2(0x54000000, p0, p1);
3999 }
4000
4001 /// Encodes a `ble` instruction (requires 32bit).
4002 pub inline fn ble(p0: Register, p1: Register, p2: i16) Instruction {
4003 return encodeDJSk16(0x64000000, p0, p1, p2);
4004 }
4005
4006 /// Encodes a `bleu` instruction (requires 32bit).
4007 pub inline fn bleu(p0: Register, p1: Register, p2: i16) Instruction {
4008 return encodeDJSk16(0x6c000000, p0, p1, p2);
4009 }
4010
4011 /// Encodes a `bne` instruction (requires 32bit).
4012 pub inline fn bne(p0: Register, p1: Register, p2: i16) Instruction {
4013 return encodeJDSk16ps2(0x5c000000, p0, p1, p2);
4014 }
4015
4016 /// Encodes a `bnez` instruction (requires 32s).
4017 pub inline fn bnez(p0: Register, p1: i5, p2: i16) Instruction {
4018 return encodeJSd5k16ps2(0x44000000, p0, p1, p2);
4019 }
4020
4021 /// Encodes a `break` instruction (requires 32bit).
4022 pub inline fn @"break"(p0: u15) Instruction {
4023 return encodeUd15(0x002a0000, p0);
4024 }
4025
4026 /// Encodes a `bstrins.d` instruction (requires 64bit).
4027 pub inline fn @"bstrins.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction {
4028 return encodeDJUm6Uk6(0x00800000, p0, p1, p2, p3);
4029 }
4030
4031 /// Encodes a `bstrins.w` instruction (requires 32s).
4032 pub inline fn @"bstrins.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction {
4033 return encodeDJUm5Uk5(0x00600000, p0, p1, p2, p3);
4034 }
4035
4036 /// Encodes a `bstrpick.d` instruction (requires 64bit).
4037 pub inline fn @"bstrpick.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction {
4038 return encodeDJUm6Uk6(0x00c00000, p0, p1, p2, p3);
4039 }
4040
4041 /// Encodes a `bstrpick.w` instruction (requires 32s).
4042 pub inline fn @"bstrpick.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction {
4043 return encodeDJUm5Uk5(0x00608000, p0, p1, p2, p3);
4044 }
4045
4046 /// Encodes a `cacop` instruction (requires 32bit).
4047 pub inline fn cacop(p0: u5, p1: Register, p2: i12) Instruction {
4048 return encodeUd5JSk12(0x06000000, p0, p1, p2);
4049 }
4050
4051 /// Encodes a `catpick.d` instruction (requires 64bit).
4052 pub inline fn @"catpick.d"(p0: Register, p1: Register, p2: Register, p3: u3) Instruction {
4053 return encodeDJKUa3(0x000c0000, p0, p1, p2, p3);
4054 }
4055
4056 /// Encodes a `catpick.w` instruction (requires 32s).
4057 pub inline fn @"catpick.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
4058 return encodeDJKUa2(0x00080000, p0, p1, p2, p3);
4059 }
4060
4061 /// Encodes a `clo.d` instruction (requires 64bit).
4062 pub inline fn @"clo.d"(p0: Register, p1: Register) Instruction {
4063 return encodeDJ(0x00002000, p0, p1);
4064 }
4065
4066 /// Encodes a `clo.w` instruction (requires 32s).
4067 pub inline fn @"clo.w"(p0: Register, p1: Register) Instruction {
4068 return encodeDJ(0x00001000, p0, p1);
4069 }
4070
4071 /// Encodes a `clz.d` instruction (requires 64bit).
4072 pub inline fn @"clz.d"(p0: Register, p1: Register) Instruction {
4073 return encodeDJ(0x00002400, p0, p1);
4074 }
4075
4076 /// Encodes a `clz.w` instruction (requires 32s).
4077 pub inline fn @"clz.w"(p0: Register, p1: Register) Instruction {
4078 return encodeDJ(0x00001400, p0, p1);
4079 }
4080
4081 /// Encodes a `cpucfg` instruction (requires 32s).
4082 pub inline fn cpucfg(p0: Register, p1: Register) Instruction {
4083 return encodeDJ(0x00006c00, p0, p1);
4084 }
4085
4086 /// Encodes a `crc.w.b.w` instruction (requires 64bit).
4087 pub inline fn @"crc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction {
4088 return encodeDJK(0x00240000, p0, p1, p2);
4089 }
4090
4091 /// Encodes a `crc.w.d.w` instruction (requires 64bit).
4092 pub inline fn @"crc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
4093 return encodeDJK(0x00258000, p0, p1, p2);
4094 }
4095
4096 /// Encodes a `crc.w.h.w` instruction (requires 64bit).
4097 pub inline fn @"crc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
4098 return encodeDJK(0x00248000, p0, p1, p2);
4099 }
4100
4101 /// Encodes a `crc.w.w.w` instruction (requires 64bit).
4102 pub inline fn @"crc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction {
4103 return encodeDJK(0x00250000, p0, p1, p2);
4104 }
4105
4106 /// Encodes a `crcc.w.b.w` instruction (requires 64bit).
4107 pub inline fn @"crcc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction {
4108 return encodeDJK(0x00260000, p0, p1, p2);
4109 }
4110
4111 /// Encodes a `crcc.w.d.w` instruction (requires 64bit).
4112 pub inline fn @"crcc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
4113 return encodeDJK(0x00278000, p0, p1, p2);
4114 }
4115
4116 /// Encodes a `crcc.w.h.w` instruction (requires 64bit).
4117 pub inline fn @"crcc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
4118 return encodeDJK(0x00268000, p0, p1, p2);
4119 }
4120
4121 /// Encodes a `crcc.w.w.w` instruction (requires 64bit).
4122 pub inline fn @"crcc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction {
4123 return encodeDJK(0x00270000, p0, p1, p2);
4124 }
4125
4126 /// Encodes a `csrrd` instruction (requires 32bit).
4127 pub inline fn csrrd(p0: Register, p1: u14) Instruction {
4128 return encodeDUk14(0x04000000, p0, p1);
4129 }
4130
4131 /// Encodes a `csrwr` instruction (requires 32bit).
4132 pub inline fn csrwr(p0: Register, p1: u14) Instruction {
4133 return encodeDUk14(0x04000032, p0, p1);
4134 }
4135
4136 /// Encodes a `csrxchg` instruction (requires 32bit).
4137 pub inline fn csrxchg(p0: Register, p1: Register, p2: u14) Instruction {
4138 return encodeDJUk14(0x04000000, p0, p1, p2);
4139 }
4140
4141 /// Encodes a `cto.d` instruction (requires 64bit).
4142 pub inline fn @"cto.d"(p0: Register, p1: Register) Instruction {
4143 return encodeDJ(0x00002800, p0, p1);
4144 }
4145
4146 /// Encodes a `cto.w` instruction (requires 32s).
4147 pub inline fn @"cto.w"(p0: Register, p1: Register) Instruction {
4148 return encodeDJ(0x00001800, p0, p1);
4149 }
4150
4151 /// Encodes a `ctz.d` instruction (requires 64bit).
4152 pub inline fn @"ctz.d"(p0: Register, p1: Register) Instruction {
4153 return encodeDJ(0x00002c00, p0, p1);
4154 }
4155
4156 /// Encodes a `ctz.w` instruction (requires 32s).
4157 pub inline fn @"ctz.w"(p0: Register, p1: Register) Instruction {
4158 return encodeDJ(0x00001c00, p0, p1);
4159 }
4160
4161 /// Encodes a `cu32i.d` instruction (requires 64bit).
4162 pub inline fn @"cu32i.d"(p0: Register, p1: i20) Instruction {
4163 return encodeDSj20(0x16000000, p0, p1);
4164 }
4165
4166 /// Encodes a `cu52i.d` instruction (requires 64bit).
4167 pub inline fn @"cu52i.d"(p0: Register, p1: Register, p2: i12) Instruction {
4168 return encodeDJSk12(0x03000000, p0, p1, p2);
4169 }
4170
4171 /// Encodes a `dbar` instruction (requires 32bit).
4172 pub inline fn dbar(p0: u15) Instruction {
4173 return encodeUd15(0x38720000, p0);
4174 }
4175
4176 /// Encodes a `dbgcall` instruction (requires 64bit).
4177 pub inline fn dbgcall(p0: u15) Instruction {
4178 return encodeUd15(0x002a8000, p0);
4179 }
4180
4181 /// Encodes a `div.d` instruction (requires 64bit).
4182 pub inline fn @"div.d"(p0: Register, p1: Register, p2: Register) Instruction {
4183 return encodeDJK(0x00220000, p0, p1, p2);
4184 }
4185
4186 /// Encodes a `div.du` instruction (requires 64bit).
4187 pub inline fn @"div.du"(p0: Register, p1: Register, p2: Register) Instruction {
4188 return encodeDJK(0x00230000, p0, p1, p2);
4189 }
4190
4191 /// Encodes a `div.w` instruction (requires 32bit).
4192 pub inline fn @"div.w"(p0: Register, p1: Register, p2: Register) Instruction {
4193 return encodeDJK(0x00200000, p0, p1, p2);
4194 }
4195
4196 /// Encodes a `div.wu` instruction (requires 32bit).
4197 pub inline fn @"div.wu"(p0: Register, p1: Register, p2: Register) Instruction {
4198 return encodeDJK(0x00210000, p0, p1, p2);
4199 }
4200
4201 /// Encodes a `eret` instruction (requires 32bit).
4202 pub inline fn eret() Instruction {
4203 return encodeEMPTY(0x06483800);
4204 }
4205
4206 /// Encodes a `fabs.d` instruction (requires f).
4207 pub inline fn @"fabs.d"(p0: Register, p1: Register) Instruction {
4208 return encodeFdFj(0x01140800, p0, p1);
4209 }
4210
4211 /// Encodes a `fabs.s` instruction (requires f).
4212 pub inline fn @"fabs.s"(p0: Register, p1: Register) Instruction {
4213 return encodeFdFj(0x01140400, p0, p1);
4214 }
4215
4216 /// Encodes a `fadd.d` instruction (requires f).
4217 pub inline fn @"fadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
4218 return encodeFdFjFk(0x01010000, p0, p1, p2);
4219 }
4220
4221 /// Encodes a `fadd.s` instruction (requires f).
4222 pub inline fn @"fadd.s"(p0: Register, p1: Register, p2: Register) Instruction {
4223 return encodeFdFjFk(0x01008000, p0, p1, p2);
4224 }
4225
4226 /// Encodes a `fclass.d` instruction (requires f).
4227 pub inline fn @"fclass.d"(p0: Register, p1: Register) Instruction {
4228 return encodeFdFj(0x01143800, p0, p1);
4229 }
4230
4231 /// Encodes a `fclass.s` instruction (requires f).
4232 pub inline fn @"fclass.s"(p0: Register, p1: Register) Instruction {
4233 return encodeFdFj(0x01143400, p0, p1);
4234 }
4235
4236 /// Encodes a `fcmp.caf.d` instruction (requires f).
4237 pub inline fn @"fcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction {
4238 return encodeCdFjFk(0x0c200000, p0, p1, p2);
4239 }
4240
4241 /// Encodes a `fcmp.caf.s` instruction (requires f).
4242 pub inline fn @"fcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction {
4243 return encodeCdFjFk(0x0c100000, p0, p1, p2);
4244 }
4245
4246 /// Encodes a `fcmp.ceq.d` instruction (requires f).
4247 pub inline fn @"fcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction {
4248 return encodeCdFjFk(0x0c220000, p0, p1, p2);
4249 }
4250
4251 /// Encodes a `fcmp.ceq.s` instruction (requires f).
4252 pub inline fn @"fcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction {
4253 return encodeCdFjFk(0x0c120000, p0, p1, p2);
4254 }
4255
4256 /// Encodes a `fcmp.cle.d` instruction (requires f).
4257 pub inline fn @"fcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction {
4258 return encodeCdFjFk(0x0c230000, p0, p1, p2);
4259 }
4260
4261 /// Encodes a `fcmp.cle.s` instruction (requires f).
4262 pub inline fn @"fcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction {
4263 return encodeCdFjFk(0x0c130000, p0, p1, p2);
4264 }
4265
4266 /// Encodes a `fcmp.clt.d` instruction (requires f).
4267 pub inline fn @"fcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction {
4268 return encodeCdFjFk(0x0c210000, p0, p1, p2);
4269 }
4270
4271 /// Encodes a `fcmp.clt.s` instruction (requires f).
4272 pub inline fn @"fcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction {
4273 return encodeCdFjFk(0x0c110000, p0, p1, p2);
4274 }
4275
4276 /// Encodes a `fcmp.cne.d` instruction (requires f).
4277 pub inline fn @"fcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction {
4278 return encodeCdFjFk(0x0c280000, p0, p1, p2);
4279 }
4280
4281 /// Encodes a `fcmp.cne.s` instruction (requires f).
4282 pub inline fn @"fcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction {
4283 return encodeCdFjFk(0x0c180000, p0, p1, p2);
4284 }
4285
4286 /// Encodes a `fcmp.cor.d` instruction (requires f).
4287 pub inline fn @"fcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction {
4288 return encodeCdFjFk(0x0c2a0000, p0, p1, p2);
4289 }
4290
4291 /// Encodes a `fcmp.cor.s` instruction (requires f).
4292 pub inline fn @"fcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction {
4293 return encodeCdFjFk(0x0c1a0000, p0, p1, p2);
4294 }
4295
4296 /// Encodes a `fcmp.cueq.d` instruction (requires f).
4297 pub inline fn @"fcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
4298 return encodeCdFjFk(0x0c260000, p0, p1, p2);
4299 }
4300
4301 /// Encodes a `fcmp.cueq.s` instruction (requires f).
4302 pub inline fn @"fcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
4303 return encodeCdFjFk(0x0c160000, p0, p1, p2);
4304 }
4305
4306 /// Encodes a `fcmp.cule.d` instruction (requires f).
4307 pub inline fn @"fcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction {
4308 return encodeCdFjFk(0x0c270000, p0, p1, p2);
4309 }
4310
4311 /// Encodes a `fcmp.cule.s` instruction (requires f).
4312 pub inline fn @"fcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction {
4313 return encodeCdFjFk(0x0c170000, p0, p1, p2);
4314 }
4315
4316 /// Encodes a `fcmp.cult.d` instruction (requires f).
4317 pub inline fn @"fcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction {
4318 return encodeCdFjFk(0x0c250000, p0, p1, p2);
4319 }
4320
4321 /// Encodes a `fcmp.cult.s` instruction (requires f).
4322 pub inline fn @"fcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction {
4323 return encodeCdFjFk(0x0c150000, p0, p1, p2);
4324 }
4325
4326 /// Encodes a `fcmp.cun.d` instruction (requires f).
4327 pub inline fn @"fcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction {
4328 return encodeCdFjFk(0x0c240000, p0, p1, p2);
4329 }
4330
4331 /// Encodes a `fcmp.cun.s` instruction (requires f).
4332 pub inline fn @"fcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction {
4333 return encodeCdFjFk(0x0c140000, p0, p1, p2);
4334 }
4335
4336 /// Encodes a `fcmp.cune.d` instruction (requires f).
4337 pub inline fn @"fcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction {
4338 return encodeCdFjFk(0x0c2c0000, p0, p1, p2);
4339 }
4340
4341 /// Encodes a `fcmp.cune.s` instruction (requires f).
4342 pub inline fn @"fcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction {
4343 return encodeCdFjFk(0x0c1c0000, p0, p1, p2);
4344 }
4345
4346 /// Encodes a `fcmp.saf.d` instruction (requires f).
4347 pub inline fn @"fcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction {
4348 return encodeCdFjFk(0x0c208000, p0, p1, p2);
4349 }
4350
4351 /// Encodes a `fcmp.saf.s` instruction (requires f).
4352 pub inline fn @"fcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction {
4353 return encodeCdFjFk(0x0c108000, p0, p1, p2);
4354 }
4355
4356 /// Encodes a `fcmp.seq.d` instruction (requires f).
4357 pub inline fn @"fcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction {
4358 return encodeCdFjFk(0x0c228000, p0, p1, p2);
4359 }
4360
4361 /// Encodes a `fcmp.seq.s` instruction (requires f).
4362 pub inline fn @"fcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction {
4363 return encodeCdFjFk(0x0c128000, p0, p1, p2);
4364 }
4365
4366 /// Encodes a `fcmp.sle.d` instruction (requires f).
4367 pub inline fn @"fcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction {
4368 return encodeCdFjFk(0x0c238000, p0, p1, p2);
4369 }
4370
4371 /// Encodes a `fcmp.sle.s` instruction (requires f).
4372 pub inline fn @"fcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction {
4373 return encodeCdFjFk(0x0c138000, p0, p1, p2);
4374 }
4375
4376 /// Encodes a `fcmp.slt.d` instruction (requires f).
4377 pub inline fn @"fcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction {
4378 return encodeCdFjFk(0x0c218000, p0, p1, p2);
4379 }
4380
4381 /// Encodes a `fcmp.slt.s` instruction (requires f).
4382 pub inline fn @"fcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction {
4383 return encodeCdFjFk(0x0c118000, p0, p1, p2);
4384 }
4385
4386 /// Encodes a `fcmp.sne.d` instruction (requires f).
4387 pub inline fn @"fcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction {
4388 return encodeCdFjFk(0x0c288000, p0, p1, p2);
4389 }
4390
4391 /// Encodes a `fcmp.sne.s` instruction (requires f).
4392 pub inline fn @"fcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction {
4393 return encodeCdFjFk(0x0c188000, p0, p1, p2);
4394 }
4395
4396 /// Encodes a `fcmp.sor.d` instruction (requires f).
4397 pub inline fn @"fcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction {
4398 return encodeCdFjFk(0x0c2a8000, p0, p1, p2);
4399 }
4400
4401 /// Encodes a `fcmp.sor.s` instruction (requires f).
4402 pub inline fn @"fcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction {
4403 return encodeCdFjFk(0x0c1a8000, p0, p1, p2);
4404 }
4405
4406 /// Encodes a `fcmp.sueq.d` instruction (requires f).
4407 pub inline fn @"fcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
4408 return encodeCdFjFk(0x0c268000, p0, p1, p2);
4409 }
4410
4411 /// Encodes a `fcmp.sueq.s` instruction (requires f).
4412 pub inline fn @"fcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
4413 return encodeCdFjFk(0x0c168000, p0, p1, p2);
4414 }
4415
4416 /// Encodes a `fcmp.sule.d` instruction (requires f).
4417 pub inline fn @"fcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction {
4418 return encodeCdFjFk(0x0c278000, p0, p1, p2);
4419 }
4420
4421 /// Encodes a `fcmp.sule.s` instruction (requires f).
4422 pub inline fn @"fcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction {
4423 return encodeCdFjFk(0x0c178000, p0, p1, p2);
4424 }
4425
4426 /// Encodes a `fcmp.sult.d` instruction (requires f).
4427 pub inline fn @"fcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction {
4428 return encodeCdFjFk(0x0c258000, p0, p1, p2);
4429 }
4430
4431 /// Encodes a `fcmp.sult.s` instruction (requires f).
4432 pub inline fn @"fcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction {
4433 return encodeCdFjFk(0x0c158000, p0, p1, p2);
4434 }
4435
4436 /// Encodes a `fcmp.sun.d` instruction (requires f).
4437 pub inline fn @"fcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction {
4438 return encodeCdFjFk(0x0c248000, p0, p1, p2);
4439 }
4440
4441 /// Encodes a `fcmp.sun.s` instruction (requires f).
4442 pub inline fn @"fcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction {
4443 return encodeCdFjFk(0x0c148000, p0, p1, p2);
4444 }
4445
4446 /// Encodes a `fcmp.sune.d` instruction (requires f).
4447 pub inline fn @"fcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction {
4448 return encodeCdFjFk(0x0c2c8000, p0, p1, p2);
4449 }
4450
4451 /// Encodes a `fcmp.sune.s` instruction (requires f).
4452 pub inline fn @"fcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction {
4453 return encodeCdFjFk(0x0c1c8000, p0, p1, p2);
4454 }
4455
4456 /// Encodes a `fcopysign.d` instruction (requires f).
4457 pub inline fn @"fcopysign.d"(p0: Register, p1: Register, p2: Register) Instruction {
4458 return encodeFdFjFk(0x01130000, p0, p1, p2);
4459 }
4460
4461 /// Encodes a `fcopysign.s` instruction (requires f).
4462 pub inline fn @"fcopysign.s"(p0: Register, p1: Register, p2: Register) Instruction {
4463 return encodeFdFjFk(0x01128000, p0, p1, p2);
4464 }
4465
4466 /// Encodes a `fcsrrd` instruction (requires 64bit).
4467 pub inline fn fcsrrd(p0: Register, p1: u5) Instruction {
4468 return encodeDUj5(0x0114c800, p0, p1);
4469 }
4470
4471 /// Encodes a `fcsrwr` instruction (requires 64bit).
4472 pub inline fn fcsrwr(p0: Register, p1: u5) Instruction {
4473 return encodeJUd5(0x0114c000, p0, p1);
4474 }
4475
4476 /// Encodes a `fcvt.d.ld` instruction (requires f).
4477 pub inline fn @"fcvt.d.ld"(p0: Register, p1: Register, p2: Register) Instruction {
4478 return encodeFdFjFk(0x01150000, p0, p1, p2);
4479 }
4480
4481 /// Encodes a `fcvt.d.s` instruction (requires f).
4482 pub inline fn @"fcvt.d.s"(p0: Register, p1: Register) Instruction {
4483 return encodeFdFj(0x01192400, p0, p1);
4484 }
4485
4486 /// Encodes a `fcvt.ld.d` instruction (requires f).
4487 pub inline fn @"fcvt.ld.d"(p0: Register, p1: Register) Instruction {
4488 return encodeFdFj(0x0114e000, p0, p1);
4489 }
4490
4491 /// Encodes a `fcvt.s.d` instruction (requires f).
4492 pub inline fn @"fcvt.s.d"(p0: Register, p1: Register) Instruction {
4493 return encodeFdFj(0x01191800, p0, p1);
4494 }
4495
4496 /// Encodes a `fcvt.ud.d` instruction (requires f).
4497 pub inline fn @"fcvt.ud.d"(p0: Register, p1: Register) Instruction {
4498 return encodeFdFj(0x0114e400, p0, p1);
4499 }
4500
4501 /// Encodes a `fdiv.d` instruction (requires f).
4502 pub inline fn @"fdiv.d"(p0: Register, p1: Register, p2: Register) Instruction {
4503 return encodeFdFjFk(0x01070000, p0, p1, p2);
4504 }
4505
4506 /// Encodes a `fdiv.s` instruction (requires f).
4507 pub inline fn @"fdiv.s"(p0: Register, p1: Register, p2: Register) Instruction {
4508 return encodeFdFjFk(0x01068000, p0, p1, p2);
4509 }
4510
4511 /// Encodes a `ffint.d.l` instruction (requires f).
4512 pub inline fn @"ffint.d.l"(p0: Register, p1: Register) Instruction {
4513 return encodeFdFj(0x011d2800, p0, p1);
4514 }
4515
4516 /// Encodes a `ffint.d.w` instruction (requires f).
4517 pub inline fn @"ffint.d.w"(p0: Register, p1: Register) Instruction {
4518 return encodeFdFj(0x011d2000, p0, p1);
4519 }
4520
4521 /// Encodes a `ffint.s.l` instruction (requires f).
4522 pub inline fn @"ffint.s.l"(p0: Register, p1: Register) Instruction {
4523 return encodeFdFj(0x011d1800, p0, p1);
4524 }
4525
4526 /// Encodes a `ffint.s.w` instruction (requires f).
4527 pub inline fn @"ffint.s.w"(p0: Register, p1: Register) Instruction {
4528 return encodeFdFj(0x011d1000, p0, p1);
4529 }
4530
4531 /// Encodes a `fld.d` instruction (requires f).
4532 pub inline fn @"fld.d"(p0: Register, p1: Register, p2: i12) Instruction {
4533 return encodeFdJSk12(0x2b800000, p0, p1, p2);
4534 }
4535
4536 /// Encodes a `fld.s` instruction (requires f).
4537 pub inline fn @"fld.s"(p0: Register, p1: Register, p2: i12) Instruction {
4538 return encodeFdJSk12(0x2b000000, p0, p1, p2);
4539 }
4540
4541 /// Encodes a `fldgt.d` instruction (requires f).
4542 pub inline fn @"fldgt.d"(p0: Register, p1: Register, p2: Register) Instruction {
4543 return encodeFdJK(0x38748000, p0, p1, p2);
4544 }
4545
4546 /// Encodes a `fldgt.s` instruction (requires f).
4547 pub inline fn @"fldgt.s"(p0: Register, p1: Register, p2: Register) Instruction {
4548 return encodeFdJK(0x38740000, p0, p1, p2);
4549 }
4550
4551 /// Encodes a `fldle.d` instruction (requires f).
4552 pub inline fn @"fldle.d"(p0: Register, p1: Register, p2: Register) Instruction {
4553 return encodeFdJK(0x38758000, p0, p1, p2);
4554 }
4555
4556 /// Encodes a `fldle.s` instruction (requires f).
4557 pub inline fn @"fldle.s"(p0: Register, p1: Register, p2: Register) Instruction {
4558 return encodeFdJK(0x38750000, p0, p1, p2);
4559 }
4560
4561 /// Encodes a `fldx.d` instruction (requires f).
4562 pub inline fn @"fldx.d"(p0: Register, p1: Register, p2: Register) Instruction {
4563 return encodeFdJK(0x38340000, p0, p1, p2);
4564 }
4565
4566 /// Encodes a `fldx.s` instruction (requires f).
4567 pub inline fn @"fldx.s"(p0: Register, p1: Register, p2: Register) Instruction {
4568 return encodeFdJK(0x38300000, p0, p1, p2);
4569 }
4570
4571 /// Encodes a `flogb.d` instruction (requires f).
4572 pub inline fn @"flogb.d"(p0: Register, p1: Register) Instruction {
4573 return encodeFdFj(0x01142800, p0, p1);
4574 }
4575
4576 /// Encodes a `flogb.s` instruction (requires f).
4577 pub inline fn @"flogb.s"(p0: Register, p1: Register) Instruction {
4578 return encodeFdFj(0x01142400, p0, p1);
4579 }
4580
4581 /// Encodes a `fmadd.d` instruction (requires f).
4582 pub inline fn @"fmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4583 return encodeFdFjFkFa(0x08200000, p0, p1, p2, p3);
4584 }
4585
4586 /// Encodes a `fmadd.s` instruction (requires f).
4587 pub inline fn @"fmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4588 return encodeFdFjFkFa(0x08100000, p0, p1, p2, p3);
4589 }
4590
4591 /// Encodes a `fmax.d` instruction (requires f).
4592 pub inline fn @"fmax.d"(p0: Register, p1: Register, p2: Register) Instruction {
4593 return encodeFdFjFk(0x01090000, p0, p1, p2);
4594 }
4595
4596 /// Encodes a `fmax.s` instruction (requires f).
4597 pub inline fn @"fmax.s"(p0: Register, p1: Register, p2: Register) Instruction {
4598 return encodeFdFjFk(0x01088000, p0, p1, p2);
4599 }
4600
4601 /// Encodes a `fmaxa.d` instruction (requires f).
4602 pub inline fn @"fmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction {
4603 return encodeFdFjFk(0x010d0000, p0, p1, p2);
4604 }
4605
4606 /// Encodes a `fmaxa.s` instruction (requires f).
4607 pub inline fn @"fmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction {
4608 return encodeFdFjFk(0x010c8000, p0, p1, p2);
4609 }
4610
4611 /// Encodes a `fmin.d` instruction (requires f).
4612 pub inline fn @"fmin.d"(p0: Register, p1: Register, p2: Register) Instruction {
4613 return encodeFdFjFk(0x010b0000, p0, p1, p2);
4614 }
4615
4616 /// Encodes a `fmin.s` instruction (requires f).
4617 pub inline fn @"fmin.s"(p0: Register, p1: Register, p2: Register) Instruction {
4618 return encodeFdFjFk(0x010a8000, p0, p1, p2);
4619 }
4620
4621 /// Encodes a `fmina.d` instruction (requires f).
4622 pub inline fn @"fmina.d"(p0: Register, p1: Register, p2: Register) Instruction {
4623 return encodeFdFjFk(0x010f0000, p0, p1, p2);
4624 }
4625
4626 /// Encodes a `fmina.s` instruction (requires f).
4627 pub inline fn @"fmina.s"(p0: Register, p1: Register, p2: Register) Instruction {
4628 return encodeFdFjFk(0x010e8000, p0, p1, p2);
4629 }
4630
4631 /// Encodes a `fmov.d` instruction (requires f).
4632 pub inline fn @"fmov.d"(p0: Register, p1: Register) Instruction {
4633 return encodeFdFj(0x01149800, p0, p1);
4634 }
4635
4636 /// Encodes a `fmov.s` instruction (requires f).
4637 pub inline fn @"fmov.s"(p0: Register, p1: Register) Instruction {
4638 return encodeFdFj(0x01149400, p0, p1);
4639 }
4640
4641 /// Encodes a `fmsub.d` instruction (requires f).
4642 pub inline fn @"fmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4643 return encodeFdFjFkFa(0x08600000, p0, p1, p2, p3);
4644 }
4645
4646 /// Encodes a `fmsub.s` instruction (requires f).
4647 pub inline fn @"fmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4648 return encodeFdFjFkFa(0x08500000, p0, p1, p2, p3);
4649 }
4650
4651 /// Encodes a `fmul.d` instruction (requires f).
4652 pub inline fn @"fmul.d"(p0: Register, p1: Register, p2: Register) Instruction {
4653 return encodeFdFjFk(0x01050000, p0, p1, p2);
4654 }
4655
4656 /// Encodes a `fmul.s` instruction (requires f).
4657 pub inline fn @"fmul.s"(p0: Register, p1: Register, p2: Register) Instruction {
4658 return encodeFdFjFk(0x01048000, p0, p1, p2);
4659 }
4660
4661 /// Encodes a `fneg.d` instruction (requires f).
4662 pub inline fn @"fneg.d"(p0: Register, p1: Register) Instruction {
4663 return encodeFdFj(0x01141800, p0, p1);
4664 }
4665
4666 /// Encodes a `fneg.s` instruction (requires f).
4667 pub inline fn @"fneg.s"(p0: Register, p1: Register) Instruction {
4668 return encodeFdFj(0x01141400, p0, p1);
4669 }
4670
4671 /// Encodes a `fnmadd.d` instruction (requires f).
4672 pub inline fn @"fnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4673 return encodeFdFjFkFa(0x08a00000, p0, p1, p2, p3);
4674 }
4675
4676 /// Encodes a `fnmadd.s` instruction (requires f).
4677 pub inline fn @"fnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4678 return encodeFdFjFkFa(0x08900000, p0, p1, p2, p3);
4679 }
4680
4681 /// Encodes a `fnmsub.d` instruction (requires f).
4682 pub inline fn @"fnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4683 return encodeFdFjFkFa(0x08e00000, p0, p1, p2, p3);
4684 }
4685
4686 /// Encodes a `fnmsub.s` instruction (requires f).
4687 pub inline fn @"fnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4688 return encodeFdFjFkFa(0x08d00000, p0, p1, p2, p3);
4689 }
4690
4691 /// Encodes a `frecip.d` instruction (requires f).
4692 pub inline fn @"frecip.d"(p0: Register, p1: Register) Instruction {
4693 return encodeFdFj(0x01145800, p0, p1);
4694 }
4695
4696 /// Encodes a `frecip.s` instruction (requires f).
4697 pub inline fn @"frecip.s"(p0: Register, p1: Register) Instruction {
4698 return encodeFdFj(0x01145400, p0, p1);
4699 }
4700
4701 /// Encodes a `frecipe.d` instruction (requires f).
4702 pub inline fn @"frecipe.d"(p0: Register, p1: Register) Instruction {
4703 return encodeFdFj(0x01147800, p0, p1);
4704 }
4705
4706 /// Encodes a `frecipe.s` instruction (requires f).
4707 pub inline fn @"frecipe.s"(p0: Register, p1: Register) Instruction {
4708 return encodeFdFj(0x01147400, p0, p1);
4709 }
4710
4711 /// Encodes a `frint.d` instruction (requires f).
4712 pub inline fn @"frint.d"(p0: Register, p1: Register) Instruction {
4713 return encodeFdFj(0x011e4800, p0, p1);
4714 }
4715
4716 /// Encodes a `frint.s` instruction (requires f).
4717 pub inline fn @"frint.s"(p0: Register, p1: Register) Instruction {
4718 return encodeFdFj(0x011e4400, p0, p1);
4719 }
4720
4721 /// Encodes a `frsqrt.d` instruction (requires f).
4722 pub inline fn @"frsqrt.d"(p0: Register, p1: Register) Instruction {
4723 return encodeFdFj(0x01146800, p0, p1);
4724 }
4725
4726 /// Encodes a `frsqrt.s` instruction (requires f).
4727 pub inline fn @"frsqrt.s"(p0: Register, p1: Register) Instruction {
4728 return encodeFdFj(0x01146400, p0, p1);
4729 }
4730
4731 /// Encodes a `frsqrte.d` instruction (requires f).
4732 pub inline fn @"frsqrte.d"(p0: Register, p1: Register) Instruction {
4733 return encodeFdFj(0x01148800, p0, p1);
4734 }
4735
4736 /// Encodes a `frsqrte.s` instruction (requires f).
4737 pub inline fn @"frsqrte.s"(p0: Register, p1: Register) Instruction {
4738 return encodeFdFj(0x01148400, p0, p1);
4739 }
4740
4741 /// Encodes a `fscaleb.d` instruction (requires f).
4742 pub inline fn @"fscaleb.d"(p0: Register, p1: Register, p2: Register) Instruction {
4743 return encodeFdFjFk(0x01110000, p0, p1, p2);
4744 }
4745
4746 /// Encodes a `fscaleb.s` instruction (requires f).
4747 pub inline fn @"fscaleb.s"(p0: Register, p1: Register, p2: Register) Instruction {
4748 return encodeFdFjFk(0x01108000, p0, p1, p2);
4749 }
4750
4751 /// Encodes a `fsel` instruction (requires f).
4752 pub inline fn fsel(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
4753 return encodeFdFjFkCa(0x0d000000, p0, p1, p2, p3);
4754 }
4755
4756 /// Encodes a `fsqrt.d` instruction (requires f).
4757 pub inline fn @"fsqrt.d"(p0: Register, p1: Register) Instruction {
4758 return encodeFdFj(0x01144800, p0, p1);
4759 }
4760
4761 /// Encodes a `fsqrt.s` instruction (requires f).
4762 pub inline fn @"fsqrt.s"(p0: Register, p1: Register) Instruction {
4763 return encodeFdFj(0x01144400, p0, p1);
4764 }
4765
4766 /// Encodes a `fst.d` instruction (requires f).
4767 pub inline fn @"fst.d"(p0: Register, p1: Register, p2: i12) Instruction {
4768 return encodeFdJSk12(0x2bc00000, p0, p1, p2);
4769 }
4770
4771 /// Encodes a `fst.s` instruction (requires f).
4772 pub inline fn @"fst.s"(p0: Register, p1: Register, p2: i12) Instruction {
4773 return encodeFdJSk12(0x2b400000, p0, p1, p2);
4774 }
4775
4776 /// Encodes a `fstgt.d` instruction (requires f).
4777 pub inline fn @"fstgt.d"(p0: Register, p1: Register, p2: Register) Instruction {
4778 return encodeFdJK(0x38768000, p0, p1, p2);
4779 }
4780
4781 /// Encodes a `fstgt.s` instruction (requires f).
4782 pub inline fn @"fstgt.s"(p0: Register, p1: Register, p2: Register) Instruction {
4783 return encodeFdJK(0x38760000, p0, p1, p2);
4784 }
4785
4786 /// Encodes a `fstle.d` instruction (requires f).
4787 pub inline fn @"fstle.d"(p0: Register, p1: Register, p2: Register) Instruction {
4788 return encodeFdJK(0x38778000, p0, p1, p2);
4789 }
4790
4791 /// Encodes a `fstle.s` instruction (requires f).
4792 pub inline fn @"fstle.s"(p0: Register, p1: Register, p2: Register) Instruction {
4793 return encodeFdJK(0x38770000, p0, p1, p2);
4794 }
4795
4796 /// Encodes a `fstx.d` instruction (requires f).
4797 pub inline fn @"fstx.d"(p0: Register, p1: Register, p2: Register) Instruction {
4798 return encodeFdJK(0x383c0000, p0, p1, p2);
4799 }
4800
4801 /// Encodes a `fstx.s` instruction (requires f).
4802 pub inline fn @"fstx.s"(p0: Register, p1: Register, p2: Register) Instruction {
4803 return encodeFdJK(0x38380000, p0, p1, p2);
4804 }
4805
4806 /// Encodes a `fsub.d` instruction (requires f).
4807 pub inline fn @"fsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
4808 return encodeFdFjFk(0x01030000, p0, p1, p2);
4809 }
4810
4811 /// Encodes a `fsub.s` instruction (requires f).
4812 pub inline fn @"fsub.s"(p0: Register, p1: Register, p2: Register) Instruction {
4813 return encodeFdFjFk(0x01028000, p0, p1, p2);
4814 }
4815
4816 /// Encodes a `ftint.l.d` instruction (requires f).
4817 pub inline fn @"ftint.l.d"(p0: Register, p1: Register) Instruction {
4818 return encodeFdFj(0x011b2800, p0, p1);
4819 }
4820
4821 /// Encodes a `ftint.l.s` instruction (requires f).
4822 pub inline fn @"ftint.l.s"(p0: Register, p1: Register) Instruction {
4823 return encodeFdFj(0x011b2400, p0, p1);
4824 }
4825
4826 /// Encodes a `ftint.w.d` instruction (requires f).
4827 pub inline fn @"ftint.w.d"(p0: Register, p1: Register) Instruction {
4828 return encodeFdFj(0x011b0800, p0, p1);
4829 }
4830
4831 /// Encodes a `ftint.w.s` instruction (requires f).
4832 pub inline fn @"ftint.w.s"(p0: Register, p1: Register) Instruction {
4833 return encodeFdFj(0x011b0400, p0, p1);
4834 }
4835
4836 /// Encodes a `ftintrm.l.d` instruction (requires f).
4837 pub inline fn @"ftintrm.l.d"(p0: Register, p1: Register) Instruction {
4838 return encodeFdFj(0x011a2800, p0, p1);
4839 }
4840
4841 /// Encodes a `ftintrm.l.s` instruction (requires f).
4842 pub inline fn @"ftintrm.l.s"(p0: Register, p1: Register) Instruction {
4843 return encodeFdFj(0x011a2400, p0, p1);
4844 }
4845
4846 /// Encodes a `ftintrm.w.d` instruction (requires f).
4847 pub inline fn @"ftintrm.w.d"(p0: Register, p1: Register) Instruction {
4848 return encodeFdFj(0x011a0800, p0, p1);
4849 }
4850
4851 /// Encodes a `ftintrm.w.s` instruction (requires f).
4852 pub inline fn @"ftintrm.w.s"(p0: Register, p1: Register) Instruction {
4853 return encodeFdFj(0x011a0400, p0, p1);
4854 }
4855
4856 /// Encodes a `ftintrne.l.d` instruction (requires f).
4857 pub inline fn @"ftintrne.l.d"(p0: Register, p1: Register) Instruction {
4858 return encodeFdFj(0x011ae800, p0, p1);
4859 }
4860
4861 /// Encodes a `ftintrne.l.s` instruction (requires f).
4862 pub inline fn @"ftintrne.l.s"(p0: Register, p1: Register) Instruction {
4863 return encodeFdFj(0x011ae400, p0, p1);
4864 }
4865
4866 /// Encodes a `ftintrne.w.d` instruction (requires f).
4867 pub inline fn @"ftintrne.w.d"(p0: Register, p1: Register) Instruction {
4868 return encodeFdFj(0x011ac800, p0, p1);
4869 }
4870
4871 /// Encodes a `ftintrne.w.s` instruction (requires f).
4872 pub inline fn @"ftintrne.w.s"(p0: Register, p1: Register) Instruction {
4873 return encodeFdFj(0x011ac400, p0, p1);
4874 }
4875
4876 /// Encodes a `ftintrp.l.d` instruction (requires f).
4877 pub inline fn @"ftintrp.l.d"(p0: Register, p1: Register) Instruction {
4878 return encodeFdFj(0x011a6800, p0, p1);
4879 }
4880
4881 /// Encodes a `ftintrp.l.s` instruction (requires f).
4882 pub inline fn @"ftintrp.l.s"(p0: Register, p1: Register) Instruction {
4883 return encodeFdFj(0x011a6400, p0, p1);
4884 }
4885
4886 /// Encodes a `ftintrp.w.d` instruction (requires f).
4887 pub inline fn @"ftintrp.w.d"(p0: Register, p1: Register) Instruction {
4888 return encodeFdFj(0x011a4800, p0, p1);
4889 }
4890
4891 /// Encodes a `ftintrp.w.s` instruction (requires f).
4892 pub inline fn @"ftintrp.w.s"(p0: Register, p1: Register) Instruction {
4893 return encodeFdFj(0x011a4400, p0, p1);
4894 }
4895
4896 /// Encodes a `ftintrz.l.d` instruction (requires f).
4897 pub inline fn @"ftintrz.l.d"(p0: Register, p1: Register) Instruction {
4898 return encodeFdFj(0x011aa800, p0, p1);
4899 }
4900
4901 /// Encodes a `ftintrz.l.s` instruction (requires f).
4902 pub inline fn @"ftintrz.l.s"(p0: Register, p1: Register) Instruction {
4903 return encodeFdFj(0x011aa400, p0, p1);
4904 }
4905
4906 /// Encodes a `ftintrz.w.d` instruction (requires f).
4907 pub inline fn @"ftintrz.w.d"(p0: Register, p1: Register) Instruction {
4908 return encodeFdFj(0x011a8800, p0, p1);
4909 }
4910
4911 /// Encodes a `ftintrz.w.s` instruction (requires f).
4912 pub inline fn @"ftintrz.w.s"(p0: Register, p1: Register) Instruction {
4913 return encodeFdFj(0x011a8400, p0, p1);
4914 }
4915
4916 /// Encodes a `gcsrrd` instruction (requires 64bit).
4917 pub inline fn gcsrrd(p0: Register, p1: u14) Instruction {
4918 return encodeDUk14(0x05000000, p0, p1);
4919 }
4920
4921 /// Encodes a `gcsrwr` instruction (requires 64bit).
4922 pub inline fn gcsrwr(p0: Register, p1: u14) Instruction {
4923 return encodeDUk14(0x05000032, p0, p1);
4924 }
4925
4926 /// Encodes a `gcsrxchg` instruction (requires 64bit).
4927 pub inline fn gcsrxchg(p0: Register, p1: Register, p2: u14) Instruction {
4928 return encodeDJUk14(0x05000000, p0, p1, p2);
4929 }
4930
4931 /// Encodes a `gtlbclr` instruction (requires 64bit).
4932 pub inline fn gtlbclr() Instruction {
4933 return encodeEMPTY(0x06482001);
4934 }
4935
4936 /// Encodes a `gtlbfill` instruction (requires 64bit).
4937 pub inline fn gtlbfill() Instruction {
4938 return encodeEMPTY(0x06483401);
4939 }
4940
4941 /// Encodes a `gtlbflush` instruction (requires 64bit).
4942 pub inline fn gtlbflush() Instruction {
4943 return encodeEMPTY(0x06482401);
4944 }
4945
4946 /// Encodes a `gtlbrd` instruction (requires 64bit).
4947 pub inline fn gtlbrd() Instruction {
4948 return encodeEMPTY(0x06482c01);
4949 }
4950
4951 /// Encodes a `gtlbsrch` instruction (requires 64bit).
4952 pub inline fn gtlbsrch() Instruction {
4953 return encodeEMPTY(0x06482801);
4954 }
4955
4956 /// Encodes a `gtlbwr` instruction (requires 64bit).
4957 pub inline fn gtlbwr() Instruction {
4958 return encodeEMPTY(0x06483001);
4959 }
4960
4961 /// Encodes a `hypcall` instruction (requires 64bit).
4962 pub inline fn hypcall(p0: u15) Instruction {
4963 return encodeUd15(0x002b8000, p0);
4964 }
4965
4966 /// Encodes a `ibar` instruction (requires 32bit).
4967 pub inline fn ibar(p0: u15) Instruction {
4968 return encodeUd15(0x38728000, p0);
4969 }
4970
4971 /// Encodes a `idle` instruction (requires 32bit).
4972 pub inline fn idle(p0: u15) Instruction {
4973 return encodeUd15(0x06488000, p0);
4974 }
4975
4976 /// Encodes a `iocsrrd.b` instruction (requires 64bit).
4977 pub inline fn @"iocsrrd.b"(p0: Register, p1: Register) Instruction {
4978 return encodeDJ(0x06480000, p0, p1);
4979 }
4980
4981 /// Encodes a `iocsrrd.d` instruction (requires 64bit).
4982 pub inline fn @"iocsrrd.d"(p0: Register, p1: Register) Instruction {
4983 return encodeDJ(0x06480c00, p0, p1);
4984 }
4985
4986 /// Encodes a `iocsrrd.h` instruction (requires 64bit).
4987 pub inline fn @"iocsrrd.h"(p0: Register, p1: Register) Instruction {
4988 return encodeDJ(0x06480400, p0, p1);
4989 }
4990
4991 /// Encodes a `iocsrrd.w` instruction (requires 64bit).
4992 pub inline fn @"iocsrrd.w"(p0: Register, p1: Register) Instruction {
4993 return encodeDJ(0x06480800, p0, p1);
4994 }
4995
4996 /// Encodes a `iocsrwr.b` instruction (requires 64bit).
4997 pub inline fn @"iocsrwr.b"(p0: Register, p1: Register) Instruction {
4998 return encodeDJ(0x06481000, p0, p1);
4999 }
5000
5001 /// Encodes a `iocsrwr.d` instruction (requires 64bit).
5002 pub inline fn @"iocsrwr.d"(p0: Register, p1: Register) Instruction {
5003 return encodeDJ(0x06481c00, p0, p1);
5004 }
5005
5006 /// Encodes a `iocsrwr.h` instruction (requires 64bit).
5007 pub inline fn @"iocsrwr.h"(p0: Register, p1: Register) Instruction {
5008 return encodeDJ(0x06481400, p0, p1);
5009 }
5010
5011 /// Encodes a `iocsrwr.w` instruction (requires 64bit).
5012 pub inline fn @"iocsrwr.w"(p0: Register, p1: Register) Instruction {
5013 return encodeDJ(0x06481800, p0, p1);
5014 }
5015
5016 /// Encodes a `jirl` instruction (requires 32bit).
5017 pub inline fn jirl(p0: Register, p1: Register, p2: i16) Instruction {
5018 return encodeDJSk16ps2(0x4c000000, p0, p1, p2);
5019 }
5020
5021 /// Encodes a `jiscr0` instruction (requires 64bit).
5022 pub inline fn jiscr0(p0: i5, p1: i16) Instruction {
5023 return encodeSd5k16ps2(0x48000200, p0, p1);
5024 }
5025
5026 /// Encodes a `jiscr1` instruction (requires 64bit).
5027 pub inline fn jiscr1(p0: i5, p1: i16) Instruction {
5028 return encodeSd5k16ps2(0x48000300, p0, p1);
5029 }
5030
5031 /// Encodes a `ld.b` instruction (requires 32bit).
5032 pub inline fn @"ld.b"(p0: Register, p1: Register, p2: i12) Instruction {
5033 return encodeDJSk12(0x28000000, p0, p1, p2);
5034 }
5035
5036 /// Encodes a `ld.bu` instruction (requires 32bit).
5037 pub inline fn @"ld.bu"(p0: Register, p1: Register, p2: i12) Instruction {
5038 return encodeDJSk12(0x2a000000, p0, p1, p2);
5039 }
5040
5041 /// Encodes a `ld.d` instruction (requires 64bit).
5042 pub inline fn @"ld.d"(p0: Register, p1: Register, p2: i12) Instruction {
5043 return encodeDJSk12(0x28c00000, p0, p1, p2);
5044 }
5045
5046 /// Encodes a `ld.h` instruction (requires 32bit).
5047 pub inline fn @"ld.h"(p0: Register, p1: Register, p2: i12) Instruction {
5048 return encodeDJSk12(0x28400000, p0, p1, p2);
5049 }
5050
5051 /// Encodes a `ld.hu` instruction (requires 32bit).
5052 pub inline fn @"ld.hu"(p0: Register, p1: Register, p2: i12) Instruction {
5053 return encodeDJSk12(0x2a400000, p0, p1, p2);
5054 }
5055
5056 /// Encodes a `ld.w` instruction (requires 32bit).
5057 pub inline fn @"ld.w"(p0: Register, p1: Register, p2: i12) Instruction {
5058 return encodeDJSk12(0x28800000, p0, p1, p2);
5059 }
5060
5061 /// Encodes a `ld.wu` instruction (requires 64bit).
5062 pub inline fn @"ld.wu"(p0: Register, p1: Register, p2: i12) Instruction {
5063 return encodeDJSk12(0x2a800000, p0, p1, p2);
5064 }
5065
5066 /// Encodes a `lddir` instruction (requires 64bit).
5067 pub inline fn lddir(p0: Register, p1: Register, p2: u8) Instruction {
5068 return encodeDJUk8(0x06400000, p0, p1, p2);
5069 }
5070
5071 /// Encodes a `ldgt.b` instruction (requires 64bit).
5072 pub inline fn @"ldgt.b"(p0: Register, p1: Register, p2: Register) Instruction {
5073 return encodeDJK(0x38780000, p0, p1, p2);
5074 }
5075
5076 /// Encodes a `ldgt.d` instruction (requires 64bit).
5077 pub inline fn @"ldgt.d"(p0: Register, p1: Register, p2: Register) Instruction {
5078 return encodeDJK(0x38798000, p0, p1, p2);
5079 }
5080
5081 /// Encodes a `ldgt.h` instruction (requires 64bit).
5082 pub inline fn @"ldgt.h"(p0: Register, p1: Register, p2: Register) Instruction {
5083 return encodeDJK(0x38788000, p0, p1, p2);
5084 }
5085
5086 /// Encodes a `ldgt.w` instruction (requires 64bit).
5087 pub inline fn @"ldgt.w"(p0: Register, p1: Register, p2: Register) Instruction {
5088 return encodeDJK(0x38790000, p0, p1, p2);
5089 }
5090
5091 /// Encodes a `ldl.d` instruction (requires 64bit).
5092 pub inline fn @"ldl.d"(p0: Register, p1: Register, p2: i12) Instruction {
5093 return encodeDJSk12(0x2e800000, p0, p1, p2);
5094 }
5095
5096 /// Encodes a `ldl.w` instruction (requires 64bit).
5097 pub inline fn @"ldl.w"(p0: Register, p1: Register, p2: i12) Instruction {
5098 return encodeDJSk12(0x2e000000, p0, p1, p2);
5099 }
5100
5101 /// Encodes a `ldle.b` instruction (requires 64bit).
5102 pub inline fn @"ldle.b"(p0: Register, p1: Register, p2: Register) Instruction {
5103 return encodeDJK(0x387a0000, p0, p1, p2);
5104 }
5105
5106 /// Encodes a `ldle.d` instruction (requires 64bit).
5107 pub inline fn @"ldle.d"(p0: Register, p1: Register, p2: Register) Instruction {
5108 return encodeDJK(0x387b8000, p0, p1, p2);
5109 }
5110
5111 /// Encodes a `ldle.h` instruction (requires 64bit).
5112 pub inline fn @"ldle.h"(p0: Register, p1: Register, p2: Register) Instruction {
5113 return encodeDJK(0x387a8000, p0, p1, p2);
5114 }
5115
5116 /// Encodes a `ldle.w` instruction (requires 64bit).
5117 pub inline fn @"ldle.w"(p0: Register, p1: Register, p2: Register) Instruction {
5118 return encodeDJK(0x387b0000, p0, p1, p2);
5119 }
5120
5121 /// Encodes a `ldox4.d` instruction (requires 64bit).
5122 pub inline fn @"ldox4.d"(p0: Register, p1: Register, p2: i14) Instruction {
5123 return encodeDJSk14(0x26000000, p0, p1, p2);
5124 }
5125
5126 /// Encodes a `ldox4.w` instruction (requires 64bit).
5127 pub inline fn @"ldox4.w"(p0: Register, p1: Register, p2: i14) Instruction {
5128 return encodeDJSk14(0x24000000, p0, p1, p2);
5129 }
5130
5131 /// Encodes a `ldpte` instruction (requires 64bit).
5132 pub inline fn ldpte(p0: Register, p1: u8) Instruction {
5133 return encodeJUk8(0x06440000, p0, p1);
5134 }
5135
5136 /// Encodes a `ldr.d` instruction (requires 64bit).
5137 pub inline fn @"ldr.d"(p0: Register, p1: Register, p2: i12) Instruction {
5138 return encodeDJSk12(0x2ec00000, p0, p1, p2);
5139 }
5140
5141 /// Encodes a `ldr.w` instruction (requires 64bit).
5142 pub inline fn @"ldr.w"(p0: Register, p1: Register, p2: i12) Instruction {
5143 return encodeDJSk12(0x2e400000, p0, p1, p2);
5144 }
5145
5146 /// Encodes a `ldx.b` instruction (requires 64bit).
5147 pub inline fn @"ldx.b"(p0: Register, p1: Register, p2: Register) Instruction {
5148 return encodeDJK(0x38000000, p0, p1, p2);
5149 }
5150
5151 /// Encodes a `ldx.bu` instruction (requires 64bit).
5152 pub inline fn @"ldx.bu"(p0: Register, p1: Register, p2: Register) Instruction {
5153 return encodeDJK(0x38200000, p0, p1, p2);
5154 }
5155
5156 /// Encodes a `ldx.d` instruction (requires 64bit).
5157 pub inline fn @"ldx.d"(p0: Register, p1: Register, p2: Register) Instruction {
5158 return encodeDJK(0x380c0000, p0, p1, p2);
5159 }
5160
5161 /// Encodes a `ldx.h` instruction (requires 64bit).
5162 pub inline fn @"ldx.h"(p0: Register, p1: Register, p2: Register) Instruction {
5163 return encodeDJK(0x38040000, p0, p1, p2);
5164 }
5165
5166 /// Encodes a `ldx.hu` instruction (requires 64bit).
5167 pub inline fn @"ldx.hu"(p0: Register, p1: Register, p2: Register) Instruction {
5168 return encodeDJK(0x38240000, p0, p1, p2);
5169 }
5170
5171 /// Encodes a `ldx.w` instruction (requires 64bit).
5172 pub inline fn @"ldx.w"(p0: Register, p1: Register, p2: Register) Instruction {
5173 return encodeDJK(0x38080000, p0, p1, p2);
5174 }
5175
5176 /// Encodes a `ldx.wu` instruction (requires 64bit).
5177 pub inline fn @"ldx.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5178 return encodeDJK(0x38280000, p0, p1, p2);
5179 }
5180
5181 /// Encodes a `ll.d` instruction (requires 64bit).
5182 pub inline fn @"ll.d"(p0: Register, p1: Register, p2: i14) Instruction {
5183 return encodeDJSk14ps2(0x22000000, p0, p1, p2);
5184 }
5185
5186 /// Encodes a `ll.w` instruction (requires 32bit).
5187 pub inline fn @"ll.w"(p0: Register, p1: Register, p2: i14) Instruction {
5188 return encodeDJSk14ps2(0x20000000, p0, p1, p2);
5189 }
5190
5191 /// Encodes a `llacq.d` instruction (requires 64bit).
5192 pub inline fn @"llacq.d"(p0: Register, p1: Register) Instruction {
5193 return encodeDJ(0x38578800, p0, p1);
5194 }
5195
5196 /// Encodes a `llacq.w` instruction (requires 64bit).
5197 pub inline fn @"llacq.w"(p0: Register, p1: Register) Instruction {
5198 return encodeDJ(0x38578000, p0, p1);
5199 }
5200
5201 /// Encodes a `lu12i.w` instruction (requires 32bit).
5202 pub inline fn @"lu12i.w"(p0: Register, p1: i20) Instruction {
5203 return encodeDSj20(0x14000000, p0, p1);
5204 }
5205
5206 /// Encodes a `maskeqz` instruction (requires 32s).
5207 pub inline fn maskeqz(p0: Register, p1: Register, p2: Register) Instruction {
5208 return encodeDJK(0x00130000, p0, p1, p2);
5209 }
5210
5211 /// Encodes a `masknez` instruction (requires 32s).
5212 pub inline fn masknez(p0: Register, p1: Register, p2: Register) Instruction {
5213 return encodeDJK(0x00138000, p0, p1, p2);
5214 }
5215
5216 /// Encodes a `mod.d` instruction (requires 64bit).
5217 pub inline fn @"mod.d"(p0: Register, p1: Register, p2: Register) Instruction {
5218 return encodeDJK(0x00228000, p0, p1, p2);
5219 }
5220
5221 /// Encodes a `mod.du` instruction (requires 64bit).
5222 pub inline fn @"mod.du"(p0: Register, p1: Register, p2: Register) Instruction {
5223 return encodeDJK(0x00238000, p0, p1, p2);
5224 }
5225
5226 /// Encodes a `mod.w` instruction (requires 32bit).
5227 pub inline fn @"mod.w"(p0: Register, p1: Register, p2: Register) Instruction {
5228 return encodeDJK(0x00208000, p0, p1, p2);
5229 }
5230
5231 /// Encodes a `mod.wu` instruction (requires 32bit).
5232 pub inline fn @"mod.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5233 return encodeDJK(0x00218000, p0, p1, p2);
5234 }
5235
5236 /// Encodes a `movfcc2fr` instruction (requires f).
5237 pub inline fn movfcc2fr(p0: Register, p1: Register) Instruction {
5238 return encodeFdCj(0x0114d400, p0, p1);
5239 }
5240
5241 /// Encodes a `movfcc2gr` instruction (requires f).
5242 pub inline fn movfcc2gr(p0: Register, p1: Register) Instruction {
5243 return encodeDCj(0x0114dc00, p0, p1);
5244 }
5245
5246 /// Encodes a `movfr2fcc` instruction (requires f).
5247 pub inline fn movfr2fcc(p0: Register, p1: Register) Instruction {
5248 return encodeCdFj(0x0114d000, p0, p1);
5249 }
5250
5251 /// Encodes a `movfr2gr.d` instruction (requires f).
5252 pub inline fn @"movfr2gr.d"(p0: Register, p1: Register) Instruction {
5253 return encodeDFj(0x0114b800, p0, p1);
5254 }
5255
5256 /// Encodes a `movfr2gr.s` instruction (requires f).
5257 pub inline fn @"movfr2gr.s"(p0: Register, p1: Register) Instruction {
5258 return encodeDFj(0x0114b400, p0, p1);
5259 }
5260
5261 /// Encodes a `movfrh2gr.s` instruction (requires f).
5262 pub inline fn @"movfrh2gr.s"(p0: Register, p1: Register) Instruction {
5263 return encodeDFj(0x0114bc00, p0, p1);
5264 }
5265
5266 /// Encodes a `movgr2fcc` instruction (requires f).
5267 pub inline fn movgr2fcc(p0: Register, p1: Register) Instruction {
5268 return encodeCdJ(0x0114d800, p0, p1);
5269 }
5270
5271 /// Encodes a `movgr2fr.d` instruction (requires f).
5272 pub inline fn @"movgr2fr.d"(p0: Register, p1: Register) Instruction {
5273 return encodeFdJ(0x0114a800, p0, p1);
5274 }
5275
5276 /// Encodes a `movgr2fr.w` instruction (requires f).
5277 pub inline fn @"movgr2fr.w"(p0: Register, p1: Register) Instruction {
5278 return encodeFdJ(0x0114a400, p0, p1);
5279 }
5280
5281 /// Encodes a `movgr2frh.w` instruction (requires f).
5282 pub inline fn @"movgr2frh.w"(p0: Register, p1: Register) Instruction {
5283 return encodeFdJ(0x0114ac00, p0, p1);
5284 }
5285
5286 /// Encodes a `movgr2scr` instruction (requires lbt).
5287 pub inline fn movgr2scr(p0: Register, p1: Register) Instruction {
5288 return encodeTdJ(0x00000800, p0, p1);
5289 }
5290
5291 /// Encodes a `movscr2gr` instruction (requires lbt).
5292 pub inline fn movscr2gr(p0: Register, p1: Register) Instruction {
5293 return encodeDTj(0x00000c00, p0, p1);
5294 }
5295
5296 /// Encodes a `mul.d` instruction (requires 64bit).
5297 pub inline fn @"mul.d"(p0: Register, p1: Register, p2: Register) Instruction {
5298 return encodeDJK(0x001d8000, p0, p1, p2);
5299 }
5300
5301 /// Encodes a `mul.w` instruction (requires 32bit).
5302 pub inline fn @"mul.w"(p0: Register, p1: Register, p2: Register) Instruction {
5303 return encodeDJK(0x001c0000, p0, p1, p2);
5304 }
5305
5306 /// Encodes a `mulh.d` instruction (requires 64bit).
5307 pub inline fn @"mulh.d"(p0: Register, p1: Register, p2: Register) Instruction {
5308 return encodeDJK(0x001e0000, p0, p1, p2);
5309 }
5310
5311 /// Encodes a `mulh.du` instruction (requires 64bit).
5312 pub inline fn @"mulh.du"(p0: Register, p1: Register, p2: Register) Instruction {
5313 return encodeDJK(0x001e8000, p0, p1, p2);
5314 }
5315
5316 /// Encodes a `mulh.w` instruction (requires 32bit).
5317 pub inline fn @"mulh.w"(p0: Register, p1: Register, p2: Register) Instruction {
5318 return encodeDJK(0x001c8000, p0, p1, p2);
5319 }
5320
5321 /// Encodes a `mulh.wu` instruction (requires 32bit).
5322 pub inline fn @"mulh.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5323 return encodeDJK(0x001d0000, p0, p1, p2);
5324 }
5325
5326 /// Encodes a `mulw.d.w` instruction (requires 64bit).
5327 pub inline fn @"mulw.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
5328 return encodeDJK(0x001f0000, p0, p1, p2);
5329 }
5330
5331 /// Encodes a `mulw.d.wu` instruction (requires 64bit).
5332 pub inline fn @"mulw.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5333 return encodeDJK(0x001f8000, p0, p1, p2);
5334 }
5335
5336 /// Encodes a `nor` instruction (requires 32bit).
5337 pub inline fn nor(p0: Register, p1: Register, p2: Register) Instruction {
5338 return encodeDJK(0x00140000, p0, p1, p2);
5339 }
5340
5341 /// Encodes a `or` instruction (requires 32bit).
5342 pub inline fn @"or"(p0: Register, p1: Register, p2: Register) Instruction {
5343 return encodeDJK(0x00150000, p0, p1, p2);
5344 }
5345
5346 /// Encodes a `ori` instruction (requires 32bit).
5347 pub inline fn ori(p0: Register, p1: Register, p2: u12) Instruction {
5348 return encodeDJUk12(0x03800000, p0, p1, p2);
5349 }
5350
5351 /// Encodes a `orn` instruction (requires 32bit).
5352 pub inline fn orn(p0: Register, p1: Register, p2: Register) Instruction {
5353 return encodeDJK(0x00160000, p0, p1, p2);
5354 }
5355
5356 /// Encodes a `pcaddu12i` instruction (requires 32bit).
5357 pub inline fn pcaddu12i(p0: Register, p1: i20) Instruction {
5358 return encodeDSj20(0x1c000000, p0, p1);
5359 }
5360
5361 /// Encodes a `pcaddu18i` instruction (requires 64bit).
5362 pub inline fn pcaddu18i(p0: Register, p1: i20) Instruction {
5363 return encodeDSj20(0x1e000000, p0, p1);
5364 }
5365
5366 /// Encodes a `pcaddu2i` instruction (requires 32bit).
5367 pub inline fn pcaddu2i(p0: Register, p1: i20) Instruction {
5368 return encodeDSj20(0x18000000, p0, p1);
5369 }
5370
5371 /// Encodes a `pcalau12i` instruction (requires 32s).
5372 pub inline fn pcalau12i(p0: Register, p1: i20) Instruction {
5373 return encodeDSj20(0x1a000000, p0, p1);
5374 }
5375
5376 /// Encodes a `preld` instruction (requires 32bit).
5377 pub inline fn preld(p0: u5, p1: Register, p2: i12) Instruction {
5378 return encodeUd5JSk12(0x2ac00000, p0, p1, p2);
5379 }
5380
5381 /// Encodes a `preldx` instruction (requires 64bit).
5382 pub inline fn preldx(p0: u5, p1: Register, p2: Register) Instruction {
5383 return encodeUd5JK(0x382c0000, p0, p1, p2);
5384 }
5385
5386 /// Encodes a `rcr.b` instruction (requires 64bit).
5387 pub inline fn @"rcr.b"(p0: Register, p1: Register, p2: Register) Instruction {
5388 return encodeDJK(0x00340000, p0, p1, p2);
5389 }
5390
5391 /// Encodes a `rcr.d` instruction (requires 64bit).
5392 pub inline fn @"rcr.d"(p0: Register, p1: Register, p2: Register) Instruction {
5393 return encodeDJK(0x00358000, p0, p1, p2);
5394 }
5395
5396 /// Encodes a `rcr.h` instruction (requires 64bit).
5397 pub inline fn @"rcr.h"(p0: Register, p1: Register, p2: Register) Instruction {
5398 return encodeDJK(0x00348000, p0, p1, p2);
5399 }
5400
5401 /// Encodes a `rcr.w` instruction (requires 64bit).
5402 pub inline fn @"rcr.w"(p0: Register, p1: Register, p2: Register) Instruction {
5403 return encodeDJK(0x00350000, p0, p1, p2);
5404 }
5405
5406 /// Encodes a `rcri.b` instruction (requires 64bit).
5407 pub inline fn @"rcri.b"(p0: Register, p1: Register, p2: u3) Instruction {
5408 return encodeDJUk3(0x00502000, p0, p1, p2);
5409 }
5410
5411 /// Encodes a `rcri.d` instruction (requires 64bit).
5412 pub inline fn @"rcri.d"(p0: Register, p1: Register, p2: u6) Instruction {
5413 return encodeDJUk6(0x00510000, p0, p1, p2);
5414 }
5415
5416 /// Encodes a `rcri.h` instruction (requires 64bit).
5417 pub inline fn @"rcri.h"(p0: Register, p1: Register, p2: u4) Instruction {
5418 return encodeDJUk4(0x00504000, p0, p1, p2);
5419 }
5420
5421 /// Encodes a `rcri.w` instruction (requires 64bit).
5422 pub inline fn @"rcri.w"(p0: Register, p1: Register, p2: u5) Instruction {
5423 return encodeDJUk5(0x00508000, p0, p1, p2);
5424 }
5425
5426 /// Encodes a `rdtime.d` instruction (requires 64bit).
5427 pub inline fn @"rdtime.d"(p0: Register, p1: Register) Instruction {
5428 return encodeDJ(0x00006800, p0, p1);
5429 }
5430
5431 /// Encodes a `rdtimeh.w` instruction (requires 32bit).
5432 pub inline fn @"rdtimeh.w"(p0: Register, p1: Register) Instruction {
5433 return encodeDJ(0x00006400, p0, p1);
5434 }
5435
5436 /// Encodes a `rdtimel.w` instruction (requires 32bit).
5437 pub inline fn @"rdtimel.w"(p0: Register, p1: Register) Instruction {
5438 return encodeDJ(0x00006000, p0, p1);
5439 }
5440
5441 /// Encodes a `revb.2h` instruction (requires 32s).
5442 pub inline fn @"revb.2h"(p0: Register, p1: Register) Instruction {
5443 return encodeDJ(0x00003000, p0, p1);
5444 }
5445
5446 /// Encodes a `revb.2w` instruction (requires 64bit).
5447 pub inline fn @"revb.2w"(p0: Register, p1: Register) Instruction {
5448 return encodeDJ(0x00003800, p0, p1);
5449 }
5450
5451 /// Encodes a `revb.4h` instruction (requires 64bit).
5452 pub inline fn @"revb.4h"(p0: Register, p1: Register) Instruction {
5453 return encodeDJ(0x00003400, p0, p1);
5454 }
5455
5456 /// Encodes a `revb.d` instruction (requires 64bit).
5457 pub inline fn @"revb.d"(p0: Register, p1: Register) Instruction {
5458 return encodeDJ(0x00003c00, p0, p1);
5459 }
5460
5461 /// Encodes a `revbit.4b` instruction (requires 32s).
5462 pub inline fn @"revbit.4b"(p0: Register, p1: Register) Instruction {
5463 return encodeDJ(0x00004800, p0, p1);
5464 }
5465
5466 /// Encodes a `revbit.8b` instruction (requires 64bit).
5467 pub inline fn @"revbit.8b"(p0: Register, p1: Register) Instruction {
5468 return encodeDJ(0x00004c00, p0, p1);
5469 }
5470
5471 /// Encodes a `revbit.d` instruction (requires 64bit).
5472 pub inline fn @"revbit.d"(p0: Register, p1: Register) Instruction {
5473 return encodeDJ(0x00005400, p0, p1);
5474 }
5475
5476 /// Encodes a `revbit.w` instruction (requires 32s).
5477 pub inline fn @"revbit.w"(p0: Register, p1: Register) Instruction {
5478 return encodeDJ(0x00005000, p0, p1);
5479 }
5480
5481 /// Encodes a `revh.2w` instruction (requires 64bit).
5482 pub inline fn @"revh.2w"(p0: Register, p1: Register) Instruction {
5483 return encodeDJ(0x00004000, p0, p1);
5484 }
5485
5486 /// Encodes a `revh.d` instruction (requires 64bit).
5487 pub inline fn @"revh.d"(p0: Register, p1: Register) Instruction {
5488 return encodeDJ(0x00004400, p0, p1);
5489 }
5490
5491 /// Encodes a `rotr.b` instruction (requires 64bit).
5492 pub inline fn @"rotr.b"(p0: Register, p1: Register, p2: Register) Instruction {
5493 return encodeDJK(0x001a0000, p0, p1, p2);
5494 }
5495
5496 /// Encodes a `rotr.d` instruction (requires 64bit).
5497 pub inline fn @"rotr.d"(p0: Register, p1: Register, p2: Register) Instruction {
5498 return encodeDJK(0x001b8000, p0, p1, p2);
5499 }
5500
5501 /// Encodes a `rotr.h` instruction (requires 64bit).
5502 pub inline fn @"rotr.h"(p0: Register, p1: Register, p2: Register) Instruction {
5503 return encodeDJK(0x001a8000, p0, p1, p2);
5504 }
5505
5506 /// Encodes a `rotr.w` instruction (requires 32s).
5507 pub inline fn @"rotr.w"(p0: Register, p1: Register, p2: Register) Instruction {
5508 return encodeDJK(0x001b0000, p0, p1, p2);
5509 }
5510
5511 /// Encodes a `rotri.b` instruction (requires 64bit).
5512 pub inline fn @"rotri.b"(p0: Register, p1: Register, p2: u3) Instruction {
5513 return encodeDJUk3(0x004c2000, p0, p1, p2);
5514 }
5515
5516 /// Encodes a `rotri.d` instruction (requires 64bit).
5517 pub inline fn @"rotri.d"(p0: Register, p1: Register, p2: u6) Instruction {
5518 return encodeDJUk6(0x004d0000, p0, p1, p2);
5519 }
5520
5521 /// Encodes a `rotri.h` instruction (requires 64bit).
5522 pub inline fn @"rotri.h"(p0: Register, p1: Register, p2: u4) Instruction {
5523 return encodeDJUk4(0x004c4000, p0, p1, p2);
5524 }
5525
5526 /// Encodes a `rotri.w` instruction (requires 32s).
5527 pub inline fn @"rotri.w"(p0: Register, p1: Register, p2: u5) Instruction {
5528 return encodeDJUk5(0x004c8000, p0, p1, p2);
5529 }
5530
5531 /// Encodes a `sbc.b` instruction (requires 64bit).
5532 pub inline fn @"sbc.b"(p0: Register, p1: Register, p2: Register) Instruction {
5533 return encodeDJK(0x00320000, p0, p1, p2);
5534 }
5535
5536 /// Encodes a `sbc.d` instruction (requires 64bit).
5537 pub inline fn @"sbc.d"(p0: Register, p1: Register, p2: Register) Instruction {
5538 return encodeDJK(0x00338000, p0, p1, p2);
5539 }
5540
5541 /// Encodes a `sbc.h` instruction (requires 64bit).
5542 pub inline fn @"sbc.h"(p0: Register, p1: Register, p2: Register) Instruction {
5543 return encodeDJK(0x00328000, p0, p1, p2);
5544 }
5545
5546 /// Encodes a `sbc.w` instruction (requires 64bit).
5547 pub inline fn @"sbc.w"(p0: Register, p1: Register, p2: Register) Instruction {
5548 return encodeDJK(0x00330000, p0, p1, p2);
5549 }
5550
5551 /// Encodes a `sc.d` instruction (requires 64bit).
5552 pub inline fn @"sc.d"(p0: Register, p1: Register, p2: i14) Instruction {
5553 return encodeDJSk14ps2(0x23000000, p0, p1, p2);
5554 }
5555
5556 /// Encodes a `sc.q` instruction (requires 64bit).
5557 pub inline fn @"sc.q"(p0: Register, p1: Register, p2: Register) Instruction {
5558 return encodeDKJ(0x38570000, p0, p1, p2);
5559 }
5560
5561 /// Encodes a `sc.w` instruction (requires 32bit).
5562 pub inline fn @"sc.w"(p0: Register, p1: Register, p2: i14) Instruction {
5563 return encodeDJSk14ps2(0x21000000, p0, p1, p2);
5564 }
5565
5566 /// Encodes a `screl.d` instruction (requires 64bit).
5567 pub inline fn @"screl.d"(p0: Register, p1: Register) Instruction {
5568 return encodeDJ(0x38578c00, p0, p1);
5569 }
5570
5571 /// Encodes a `screl.w` instruction (requires 64bit).
5572 pub inline fn @"screl.w"(p0: Register, p1: Register) Instruction {
5573 return encodeDJ(0x38578400, p0, p1);
5574 }
5575
5576 /// Encodes a `sext.b` instruction (requires 32s).
5577 pub inline fn @"sext.b"(p0: Register, p1: Register) Instruction {
5578 return encodeDJ(0x00005c00, p0, p1);
5579 }
5580
5581 /// Encodes a `sext.h` instruction (requires 32s).
5582 pub inline fn @"sext.h"(p0: Register, p1: Register) Instruction {
5583 return encodeDJ(0x00005800, p0, p1);
5584 }
5585
5586 /// Encodes a `sladd.d` instruction (requires 64bit).
5587 pub inline fn @"sladd.d"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
5588 return encodeDJKUa2(0x002c0000, p0, p1, p2, p3);
5589 }
5590
5591 /// Encodes a `sladd.w` instruction (requires 32s).
5592 pub inline fn @"sladd.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
5593 return encodeDJKUa2(0x00040000, p0, p1, p2, p3);
5594 }
5595
5596 /// Encodes a `sladd.wu` instruction (requires 64bit).
5597 pub inline fn @"sladd.wu"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction {
5598 return encodeDJKUa2(0x00060000, p0, p1, p2, p3);
5599 }
5600
5601 /// Encodes a `sll.d` instruction (requires 64bit).
5602 pub inline fn @"sll.d"(p0: Register, p1: Register, p2: Register) Instruction {
5603 return encodeDJK(0x00188000, p0, p1, p2);
5604 }
5605
5606 /// Encodes a `sll.w` instruction (requires 32bit).
5607 pub inline fn @"sll.w"(p0: Register, p1: Register, p2: Register) Instruction {
5608 return encodeDJK(0x00170000, p0, p1, p2);
5609 }
5610
5611 /// Encodes a `slli.d` instruction (requires 64bit).
5612 pub inline fn @"slli.d"(p0: Register, p1: Register, p2: u6) Instruction {
5613 return encodeDJUk6(0x00410000, p0, p1, p2);
5614 }
5615
5616 /// Encodes a `slli.w` instruction (requires 32bit).
5617 pub inline fn @"slli.w"(p0: Register, p1: Register, p2: u5) Instruction {
5618 return encodeDJUk5(0x00408000, p0, p1, p2);
5619 }
5620
5621 /// Encodes a `slt` instruction (requires 32bit).
5622 pub inline fn slt(p0: Register, p1: Register, p2: Register) Instruction {
5623 return encodeDJK(0x00120000, p0, p1, p2);
5624 }
5625
5626 /// Encodes a `slti` instruction (requires 32bit).
5627 pub inline fn slti(p0: Register, p1: Register, p2: i12) Instruction {
5628 return encodeDJSk12(0x02000000, p0, p1, p2);
5629 }
5630
5631 /// Encodes a `sltu` instruction (requires 32bit).
5632 pub inline fn sltu(p0: Register, p1: Register, p2: Register) Instruction {
5633 return encodeDJK(0x00128000, p0, p1, p2);
5634 }
5635
5636 /// Encodes a `sltui` instruction (requires 32bit).
5637 pub inline fn sltui(p0: Register, p1: Register, p2: i12) Instruction {
5638 return encodeDJSk12(0x02400000, p0, p1, p2);
5639 }
5640
5641 /// Encodes a `sra.d` instruction (requires 64bit).
5642 pub inline fn @"sra.d"(p0: Register, p1: Register, p2: Register) Instruction {
5643 return encodeDJK(0x00198000, p0, p1, p2);
5644 }
5645
5646 /// Encodes a `sra.w` instruction (requires 32bit).
5647 pub inline fn @"sra.w"(p0: Register, p1: Register, p2: Register) Instruction {
5648 return encodeDJK(0x00180000, p0, p1, p2);
5649 }
5650
5651 /// Encodes a `srai.d` instruction (requires 64bit).
5652 pub inline fn @"srai.d"(p0: Register, p1: Register, p2: u6) Instruction {
5653 return encodeDJUk6(0x00490000, p0, p1, p2);
5654 }
5655
5656 /// Encodes a `srai.w` instruction (requires 32bit).
5657 pub inline fn @"srai.w"(p0: Register, p1: Register, p2: u5) Instruction {
5658 return encodeDJUk5(0x00488000, p0, p1, p2);
5659 }
5660
5661 /// Encodes a `srl.d` instruction (requires 64bit).
5662 pub inline fn @"srl.d"(p0: Register, p1: Register, p2: Register) Instruction {
5663 return encodeDJK(0x00190000, p0, p1, p2);
5664 }
5665
5666 /// Encodes a `srl.w` instruction (requires 32bit).
5667 pub inline fn @"srl.w"(p0: Register, p1: Register, p2: Register) Instruction {
5668 return encodeDJK(0x00178000, p0, p1, p2);
5669 }
5670
5671 /// Encodes a `srli.d` instruction (requires 64bit).
5672 pub inline fn @"srli.d"(p0: Register, p1: Register, p2: u6) Instruction {
5673 return encodeDJUk6(0x00450000, p0, p1, p2);
5674 }
5675
5676 /// Encodes a `srli.w` instruction (requires 32bit).
5677 pub inline fn @"srli.w"(p0: Register, p1: Register, p2: u5) Instruction {
5678 return encodeDJUk5(0x00448000, p0, p1, p2);
5679 }
5680
5681 /// Encodes a `st.b` instruction (requires 32bit).
5682 pub inline fn @"st.b"(p0: Register, p1: Register, p2: i12) Instruction {
5683 return encodeDJSk12(0x29000000, p0, p1, p2);
5684 }
5685
5686 /// Encodes a `st.d` instruction (requires 64bit).
5687 pub inline fn @"st.d"(p0: Register, p1: Register, p2: i12) Instruction {
5688 return encodeDJSk12(0x29c00000, p0, p1, p2);
5689 }
5690
5691 /// Encodes a `st.h` instruction (requires 32bit).
5692 pub inline fn @"st.h"(p0: Register, p1: Register, p2: i12) Instruction {
5693 return encodeDJSk12(0x29400000, p0, p1, p2);
5694 }
5695
5696 /// Encodes a `st.w` instruction (requires 32bit).
5697 pub inline fn @"st.w"(p0: Register, p1: Register, p2: i12) Instruction {
5698 return encodeDJSk12(0x29800000, p0, p1, p2);
5699 }
5700
5701 /// Encodes a `stgt.b` instruction (requires 64bit).
5702 pub inline fn @"stgt.b"(p0: Register, p1: Register, p2: Register) Instruction {
5703 return encodeDJK(0x387c0000, p0, p1, p2);
5704 }
5705
5706 /// Encodes a `stgt.d` instruction (requires 64bit).
5707 pub inline fn @"stgt.d"(p0: Register, p1: Register, p2: Register) Instruction {
5708 return encodeDJK(0x387d8000, p0, p1, p2);
5709 }
5710
5711 /// Encodes a `stgt.h` instruction (requires 64bit).
5712 pub inline fn @"stgt.h"(p0: Register, p1: Register, p2: Register) Instruction {
5713 return encodeDJK(0x387c8000, p0, p1, p2);
5714 }
5715
5716 /// Encodes a `stgt.w` instruction (requires 64bit).
5717 pub inline fn @"stgt.w"(p0: Register, p1: Register, p2: Register) Instruction {
5718 return encodeDJK(0x387d0000, p0, p1, p2);
5719 }
5720
5721 /// Encodes a `stl.d` instruction (requires 64bit).
5722 pub inline fn @"stl.d"(p0: Register, p1: Register, p2: i12) Instruction {
5723 return encodeDJSk12(0x2f800000, p0, p1, p2);
5724 }
5725
5726 /// Encodes a `stl.w` instruction (requires 64bit).
5727 pub inline fn @"stl.w"(p0: Register, p1: Register, p2: i12) Instruction {
5728 return encodeDJSk12(0x2f000000, p0, p1, p2);
5729 }
5730
5731 /// Encodes a `stle.b` instruction (requires 64bit).
5732 pub inline fn @"stle.b"(p0: Register, p1: Register, p2: Register) Instruction {
5733 return encodeDJK(0x387e0000, p0, p1, p2);
5734 }
5735
5736 /// Encodes a `stle.d` instruction (requires 64bit).
5737 pub inline fn @"stle.d"(p0: Register, p1: Register, p2: Register) Instruction {
5738 return encodeDJK(0x387f8000, p0, p1, p2);
5739 }
5740
5741 /// Encodes a `stle.h` instruction (requires 64bit).
5742 pub inline fn @"stle.h"(p0: Register, p1: Register, p2: Register) Instruction {
5743 return encodeDJK(0x387e8000, p0, p1, p2);
5744 }
5745
5746 /// Encodes a `stle.w` instruction (requires 64bit).
5747 pub inline fn @"stle.w"(p0: Register, p1: Register, p2: Register) Instruction {
5748 return encodeDJK(0x387f0000, p0, p1, p2);
5749 }
5750
5751 /// Encodes a `stox4.d` instruction (requires 64bit).
5752 pub inline fn @"stox4.d"(p0: Register, p1: Register, p2: i14) Instruction {
5753 return encodeDJSk14(0x27000000, p0, p1, p2);
5754 }
5755
5756 /// Encodes a `stox4.w` instruction (requires 64bit).
5757 pub inline fn @"stox4.w"(p0: Register, p1: Register, p2: i14) Instruction {
5758 return encodeDJSk14(0x25000000, p0, p1, p2);
5759 }
5760
5761 /// Encodes a `str.d` instruction (requires 64bit).
5762 pub inline fn @"str.d"(p0: Register, p1: Register, p2: i12) Instruction {
5763 return encodeDJSk12(0x2fc00000, p0, p1, p2);
5764 }
5765
5766 /// Encodes a `str.w` instruction (requires 64bit).
5767 pub inline fn @"str.w"(p0: Register, p1: Register, p2: i12) Instruction {
5768 return encodeDJSk12(0x2f400000, p0, p1, p2);
5769 }
5770
5771 /// Encodes a `stx.b` instruction (requires 64bit).
5772 pub inline fn @"stx.b"(p0: Register, p1: Register, p2: Register) Instruction {
5773 return encodeDJK(0x38100000, p0, p1, p2);
5774 }
5775
5776 /// Encodes a `stx.d` instruction (requires 64bit).
5777 pub inline fn @"stx.d"(p0: Register, p1: Register, p2: Register) Instruction {
5778 return encodeDJK(0x381c0000, p0, p1, p2);
5779 }
5780
5781 /// Encodes a `stx.h` instruction (requires 64bit).
5782 pub inline fn @"stx.h"(p0: Register, p1: Register, p2: Register) Instruction {
5783 return encodeDJK(0x38140000, p0, p1, p2);
5784 }
5785
5786 /// Encodes a `stx.w` instruction (requires 64bit).
5787 pub inline fn @"stx.w"(p0: Register, p1: Register, p2: Register) Instruction {
5788 return encodeDJK(0x38180000, p0, p1, p2);
5789 }
5790
5791 /// Encodes a `sub.d` instruction (requires 64bit).
5792 pub inline fn @"sub.d"(p0: Register, p1: Register, p2: Register) Instruction {
5793 return encodeDJK(0x00118000, p0, p1, p2);
5794 }
5795
5796 /// Encodes a `sub.w` instruction (requires 32bit).
5797 pub inline fn @"sub.w"(p0: Register, p1: Register, p2: Register) Instruction {
5798 return encodeDJK(0x00110000, p0, p1, p2);
5799 }
5800
5801 /// Encodes a `syscall` instruction (requires 32bit).
5802 pub inline fn syscall(p0: u15) Instruction {
5803 return encodeUd15(0x002b0000, p0);
5804 }
5805
5806 /// Encodes a `tlbclr` instruction (requires 64bit).
5807 pub inline fn tlbclr() Instruction {
5808 return encodeEMPTY(0x06482000);
5809 }
5810
5811 /// Encodes a `tlbfill` instruction (requires 32bit).
5812 pub inline fn tlbfill() Instruction {
5813 return encodeEMPTY(0x06483400);
5814 }
5815
5816 /// Encodes a `tlbflush` instruction (requires 64bit).
5817 pub inline fn tlbflush() Instruction {
5818 return encodeEMPTY(0x06482400);
5819 }
5820
5821 /// Encodes a `tlbinv` instruction (requires 32bit).
5822 pub inline fn tlbinv(p0: Register, p1: Register, p2: u5) Instruction {
5823 return encodeJKUd5(0x06498000, p0, p1, p2);
5824 }
5825
5826 /// Encodes a `tlbrd` instruction (requires 32bit).
5827 pub inline fn tlbrd() Instruction {
5828 return encodeEMPTY(0x06482c00);
5829 }
5830
5831 /// Encodes a `tlbsrch` instruction (requires 32bit).
5832 pub inline fn tlbsrch() Instruction {
5833 return encodeEMPTY(0x06482800);
5834 }
5835
5836 /// Encodes a `tlbwr` instruction (requires 32bit).
5837 pub inline fn tlbwr() Instruction {
5838 return encodeEMPTY(0x06483000);
5839 }
5840
5841 /// Encodes a `vabsd.b` instruction (requires lsx).
5842 pub inline fn @"vabsd.b"(p0: Register, p1: Register, p2: Register) Instruction {
5843 return encodeVdVjVk(0x70600000, p0, p1, p2);
5844 }
5845
5846 /// Encodes a `vabsd.bu` instruction (requires lsx).
5847 pub inline fn @"vabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction {
5848 return encodeVdVjVk(0x70620000, p0, p1, p2);
5849 }
5850
5851 /// Encodes a `vabsd.d` instruction (requires lsx).
5852 pub inline fn @"vabsd.d"(p0: Register, p1: Register, p2: Register) Instruction {
5853 return encodeVdVjVk(0x70618000, p0, p1, p2);
5854 }
5855
5856 /// Encodes a `vabsd.du` instruction (requires lsx).
5857 pub inline fn @"vabsd.du"(p0: Register, p1: Register, p2: Register) Instruction {
5858 return encodeVdVjVk(0x70638000, p0, p1, p2);
5859 }
5860
5861 /// Encodes a `vabsd.h` instruction (requires lsx).
5862 pub inline fn @"vabsd.h"(p0: Register, p1: Register, p2: Register) Instruction {
5863 return encodeVdVjVk(0x70608000, p0, p1, p2);
5864 }
5865
5866 /// Encodes a `vabsd.hu` instruction (requires lsx).
5867 pub inline fn @"vabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction {
5868 return encodeVdVjVk(0x70628000, p0, p1, p2);
5869 }
5870
5871 /// Encodes a `vabsd.w` instruction (requires lsx).
5872 pub inline fn @"vabsd.w"(p0: Register, p1: Register, p2: Register) Instruction {
5873 return encodeVdVjVk(0x70610000, p0, p1, p2);
5874 }
5875
5876 /// Encodes a `vabsd.wu` instruction (requires lsx).
5877 pub inline fn @"vabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5878 return encodeVdVjVk(0x70630000, p0, p1, p2);
5879 }
5880
5881 /// Encodes a `vadd.b` instruction (requires lsx).
5882 pub inline fn @"vadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
5883 return encodeVdVjVk(0x700a0000, p0, p1, p2);
5884 }
5885
5886 /// Encodes a `vadd.d` instruction (requires lsx).
5887 pub inline fn @"vadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
5888 return encodeVdVjVk(0x700b8000, p0, p1, p2);
5889 }
5890
5891 /// Encodes a `vadd.h` instruction (requires lsx).
5892 pub inline fn @"vadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
5893 return encodeVdVjVk(0x700a8000, p0, p1, p2);
5894 }
5895
5896 /// Encodes a `vadd.q` instruction (requires lsx).
5897 pub inline fn @"vadd.q"(p0: Register, p1: Register, p2: Register) Instruction {
5898 return encodeVdVjVk(0x712d0000, p0, p1, p2);
5899 }
5900
5901 /// Encodes a `vadd.w` instruction (requires lsx).
5902 pub inline fn @"vadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
5903 return encodeVdVjVk(0x700b0000, p0, p1, p2);
5904 }
5905
5906 /// Encodes a `vadda.b` instruction (requires lsx).
5907 pub inline fn @"vadda.b"(p0: Register, p1: Register, p2: Register) Instruction {
5908 return encodeVdVjVk(0x705c0000, p0, p1, p2);
5909 }
5910
5911 /// Encodes a `vadda.d` instruction (requires lsx).
5912 pub inline fn @"vadda.d"(p0: Register, p1: Register, p2: Register) Instruction {
5913 return encodeVdVjVk(0x705d8000, p0, p1, p2);
5914 }
5915
5916 /// Encodes a `vadda.h` instruction (requires lsx).
5917 pub inline fn @"vadda.h"(p0: Register, p1: Register, p2: Register) Instruction {
5918 return encodeVdVjVk(0x705c8000, p0, p1, p2);
5919 }
5920
5921 /// Encodes a `vadda.w` instruction (requires lsx).
5922 pub inline fn @"vadda.w"(p0: Register, p1: Register, p2: Register) Instruction {
5923 return encodeVdVjVk(0x705d0000, p0, p1, p2);
5924 }
5925
5926 /// Encodes a `vaddi.bu` instruction (requires lsx).
5927 pub inline fn @"vaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
5928 return encodeVdVjUk5(0x728a0000, p0, p1, p2);
5929 }
5930
5931 /// Encodes a `vaddi.du` instruction (requires lsx).
5932 pub inline fn @"vaddi.du"(p0: Register, p1: Register, p2: u5) Instruction {
5933 return encodeVdVjUk5(0x728b8000, p0, p1, p2);
5934 }
5935
5936 /// Encodes a `vaddi.hu` instruction (requires lsx).
5937 pub inline fn @"vaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
5938 return encodeVdVjUk5(0x728a8000, p0, p1, p2);
5939 }
5940
5941 /// Encodes a `vaddi.wu` instruction (requires lsx).
5942 pub inline fn @"vaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
5943 return encodeVdVjUk5(0x728b0000, p0, p1, p2);
5944 }
5945
5946 /// Encodes a `vaddwev.d.w` instruction (requires lsx).
5947 pub inline fn @"vaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
5948 return encodeVdVjVk(0x701f0000, p0, p1, p2);
5949 }
5950
5951 /// Encodes a `vaddwev.d.wu` instruction (requires lsx).
5952 pub inline fn @"vaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
5953 return encodeVdVjVk(0x702f0000, p0, p1, p2);
5954 }
5955
5956 /// Encodes a `vaddwev.d.wu.w` instruction (requires lsx).
5957 pub inline fn @"vaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
5958 return encodeVdVjVk(0x703f0000, p0, p1, p2);
5959 }
5960
5961 /// Encodes a `vaddwev.h.b` instruction (requires lsx).
5962 pub inline fn @"vaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
5963 return encodeVdVjVk(0x701e0000, p0, p1, p2);
5964 }
5965
5966 /// Encodes a `vaddwev.h.bu` instruction (requires lsx).
5967 pub inline fn @"vaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
5968 return encodeVdVjVk(0x702e0000, p0, p1, p2);
5969 }
5970
5971 /// Encodes a `vaddwev.h.bu.b` instruction (requires lsx).
5972 pub inline fn @"vaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
5973 return encodeVdVjVk(0x703e0000, p0, p1, p2);
5974 }
5975
5976 /// Encodes a `vaddwev.q.d` instruction (requires lsx).
5977 pub inline fn @"vaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
5978 return encodeVdVjVk(0x701f8000, p0, p1, p2);
5979 }
5980
5981 /// Encodes a `vaddwev.q.du` instruction (requires lsx).
5982 pub inline fn @"vaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
5983 return encodeVdVjVk(0x702f8000, p0, p1, p2);
5984 }
5985
5986 /// Encodes a `vaddwev.q.du.d` instruction (requires lsx).
5987 pub inline fn @"vaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
5988 return encodeVdVjVk(0x703f8000, p0, p1, p2);
5989 }
5990
5991 /// Encodes a `vaddwev.w.h` instruction (requires lsx).
5992 pub inline fn @"vaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
5993 return encodeVdVjVk(0x701e8000, p0, p1, p2);
5994 }
5995
5996 /// Encodes a `vaddwev.w.hu` instruction (requires lsx).
5997 pub inline fn @"vaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
5998 return encodeVdVjVk(0x702e8000, p0, p1, p2);
5999 }
6000
6001 /// Encodes a `vaddwev.w.hu.h` instruction (requires lsx).
6002 pub inline fn @"vaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
6003 return encodeVdVjVk(0x703e8000, p0, p1, p2);
6004 }
6005
6006 /// Encodes a `vaddwod.d.w` instruction (requires lsx).
6007 pub inline fn @"vaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
6008 return encodeVdVjVk(0x70230000, p0, p1, p2);
6009 }
6010
6011 /// Encodes a `vaddwod.d.wu` instruction (requires lsx).
6012 pub inline fn @"vaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
6013 return encodeVdVjVk(0x70330000, p0, p1, p2);
6014 }
6015
6016 /// Encodes a `vaddwod.d.wu.w` instruction (requires lsx).
6017 pub inline fn @"vaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
6018 return encodeVdVjVk(0x70410000, p0, p1, p2);
6019 }
6020
6021 /// Encodes a `vaddwod.h.b` instruction (requires lsx).
6022 pub inline fn @"vaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
6023 return encodeVdVjVk(0x70220000, p0, p1, p2);
6024 }
6025
6026 /// Encodes a `vaddwod.h.bu` instruction (requires lsx).
6027 pub inline fn @"vaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
6028 return encodeVdVjVk(0x70320000, p0, p1, p2);
6029 }
6030
6031 /// Encodes a `vaddwod.h.bu.b` instruction (requires lsx).
6032 pub inline fn @"vaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
6033 return encodeVdVjVk(0x70400000, p0, p1, p2);
6034 }
6035
6036 /// Encodes a `vaddwod.q.d` instruction (requires lsx).
6037 pub inline fn @"vaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
6038 return encodeVdVjVk(0x70238000, p0, p1, p2);
6039 }
6040
6041 /// Encodes a `vaddwod.q.du` instruction (requires lsx).
6042 pub inline fn @"vaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
6043 return encodeVdVjVk(0x70338000, p0, p1, p2);
6044 }
6045
6046 /// Encodes a `vaddwod.q.du.d` instruction (requires lsx).
6047 pub inline fn @"vaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
6048 return encodeVdVjVk(0x70418000, p0, p1, p2);
6049 }
6050
6051 /// Encodes a `vaddwod.w.h` instruction (requires lsx).
6052 pub inline fn @"vaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
6053 return encodeVdVjVk(0x70228000, p0, p1, p2);
6054 }
6055
6056 /// Encodes a `vaddwod.w.hu` instruction (requires lsx).
6057 pub inline fn @"vaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
6058 return encodeVdVjVk(0x70328000, p0, p1, p2);
6059 }
6060
6061 /// Encodes a `vaddwod.w.hu.h` instruction (requires lsx).
6062 pub inline fn @"vaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
6063 return encodeVdVjVk(0x70408000, p0, p1, p2);
6064 }
6065
6066 /// Encodes a `vand.v` instruction (requires lsx).
6067 pub inline fn @"vand.v"(p0: Register, p1: Register, p2: Register) Instruction {
6068 return encodeVdVjVk(0x71260000, p0, p1, p2);
6069 }
6070
6071 /// Encodes a `vandi.b` instruction (requires lsx).
6072 pub inline fn @"vandi.b"(p0: Register, p1: Register, p2: u8) Instruction {
6073 return encodeVdVjUk8(0x73d00000, p0, p1, p2);
6074 }
6075
6076 /// Encodes a `vandn.v` instruction (requires lsx).
6077 pub inline fn @"vandn.v"(p0: Register, p1: Register, p2: Register) Instruction {
6078 return encodeVdVjVk(0x71280000, p0, p1, p2);
6079 }
6080
6081 /// Encodes a `vavg.b` instruction (requires lsx).
6082 pub inline fn @"vavg.b"(p0: Register, p1: Register, p2: Register) Instruction {
6083 return encodeVdVjVk(0x70640000, p0, p1, p2);
6084 }
6085
6086 /// Encodes a `vavg.bu` instruction (requires lsx).
6087 pub inline fn @"vavg.bu"(p0: Register, p1: Register, p2: Register) Instruction {
6088 return encodeVdVjVk(0x70660000, p0, p1, p2);
6089 }
6090
6091 /// Encodes a `vavg.d` instruction (requires lsx).
6092 pub inline fn @"vavg.d"(p0: Register, p1: Register, p2: Register) Instruction {
6093 return encodeVdVjVk(0x70658000, p0, p1, p2);
6094 }
6095
6096 /// Encodes a `vavg.du` instruction (requires lsx).
6097 pub inline fn @"vavg.du"(p0: Register, p1: Register, p2: Register) Instruction {
6098 return encodeVdVjVk(0x70678000, p0, p1, p2);
6099 }
6100
6101 /// Encodes a `vavg.h` instruction (requires lsx).
6102 pub inline fn @"vavg.h"(p0: Register, p1: Register, p2: Register) Instruction {
6103 return encodeVdVjVk(0x70648000, p0, p1, p2);
6104 }
6105
6106 /// Encodes a `vavg.hu` instruction (requires lsx).
6107 pub inline fn @"vavg.hu"(p0: Register, p1: Register, p2: Register) Instruction {
6108 return encodeVdVjVk(0x70668000, p0, p1, p2);
6109 }
6110
6111 /// Encodes a `vavg.w` instruction (requires lsx).
6112 pub inline fn @"vavg.w"(p0: Register, p1: Register, p2: Register) Instruction {
6113 return encodeVdVjVk(0x70650000, p0, p1, p2);
6114 }
6115
6116 /// Encodes a `vavg.wu` instruction (requires lsx).
6117 pub inline fn @"vavg.wu"(p0: Register, p1: Register, p2: Register) Instruction {
6118 return encodeVdVjVk(0x70670000, p0, p1, p2);
6119 }
6120
6121 /// Encodes a `vavgr.b` instruction (requires lsx).
6122 pub inline fn @"vavgr.b"(p0: Register, p1: Register, p2: Register) Instruction {
6123 return encodeVdVjVk(0x70680000, p0, p1, p2);
6124 }
6125
6126 /// Encodes a `vavgr.bu` instruction (requires lsx).
6127 pub inline fn @"vavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction {
6128 return encodeVdVjVk(0x706a0000, p0, p1, p2);
6129 }
6130
6131 /// Encodes a `vavgr.d` instruction (requires lsx).
6132 pub inline fn @"vavgr.d"(p0: Register, p1: Register, p2: Register) Instruction {
6133 return encodeVdVjVk(0x70698000, p0, p1, p2);
6134 }
6135
6136 /// Encodes a `vavgr.du` instruction (requires lsx).
6137 pub inline fn @"vavgr.du"(p0: Register, p1: Register, p2: Register) Instruction {
6138 return encodeVdVjVk(0x706b8000, p0, p1, p2);
6139 }
6140
6141 /// Encodes a `vavgr.h` instruction (requires lsx).
6142 pub inline fn @"vavgr.h"(p0: Register, p1: Register, p2: Register) Instruction {
6143 return encodeVdVjVk(0x70688000, p0, p1, p2);
6144 }
6145
6146 /// Encodes a `vavgr.hu` instruction (requires lsx).
6147 pub inline fn @"vavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction {
6148 return encodeVdVjVk(0x706a8000, p0, p1, p2);
6149 }
6150
6151 /// Encodes a `vavgr.w` instruction (requires lsx).
6152 pub inline fn @"vavgr.w"(p0: Register, p1: Register, p2: Register) Instruction {
6153 return encodeVdVjVk(0x70690000, p0, p1, p2);
6154 }
6155
6156 /// Encodes a `vavgr.wu` instruction (requires lsx).
6157 pub inline fn @"vavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction {
6158 return encodeVdVjVk(0x706b0000, p0, p1, p2);
6159 }
6160
6161 /// Encodes a `vbitclr.b` instruction (requires lsx).
6162 pub inline fn @"vbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction {
6163 return encodeVdVjVk(0x710c0000, p0, p1, p2);
6164 }
6165
6166 /// Encodes a `vbitclr.d` instruction (requires lsx).
6167 pub inline fn @"vbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction {
6168 return encodeVdVjVk(0x710d8000, p0, p1, p2);
6169 }
6170
6171 /// Encodes a `vbitclr.h` instruction (requires lsx).
6172 pub inline fn @"vbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction {
6173 return encodeVdVjVk(0x710c8000, p0, p1, p2);
6174 }
6175
6176 /// Encodes a `vbitclr.w` instruction (requires lsx).
6177 pub inline fn @"vbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction {
6178 return encodeVdVjVk(0x710d0000, p0, p1, p2);
6179 }
6180
6181 /// Encodes a `vbitclri.b` instruction (requires lsx).
6182 pub inline fn @"vbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction {
6183 return encodeVdVjUk3(0x73102000, p0, p1, p2);
6184 }
6185
6186 /// Encodes a `vbitclri.d` instruction (requires lsx).
6187 pub inline fn @"vbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction {
6188 return encodeVdVjUk6(0x73110000, p0, p1, p2);
6189 }
6190
6191 /// Encodes a `vbitclri.h` instruction (requires lsx).
6192 pub inline fn @"vbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction {
6193 return encodeVdVjUk4(0x73104000, p0, p1, p2);
6194 }
6195
6196 /// Encodes a `vbitclri.w` instruction (requires lsx).
6197 pub inline fn @"vbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction {
6198 return encodeVdVjUk5(0x73108000, p0, p1, p2);
6199 }
6200
6201 /// Encodes a `vbitrev.b` instruction (requires lsx).
6202 pub inline fn @"vbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction {
6203 return encodeVdVjVk(0x71100000, p0, p1, p2);
6204 }
6205
6206 /// Encodes a `vbitrev.d` instruction (requires lsx).
6207 pub inline fn @"vbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction {
6208 return encodeVdVjVk(0x71118000, p0, p1, p2);
6209 }
6210
6211 /// Encodes a `vbitrev.h` instruction (requires lsx).
6212 pub inline fn @"vbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction {
6213 return encodeVdVjVk(0x71108000, p0, p1, p2);
6214 }
6215
6216 /// Encodes a `vbitrev.w` instruction (requires lsx).
6217 pub inline fn @"vbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction {
6218 return encodeVdVjVk(0x71110000, p0, p1, p2);
6219 }
6220
6221 /// Encodes a `vbitrevi.b` instruction (requires lsx).
6222 pub inline fn @"vbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction {
6223 return encodeVdVjUk3(0x73182000, p0, p1, p2);
6224 }
6225
6226 /// Encodes a `vbitrevi.d` instruction (requires lsx).
6227 pub inline fn @"vbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction {
6228 return encodeVdVjUk6(0x73190000, p0, p1, p2);
6229 }
6230
6231 /// Encodes a `vbitrevi.h` instruction (requires lsx).
6232 pub inline fn @"vbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction {
6233 return encodeVdVjUk4(0x73184000, p0, p1, p2);
6234 }
6235
6236 /// Encodes a `vbitrevi.w` instruction (requires lsx).
6237 pub inline fn @"vbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction {
6238 return encodeVdVjUk5(0x73188000, p0, p1, p2);
6239 }
6240
6241 /// Encodes a `vbitsel.v` instruction (requires lsx).
6242 pub inline fn @"vbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6243 return encodeVdVjVkVa(0x0d100000, p0, p1, p2, p3);
6244 }
6245
6246 /// Encodes a `vbitseli.b` instruction (requires lsx).
6247 pub inline fn @"vbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction {
6248 return encodeVdVjUk8(0x73c40000, p0, p1, p2);
6249 }
6250
6251 /// Encodes a `vbitset.b` instruction (requires lsx).
6252 pub inline fn @"vbitset.b"(p0: Register, p1: Register, p2: Register) Instruction {
6253 return encodeVdVjVk(0x710e0000, p0, p1, p2);
6254 }
6255
6256 /// Encodes a `vbitset.d` instruction (requires lsx).
6257 pub inline fn @"vbitset.d"(p0: Register, p1: Register, p2: Register) Instruction {
6258 return encodeVdVjVk(0x710f8000, p0, p1, p2);
6259 }
6260
6261 /// Encodes a `vbitset.h` instruction (requires lsx).
6262 pub inline fn @"vbitset.h"(p0: Register, p1: Register, p2: Register) Instruction {
6263 return encodeVdVjVk(0x710e8000, p0, p1, p2);
6264 }
6265
6266 /// Encodes a `vbitset.w` instruction (requires lsx).
6267 pub inline fn @"vbitset.w"(p0: Register, p1: Register, p2: Register) Instruction {
6268 return encodeVdVjVk(0x710f0000, p0, p1, p2);
6269 }
6270
6271 /// Encodes a `vbitseti.b` instruction (requires lsx).
6272 pub inline fn @"vbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction {
6273 return encodeVdVjUk3(0x73142000, p0, p1, p2);
6274 }
6275
6276 /// Encodes a `vbitseti.d` instruction (requires lsx).
6277 pub inline fn @"vbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction {
6278 return encodeVdVjUk6(0x73150000, p0, p1, p2);
6279 }
6280
6281 /// Encodes a `vbitseti.h` instruction (requires lsx).
6282 pub inline fn @"vbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction {
6283 return encodeVdVjUk4(0x73144000, p0, p1, p2);
6284 }
6285
6286 /// Encodes a `vbitseti.w` instruction (requires lsx).
6287 pub inline fn @"vbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction {
6288 return encodeVdVjUk5(0x73148000, p0, p1, p2);
6289 }
6290
6291 /// Encodes a `vbsll.v` instruction (requires lsx).
6292 pub inline fn @"vbsll.v"(p0: Register, p1: Register, p2: u5) Instruction {
6293 return encodeVdVjUk5(0x728e0000, p0, p1, p2);
6294 }
6295
6296 /// Encodes a `vbsrl.v` instruction (requires lsx).
6297 pub inline fn @"vbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction {
6298 return encodeVdVjUk5(0x728e8000, p0, p1, p2);
6299 }
6300
6301 /// Encodes a `vclo.b` instruction (requires lsx).
6302 pub inline fn @"vclo.b"(p0: Register, p1: Register) Instruction {
6303 return encodeVdVj(0x729c0000, p0, p1);
6304 }
6305
6306 /// Encodes a `vclo.d` instruction (requires lsx).
6307 pub inline fn @"vclo.d"(p0: Register, p1: Register) Instruction {
6308 return encodeVdVj(0x729c0c00, p0, p1);
6309 }
6310
6311 /// Encodes a `vclo.h` instruction (requires lsx).
6312 pub inline fn @"vclo.h"(p0: Register, p1: Register) Instruction {
6313 return encodeVdVj(0x729c0400, p0, p1);
6314 }
6315
6316 /// Encodes a `vclo.w` instruction (requires lsx).
6317 pub inline fn @"vclo.w"(p0: Register, p1: Register) Instruction {
6318 return encodeVdVj(0x729c0800, p0, p1);
6319 }
6320
6321 /// Encodes a `vclz.b` instruction (requires lsx).
6322 pub inline fn @"vclz.b"(p0: Register, p1: Register) Instruction {
6323 return encodeVdVj(0x729c1000, p0, p1);
6324 }
6325
6326 /// Encodes a `vclz.d` instruction (requires lsx).
6327 pub inline fn @"vclz.d"(p0: Register, p1: Register) Instruction {
6328 return encodeVdVj(0x729c1c00, p0, p1);
6329 }
6330
6331 /// Encodes a `vclz.h` instruction (requires lsx).
6332 pub inline fn @"vclz.h"(p0: Register, p1: Register) Instruction {
6333 return encodeVdVj(0x729c1400, p0, p1);
6334 }
6335
6336 /// Encodes a `vclz.w` instruction (requires lsx).
6337 pub inline fn @"vclz.w"(p0: Register, p1: Register) Instruction {
6338 return encodeVdVj(0x729c1800, p0, p1);
6339 }
6340
6341 /// Encodes a `vdiv.b` instruction (requires lsx).
6342 pub inline fn @"vdiv.b"(p0: Register, p1: Register, p2: Register) Instruction {
6343 return encodeVdVjVk(0x70e00000, p0, p1, p2);
6344 }
6345
6346 /// Encodes a `vdiv.bu` instruction (requires lsx).
6347 pub inline fn @"vdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction {
6348 return encodeVdVjVk(0x70e40000, p0, p1, p2);
6349 }
6350
6351 /// Encodes a `vdiv.d` instruction (requires lsx).
6352 pub inline fn @"vdiv.d"(p0: Register, p1: Register, p2: Register) Instruction {
6353 return encodeVdVjVk(0x70e18000, p0, p1, p2);
6354 }
6355
6356 /// Encodes a `vdiv.du` instruction (requires lsx).
6357 pub inline fn @"vdiv.du"(p0: Register, p1: Register, p2: Register) Instruction {
6358 return encodeVdVjVk(0x70e58000, p0, p1, p2);
6359 }
6360
6361 /// Encodes a `vdiv.h` instruction (requires lsx).
6362 pub inline fn @"vdiv.h"(p0: Register, p1: Register, p2: Register) Instruction {
6363 return encodeVdVjVk(0x70e08000, p0, p1, p2);
6364 }
6365
6366 /// Encodes a `vdiv.hu` instruction (requires lsx).
6367 pub inline fn @"vdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction {
6368 return encodeVdVjVk(0x70e48000, p0, p1, p2);
6369 }
6370
6371 /// Encodes a `vdiv.w` instruction (requires lsx).
6372 pub inline fn @"vdiv.w"(p0: Register, p1: Register, p2: Register) Instruction {
6373 return encodeVdVjVk(0x70e10000, p0, p1, p2);
6374 }
6375
6376 /// Encodes a `vdiv.wu` instruction (requires lsx).
6377 pub inline fn @"vdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction {
6378 return encodeVdVjVk(0x70e50000, p0, p1, p2);
6379 }
6380
6381 /// Encodes a `vext2xv.d.b` instruction (requires lasx).
6382 pub inline fn @"vext2xv.d.b"(p0: Register, p1: Register) Instruction {
6383 return encodeXdXj(0x769f1800, p0, p1);
6384 }
6385
6386 /// Encodes a `vext2xv.d.h` instruction (requires lasx).
6387 pub inline fn @"vext2xv.d.h"(p0: Register, p1: Register) Instruction {
6388 return encodeXdXj(0x769f2000, p0, p1);
6389 }
6390
6391 /// Encodes a `vext2xv.d.w` instruction (requires lasx).
6392 pub inline fn @"vext2xv.d.w"(p0: Register, p1: Register) Instruction {
6393 return encodeXdXj(0x769f2400, p0, p1);
6394 }
6395
6396 /// Encodes a `vext2xv.du.bu` instruction (requires lasx).
6397 pub inline fn @"vext2xv.du.bu"(p0: Register, p1: Register) Instruction {
6398 return encodeXdXj(0x769f3000, p0, p1);
6399 }
6400
6401 /// Encodes a `vext2xv.du.hu` instruction (requires lasx).
6402 pub inline fn @"vext2xv.du.hu"(p0: Register, p1: Register) Instruction {
6403 return encodeXdXj(0x769f3800, p0, p1);
6404 }
6405
6406 /// Encodes a `vext2xv.du.wu` instruction (requires lasx).
6407 pub inline fn @"vext2xv.du.wu"(p0: Register, p1: Register) Instruction {
6408 return encodeXdXj(0x769f3c00, p0, p1);
6409 }
6410
6411 /// Encodes a `vext2xv.h.b` instruction (requires lasx).
6412 pub inline fn @"vext2xv.h.b"(p0: Register, p1: Register) Instruction {
6413 return encodeXdXj(0x769f1000, p0, p1);
6414 }
6415
6416 /// Encodes a `vext2xv.hu.bu` instruction (requires lasx).
6417 pub inline fn @"vext2xv.hu.bu"(p0: Register, p1: Register) Instruction {
6418 return encodeXdXj(0x769f2800, p0, p1);
6419 }
6420
6421 /// Encodes a `vext2xv.w.b` instruction (requires lasx).
6422 pub inline fn @"vext2xv.w.b"(p0: Register, p1: Register) Instruction {
6423 return encodeXdXj(0x769f1400, p0, p1);
6424 }
6425
6426 /// Encodes a `vext2xv.w.h` instruction (requires lasx).
6427 pub inline fn @"vext2xv.w.h"(p0: Register, p1: Register) Instruction {
6428 return encodeXdXj(0x769f1c00, p0, p1);
6429 }
6430
6431 /// Encodes a `vext2xv.wu.bu` instruction (requires lasx).
6432 pub inline fn @"vext2xv.wu.bu"(p0: Register, p1: Register) Instruction {
6433 return encodeXdXj(0x769f2c00, p0, p1);
6434 }
6435
6436 /// Encodes a `vext2xv.wu.hu` instruction (requires lasx).
6437 pub inline fn @"vext2xv.wu.hu"(p0: Register, p1: Register) Instruction {
6438 return encodeXdXj(0x769f3400, p0, p1);
6439 }
6440
6441 /// Encodes a `vexth.d.w` instruction (requires lsx).
6442 pub inline fn @"vexth.d.w"(p0: Register, p1: Register) Instruction {
6443 return encodeVdVj(0x729ee800, p0, p1);
6444 }
6445
6446 /// Encodes a `vexth.du.wu` instruction (requires lsx).
6447 pub inline fn @"vexth.du.wu"(p0: Register, p1: Register) Instruction {
6448 return encodeVdVj(0x729ef800, p0, p1);
6449 }
6450
6451 /// Encodes a `vexth.h.b` instruction (requires lsx).
6452 pub inline fn @"vexth.h.b"(p0: Register, p1: Register) Instruction {
6453 return encodeVdVj(0x729ee000, p0, p1);
6454 }
6455
6456 /// Encodes a `vexth.hu.bu` instruction (requires lsx).
6457 pub inline fn @"vexth.hu.bu"(p0: Register, p1: Register) Instruction {
6458 return encodeVdVj(0x729ef000, p0, p1);
6459 }
6460
6461 /// Encodes a `vexth.q.d` instruction (requires lsx).
6462 pub inline fn @"vexth.q.d"(p0: Register, p1: Register) Instruction {
6463 return encodeVdVj(0x729eec00, p0, p1);
6464 }
6465
6466 /// Encodes a `vexth.qu.du` instruction (requires lsx).
6467 pub inline fn @"vexth.qu.du"(p0: Register, p1: Register) Instruction {
6468 return encodeVdVj(0x729efc00, p0, p1);
6469 }
6470
6471 /// Encodes a `vexth.w.h` instruction (requires lsx).
6472 pub inline fn @"vexth.w.h"(p0: Register, p1: Register) Instruction {
6473 return encodeVdVj(0x729ee400, p0, p1);
6474 }
6475
6476 /// Encodes a `vexth.wu.hu` instruction (requires lsx).
6477 pub inline fn @"vexth.wu.hu"(p0: Register, p1: Register) Instruction {
6478 return encodeVdVj(0x729ef400, p0, p1);
6479 }
6480
6481 /// Encodes a `vextl.q.d` instruction (requires lsx).
6482 pub inline fn @"vextl.q.d"(p0: Register, p1: Register) Instruction {
6483 return encodeVdVj(0x73090000, p0, p1);
6484 }
6485
6486 /// Encodes a `vextl.qu.du` instruction (requires lsx).
6487 pub inline fn @"vextl.qu.du"(p0: Register, p1: Register) Instruction {
6488 return encodeVdVj(0x730d0000, p0, p1);
6489 }
6490
6491 /// Encodes a `vextrins.b` instruction (requires lsx).
6492 pub inline fn @"vextrins.b"(p0: Register, p1: Register, p2: u8) Instruction {
6493 return encodeVdVjUk8(0x738c0000, p0, p1, p2);
6494 }
6495
6496 /// Encodes a `vextrins.d` instruction (requires lsx).
6497 pub inline fn @"vextrins.d"(p0: Register, p1: Register, p2: u8) Instruction {
6498 return encodeVdVjUk8(0x73800000, p0, p1, p2);
6499 }
6500
6501 /// Encodes a `vextrins.h` instruction (requires lsx).
6502 pub inline fn @"vextrins.h"(p0: Register, p1: Register, p2: u8) Instruction {
6503 return encodeVdVjUk8(0x73880000, p0, p1, p2);
6504 }
6505
6506 /// Encodes a `vextrins.w` instruction (requires lsx).
6507 pub inline fn @"vextrins.w"(p0: Register, p1: Register, p2: u8) Instruction {
6508 return encodeVdVjUk8(0x73840000, p0, p1, p2);
6509 }
6510
6511 /// Encodes a `vfadd.d` instruction (requires lsx).
6512 pub inline fn @"vfadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
6513 return encodeVdVjVk(0x71310000, p0, p1, p2);
6514 }
6515
6516 /// Encodes a `vfadd.s` instruction (requires lsx).
6517 pub inline fn @"vfadd.s"(p0: Register, p1: Register, p2: Register) Instruction {
6518 return encodeVdVjVk(0x71308000, p0, p1, p2);
6519 }
6520
6521 /// Encodes a `vfclass.d` instruction (requires lsx).
6522 pub inline fn @"vfclass.d"(p0: Register, p1: Register) Instruction {
6523 return encodeVdVj(0x729cd800, p0, p1);
6524 }
6525
6526 /// Encodes a `vfclass.s` instruction (requires lsx).
6527 pub inline fn @"vfclass.s"(p0: Register, p1: Register) Instruction {
6528 return encodeVdVj(0x729cd400, p0, p1);
6529 }
6530
6531 /// Encodes a `vfcmp.caf.d` instruction (requires lsx).
6532 pub inline fn @"vfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction {
6533 return encodeVdVjVk(0x0c600000, p0, p1, p2);
6534 }
6535
6536 /// Encodes a `vfcmp.caf.s` instruction (requires lsx).
6537 pub inline fn @"vfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction {
6538 return encodeVdVjVk(0x0c500000, p0, p1, p2);
6539 }
6540
6541 /// Encodes a `vfcmp.ceq.d` instruction (requires lsx).
6542 pub inline fn @"vfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction {
6543 return encodeVdVjVk(0x0c620000, p0, p1, p2);
6544 }
6545
6546 /// Encodes a `vfcmp.ceq.s` instruction (requires lsx).
6547 pub inline fn @"vfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction {
6548 return encodeVdVjVk(0x0c520000, p0, p1, p2);
6549 }
6550
6551 /// Encodes a `vfcmp.cle.d` instruction (requires lsx).
6552 pub inline fn @"vfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction {
6553 return encodeVdVjVk(0x0c630000, p0, p1, p2);
6554 }
6555
6556 /// Encodes a `vfcmp.cle.s` instruction (requires lsx).
6557 pub inline fn @"vfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction {
6558 return encodeVdVjVk(0x0c530000, p0, p1, p2);
6559 }
6560
6561 /// Encodes a `vfcmp.clt.d` instruction (requires lsx).
6562 pub inline fn @"vfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction {
6563 return encodeVdVjVk(0x0c610000, p0, p1, p2);
6564 }
6565
6566 /// Encodes a `vfcmp.clt.s` instruction (requires lsx).
6567 pub inline fn @"vfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction {
6568 return encodeVdVjVk(0x0c510000, p0, p1, p2);
6569 }
6570
6571 /// Encodes a `vfcmp.cne.d` instruction (requires lsx).
6572 pub inline fn @"vfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction {
6573 return encodeVdVjVk(0x0c680000, p0, p1, p2);
6574 }
6575
6576 /// Encodes a `vfcmp.cne.s` instruction (requires lsx).
6577 pub inline fn @"vfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction {
6578 return encodeVdVjVk(0x0c580000, p0, p1, p2);
6579 }
6580
6581 /// Encodes a `vfcmp.cor.d` instruction (requires lsx).
6582 pub inline fn @"vfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction {
6583 return encodeVdVjVk(0x0c6a0000, p0, p1, p2);
6584 }
6585
6586 /// Encodes a `vfcmp.cor.s` instruction (requires lsx).
6587 pub inline fn @"vfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction {
6588 return encodeVdVjVk(0x0c5a0000, p0, p1, p2);
6589 }
6590
6591 /// Encodes a `vfcmp.cueq.d` instruction (requires lsx).
6592 pub inline fn @"vfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
6593 return encodeVdVjVk(0x0c660000, p0, p1, p2);
6594 }
6595
6596 /// Encodes a `vfcmp.cueq.s` instruction (requires lsx).
6597 pub inline fn @"vfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
6598 return encodeVdVjVk(0x0c560000, p0, p1, p2);
6599 }
6600
6601 /// Encodes a `vfcmp.cule.d` instruction (requires lsx).
6602 pub inline fn @"vfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction {
6603 return encodeVdVjVk(0x0c670000, p0, p1, p2);
6604 }
6605
6606 /// Encodes a `vfcmp.cule.s` instruction (requires lsx).
6607 pub inline fn @"vfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction {
6608 return encodeVdVjVk(0x0c570000, p0, p1, p2);
6609 }
6610
6611 /// Encodes a `vfcmp.cult.d` instruction (requires lsx).
6612 pub inline fn @"vfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction {
6613 return encodeVdVjVk(0x0c650000, p0, p1, p2);
6614 }
6615
6616 /// Encodes a `vfcmp.cult.s` instruction (requires lsx).
6617 pub inline fn @"vfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction {
6618 return encodeVdVjVk(0x0c550000, p0, p1, p2);
6619 }
6620
6621 /// Encodes a `vfcmp.cun.d` instruction (requires lsx).
6622 pub inline fn @"vfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction {
6623 return encodeVdVjVk(0x0c640000, p0, p1, p2);
6624 }
6625
6626 /// Encodes a `vfcmp.cun.s` instruction (requires lsx).
6627 pub inline fn @"vfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction {
6628 return encodeVdVjVk(0x0c540000, p0, p1, p2);
6629 }
6630
6631 /// Encodes a `vfcmp.cune.d` instruction (requires lsx).
6632 pub inline fn @"vfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction {
6633 return encodeVdVjVk(0x0c6c0000, p0, p1, p2);
6634 }
6635
6636 /// Encodes a `vfcmp.cune.s` instruction (requires lsx).
6637 pub inline fn @"vfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction {
6638 return encodeVdVjVk(0x0c5c0000, p0, p1, p2);
6639 }
6640
6641 /// Encodes a `vfcmp.saf.d` instruction (requires lsx).
6642 pub inline fn @"vfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction {
6643 return encodeVdVjVk(0x0c608000, p0, p1, p2);
6644 }
6645
6646 /// Encodes a `vfcmp.saf.s` instruction (requires lsx).
6647 pub inline fn @"vfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction {
6648 return encodeVdVjVk(0x0c508000, p0, p1, p2);
6649 }
6650
6651 /// Encodes a `vfcmp.seq.d` instruction (requires lsx).
6652 pub inline fn @"vfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction {
6653 return encodeVdVjVk(0x0c628000, p0, p1, p2);
6654 }
6655
6656 /// Encodes a `vfcmp.seq.s` instruction (requires lsx).
6657 pub inline fn @"vfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction {
6658 return encodeVdVjVk(0x0c528000, p0, p1, p2);
6659 }
6660
6661 /// Encodes a `vfcmp.sle.d` instruction (requires lsx).
6662 pub inline fn @"vfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction {
6663 return encodeVdVjVk(0x0c638000, p0, p1, p2);
6664 }
6665
6666 /// Encodes a `vfcmp.sle.s` instruction (requires lsx).
6667 pub inline fn @"vfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction {
6668 return encodeVdVjVk(0x0c538000, p0, p1, p2);
6669 }
6670
6671 /// Encodes a `vfcmp.slt.d` instruction (requires lsx).
6672 pub inline fn @"vfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction {
6673 return encodeVdVjVk(0x0c618000, p0, p1, p2);
6674 }
6675
6676 /// Encodes a `vfcmp.slt.s` instruction (requires lsx).
6677 pub inline fn @"vfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction {
6678 return encodeVdVjVk(0x0c518000, p0, p1, p2);
6679 }
6680
6681 /// Encodes a `vfcmp.sne.d` instruction (requires lsx).
6682 pub inline fn @"vfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction {
6683 return encodeVdVjVk(0x0c688000, p0, p1, p2);
6684 }
6685
6686 /// Encodes a `vfcmp.sne.s` instruction (requires lsx).
6687 pub inline fn @"vfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction {
6688 return encodeVdVjVk(0x0c588000, p0, p1, p2);
6689 }
6690
6691 /// Encodes a `vfcmp.sor.d` instruction (requires lsx).
6692 pub inline fn @"vfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction {
6693 return encodeVdVjVk(0x0c6a8000, p0, p1, p2);
6694 }
6695
6696 /// Encodes a `vfcmp.sor.s` instruction (requires lsx).
6697 pub inline fn @"vfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction {
6698 return encodeVdVjVk(0x0c5a8000, p0, p1, p2);
6699 }
6700
6701 /// Encodes a `vfcmp.sueq.d` instruction (requires lsx).
6702 pub inline fn @"vfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
6703 return encodeVdVjVk(0x0c668000, p0, p1, p2);
6704 }
6705
6706 /// Encodes a `vfcmp.sueq.s` instruction (requires lsx).
6707 pub inline fn @"vfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
6708 return encodeVdVjVk(0x0c568000, p0, p1, p2);
6709 }
6710
6711 /// Encodes a `vfcmp.sule.d` instruction (requires lsx).
6712 pub inline fn @"vfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction {
6713 return encodeVdVjVk(0x0c678000, p0, p1, p2);
6714 }
6715
6716 /// Encodes a `vfcmp.sule.s` instruction (requires lsx).
6717 pub inline fn @"vfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction {
6718 return encodeVdVjVk(0x0c578000, p0, p1, p2);
6719 }
6720
6721 /// Encodes a `vfcmp.sult.d` instruction (requires lsx).
6722 pub inline fn @"vfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction {
6723 return encodeVdVjVk(0x0c658000, p0, p1, p2);
6724 }
6725
6726 /// Encodes a `vfcmp.sult.s` instruction (requires lsx).
6727 pub inline fn @"vfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction {
6728 return encodeVdVjVk(0x0c558000, p0, p1, p2);
6729 }
6730
6731 /// Encodes a `vfcmp.sun.d` instruction (requires lsx).
6732 pub inline fn @"vfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction {
6733 return encodeVdVjVk(0x0c648000, p0, p1, p2);
6734 }
6735
6736 /// Encodes a `vfcmp.sun.s` instruction (requires lsx).
6737 pub inline fn @"vfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction {
6738 return encodeVdVjVk(0x0c548000, p0, p1, p2);
6739 }
6740
6741 /// Encodes a `vfcmp.sune.d` instruction (requires lsx).
6742 pub inline fn @"vfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction {
6743 return encodeVdVjVk(0x0c6c8000, p0, p1, p2);
6744 }
6745
6746 /// Encodes a `vfcmp.sune.s` instruction (requires lsx).
6747 pub inline fn @"vfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction {
6748 return encodeVdVjVk(0x0c5c8000, p0, p1, p2);
6749 }
6750
6751 /// Encodes a `vfcvt.h.s` instruction (requires lsx).
6752 pub inline fn @"vfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction {
6753 return encodeVdVjVk(0x71460000, p0, p1, p2);
6754 }
6755
6756 /// Encodes a `vfcvt.s.d` instruction (requires lsx).
6757 pub inline fn @"vfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction {
6758 return encodeVdVjVk(0x71468000, p0, p1, p2);
6759 }
6760
6761 /// Encodes a `vfcvth.d.s` instruction (requires lsx).
6762 pub inline fn @"vfcvth.d.s"(p0: Register, p1: Register) Instruction {
6763 return encodeVdVj(0x729df400, p0, p1);
6764 }
6765
6766 /// Encodes a `vfcvth.s.h` instruction (requires lsx).
6767 pub inline fn @"vfcvth.s.h"(p0: Register, p1: Register) Instruction {
6768 return encodeVdVj(0x729dec00, p0, p1);
6769 }
6770
6771 /// Encodes a `vfcvtl.d.s` instruction (requires lsx).
6772 pub inline fn @"vfcvtl.d.s"(p0: Register, p1: Register) Instruction {
6773 return encodeVdVj(0x729df000, p0, p1);
6774 }
6775
6776 /// Encodes a `vfcvtl.s.h` instruction (requires lsx).
6777 pub inline fn @"vfcvtl.s.h"(p0: Register, p1: Register) Instruction {
6778 return encodeVdVj(0x729de800, p0, p1);
6779 }
6780
6781 /// Encodes a `vfdiv.d` instruction (requires lsx).
6782 pub inline fn @"vfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction {
6783 return encodeVdVjVk(0x713b0000, p0, p1, p2);
6784 }
6785
6786 /// Encodes a `vfdiv.s` instruction (requires lsx).
6787 pub inline fn @"vfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction {
6788 return encodeVdVjVk(0x713a8000, p0, p1, p2);
6789 }
6790
6791 /// Encodes a `vffint.d.l` instruction (requires lsx).
6792 pub inline fn @"vffint.d.l"(p0: Register, p1: Register) Instruction {
6793 return encodeVdVj(0x729e0800, p0, p1);
6794 }
6795
6796 /// Encodes a `vffint.d.lu` instruction (requires lsx).
6797 pub inline fn @"vffint.d.lu"(p0: Register, p1: Register) Instruction {
6798 return encodeVdVj(0x729e0c00, p0, p1);
6799 }
6800
6801 /// Encodes a `vffint.s.l` instruction (requires lsx).
6802 pub inline fn @"vffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction {
6803 return encodeVdVjVk(0x71480000, p0, p1, p2);
6804 }
6805
6806 /// Encodes a `vffint.s.w` instruction (requires lsx).
6807 pub inline fn @"vffint.s.w"(p0: Register, p1: Register) Instruction {
6808 return encodeVdVj(0x729e0000, p0, p1);
6809 }
6810
6811 /// Encodes a `vffint.s.wu` instruction (requires lsx).
6812 pub inline fn @"vffint.s.wu"(p0: Register, p1: Register) Instruction {
6813 return encodeVdVj(0x729e0400, p0, p1);
6814 }
6815
6816 /// Encodes a `vffinth.d.w` instruction (requires lsx).
6817 pub inline fn @"vffinth.d.w"(p0: Register, p1: Register) Instruction {
6818 return encodeVdVj(0x729e1400, p0, p1);
6819 }
6820
6821 /// Encodes a `vffintl.d.w` instruction (requires lsx).
6822 pub inline fn @"vffintl.d.w"(p0: Register, p1: Register) Instruction {
6823 return encodeVdVj(0x729e1000, p0, p1);
6824 }
6825
6826 /// Encodes a `vflogb.d` instruction (requires lsx).
6827 pub inline fn @"vflogb.d"(p0: Register, p1: Register) Instruction {
6828 return encodeVdVj(0x729cc800, p0, p1);
6829 }
6830
6831 /// Encodes a `vflogb.s` instruction (requires lsx).
6832 pub inline fn @"vflogb.s"(p0: Register, p1: Register) Instruction {
6833 return encodeVdVj(0x729cc400, p0, p1);
6834 }
6835
6836 /// Encodes a `vfmadd.d` instruction (requires lsx).
6837 pub inline fn @"vfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6838 return encodeVdVjVkVa(0x09200000, p0, p1, p2, p3);
6839 }
6840
6841 /// Encodes a `vfmadd.s` instruction (requires lsx).
6842 pub inline fn @"vfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6843 return encodeVdVjVkVa(0x09100000, p0, p1, p2, p3);
6844 }
6845
6846 /// Encodes a `vfmax.d` instruction (requires lsx).
6847 pub inline fn @"vfmax.d"(p0: Register, p1: Register, p2: Register) Instruction {
6848 return encodeVdVjVk(0x713d0000, p0, p1, p2);
6849 }
6850
6851 /// Encodes a `vfmax.s` instruction (requires lsx).
6852 pub inline fn @"vfmax.s"(p0: Register, p1: Register, p2: Register) Instruction {
6853 return encodeVdVjVk(0x713c8000, p0, p1, p2);
6854 }
6855
6856 /// Encodes a `vfmaxa.d` instruction (requires lsx).
6857 pub inline fn @"vfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction {
6858 return encodeVdVjVk(0x71410000, p0, p1, p2);
6859 }
6860
6861 /// Encodes a `vfmaxa.s` instruction (requires lsx).
6862 pub inline fn @"vfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction {
6863 return encodeVdVjVk(0x71408000, p0, p1, p2);
6864 }
6865
6866 /// Encodes a `vfmin.d` instruction (requires lsx).
6867 pub inline fn @"vfmin.d"(p0: Register, p1: Register, p2: Register) Instruction {
6868 return encodeVdVjVk(0x713f0000, p0, p1, p2);
6869 }
6870
6871 /// Encodes a `vfmin.s` instruction (requires lsx).
6872 pub inline fn @"vfmin.s"(p0: Register, p1: Register, p2: Register) Instruction {
6873 return encodeVdVjVk(0x713e8000, p0, p1, p2);
6874 }
6875
6876 /// Encodes a `vfmina.d` instruction (requires lsx).
6877 pub inline fn @"vfmina.d"(p0: Register, p1: Register, p2: Register) Instruction {
6878 return encodeVdVjVk(0x71430000, p0, p1, p2);
6879 }
6880
6881 /// Encodes a `vfmina.s` instruction (requires lsx).
6882 pub inline fn @"vfmina.s"(p0: Register, p1: Register, p2: Register) Instruction {
6883 return encodeVdVjVk(0x71428000, p0, p1, p2);
6884 }
6885
6886 /// Encodes a `vfmsub.d` instruction (requires lsx).
6887 pub inline fn @"vfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6888 return encodeVdVjVkVa(0x09600000, p0, p1, p2, p3);
6889 }
6890
6891 /// Encodes a `vfmsub.s` instruction (requires lsx).
6892 pub inline fn @"vfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6893 return encodeVdVjVkVa(0x09500000, p0, p1, p2, p3);
6894 }
6895
6896 /// Encodes a `vfmul.d` instruction (requires lsx).
6897 pub inline fn @"vfmul.d"(p0: Register, p1: Register, p2: Register) Instruction {
6898 return encodeVdVjVk(0x71390000, p0, p1, p2);
6899 }
6900
6901 /// Encodes a `vfmul.s` instruction (requires lsx).
6902 pub inline fn @"vfmul.s"(p0: Register, p1: Register, p2: Register) Instruction {
6903 return encodeVdVjVk(0x71388000, p0, p1, p2);
6904 }
6905
6906 /// Encodes a `vfnmadd.d` instruction (requires lsx).
6907 pub inline fn @"vfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6908 return encodeVdVjVkVa(0x09a00000, p0, p1, p2, p3);
6909 }
6910
6911 /// Encodes a `vfnmadd.s` instruction (requires lsx).
6912 pub inline fn @"vfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6913 return encodeVdVjVkVa(0x09900000, p0, p1, p2, p3);
6914 }
6915
6916 /// Encodes a `vfnmsub.d` instruction (requires lsx).
6917 pub inline fn @"vfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6918 return encodeVdVjVkVa(0x09e00000, p0, p1, p2, p3);
6919 }
6920
6921 /// Encodes a `vfnmsub.s` instruction (requires lsx).
6922 pub inline fn @"vfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
6923 return encodeVdVjVkVa(0x09d00000, p0, p1, p2, p3);
6924 }
6925
6926 /// Encodes a `vfrecip.d` instruction (requires lsx).
6927 pub inline fn @"vfrecip.d"(p0: Register, p1: Register) Instruction {
6928 return encodeVdVj(0x729cf800, p0, p1);
6929 }
6930
6931 /// Encodes a `vfrecip.s` instruction (requires lsx).
6932 pub inline fn @"vfrecip.s"(p0: Register, p1: Register) Instruction {
6933 return encodeVdVj(0x729cf400, p0, p1);
6934 }
6935
6936 /// Encodes a `vfrecipe.d` instruction (requires lsx).
6937 pub inline fn @"vfrecipe.d"(p0: Register, p1: Register) Instruction {
6938 return encodeVdVj(0x729d1800, p0, p1);
6939 }
6940
6941 /// Encodes a `vfrecipe.s` instruction (requires lsx).
6942 pub inline fn @"vfrecipe.s"(p0: Register, p1: Register) Instruction {
6943 return encodeVdVj(0x729d1400, p0, p1);
6944 }
6945
6946 /// Encodes a `vfrint.d` instruction (requires lsx).
6947 pub inline fn @"vfrint.d"(p0: Register, p1: Register) Instruction {
6948 return encodeVdVj(0x729d3800, p0, p1);
6949 }
6950
6951 /// Encodes a `vfrint.s` instruction (requires lsx).
6952 pub inline fn @"vfrint.s"(p0: Register, p1: Register) Instruction {
6953 return encodeVdVj(0x729d3400, p0, p1);
6954 }
6955
6956 /// Encodes a `vfrintrm.d` instruction (requires lsx).
6957 pub inline fn @"vfrintrm.d"(p0: Register, p1: Register) Instruction {
6958 return encodeVdVj(0x729d4800, p0, p1);
6959 }
6960
6961 /// Encodes a `vfrintrm.s` instruction (requires lsx).
6962 pub inline fn @"vfrintrm.s"(p0: Register, p1: Register) Instruction {
6963 return encodeVdVj(0x729d4400, p0, p1);
6964 }
6965
6966 /// Encodes a `vfrintrne.d` instruction (requires lsx).
6967 pub inline fn @"vfrintrne.d"(p0: Register, p1: Register) Instruction {
6968 return encodeVdVj(0x729d7800, p0, p1);
6969 }
6970
6971 /// Encodes a `vfrintrne.s` instruction (requires lsx).
6972 pub inline fn @"vfrintrne.s"(p0: Register, p1: Register) Instruction {
6973 return encodeVdVj(0x729d7400, p0, p1);
6974 }
6975
6976 /// Encodes a `vfrintrp.d` instruction (requires lsx).
6977 pub inline fn @"vfrintrp.d"(p0: Register, p1: Register) Instruction {
6978 return encodeVdVj(0x729d5800, p0, p1);
6979 }
6980
6981 /// Encodes a `vfrintrp.s` instruction (requires lsx).
6982 pub inline fn @"vfrintrp.s"(p0: Register, p1: Register) Instruction {
6983 return encodeVdVj(0x729d5400, p0, p1);
6984 }
6985
6986 /// Encodes a `vfrintrz.d` instruction (requires lsx).
6987 pub inline fn @"vfrintrz.d"(p0: Register, p1: Register) Instruction {
6988 return encodeVdVj(0x729d6800, p0, p1);
6989 }
6990
6991 /// Encodes a `vfrintrz.s` instruction (requires lsx).
6992 pub inline fn @"vfrintrz.s"(p0: Register, p1: Register) Instruction {
6993 return encodeVdVj(0x729d6400, p0, p1);
6994 }
6995
6996 /// Encodes a `vfrsqrt.d` instruction (requires lsx).
6997 pub inline fn @"vfrsqrt.d"(p0: Register, p1: Register) Instruction {
6998 return encodeVdVj(0x729d0800, p0, p1);
6999 }
7000
7001 /// Encodes a `vfrsqrt.s` instruction (requires lsx).
7002 pub inline fn @"vfrsqrt.s"(p0: Register, p1: Register) Instruction {
7003 return encodeVdVj(0x729d0400, p0, p1);
7004 }
7005
7006 /// Encodes a `vfrsqrte.d` instruction (requires lsx).
7007 pub inline fn @"vfrsqrte.d"(p0: Register, p1: Register) Instruction {
7008 return encodeVdVj(0x729d2800, p0, p1);
7009 }
7010
7011 /// Encodes a `vfrsqrte.s` instruction (requires lsx).
7012 pub inline fn @"vfrsqrte.s"(p0: Register, p1: Register) Instruction {
7013 return encodeVdVj(0x729d2400, p0, p1);
7014 }
7015
7016 /// Encodes a `vfrstp.b` instruction (requires lsx).
7017 pub inline fn @"vfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction {
7018 return encodeVdVjVk(0x712b0000, p0, p1, p2);
7019 }
7020
7021 /// Encodes a `vfrstp.h` instruction (requires lsx).
7022 pub inline fn @"vfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction {
7023 return encodeVdVjVk(0x712b8000, p0, p1, p2);
7024 }
7025
7026 /// Encodes a `vfrstpi.b` instruction (requires lsx).
7027 pub inline fn @"vfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction {
7028 return encodeVdVjUk5(0x729a0000, p0, p1, p2);
7029 }
7030
7031 /// Encodes a `vfrstpi.h` instruction (requires lsx).
7032 pub inline fn @"vfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction {
7033 return encodeVdVjUk5(0x729a8000, p0, p1, p2);
7034 }
7035
7036 /// Encodes a `vfsqrt.d` instruction (requires lsx).
7037 pub inline fn @"vfsqrt.d"(p0: Register, p1: Register) Instruction {
7038 return encodeVdVj(0x729ce800, p0, p1);
7039 }
7040
7041 /// Encodes a `vfsqrt.s` instruction (requires lsx).
7042 pub inline fn @"vfsqrt.s"(p0: Register, p1: Register) Instruction {
7043 return encodeVdVj(0x729ce400, p0, p1);
7044 }
7045
7046 /// Encodes a `vfsub.d` instruction (requires lsx).
7047 pub inline fn @"vfsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
7048 return encodeVdVjVk(0x71330000, p0, p1, p2);
7049 }
7050
7051 /// Encodes a `vfsub.s` instruction (requires lsx).
7052 pub inline fn @"vfsub.s"(p0: Register, p1: Register, p2: Register) Instruction {
7053 return encodeVdVjVk(0x71328000, p0, p1, p2);
7054 }
7055
7056 /// Encodes a `vftint.l.d` instruction (requires lsx).
7057 pub inline fn @"vftint.l.d"(p0: Register, p1: Register) Instruction {
7058 return encodeVdVj(0x729e3400, p0, p1);
7059 }
7060
7061 /// Encodes a `vftint.lu.d` instruction (requires lsx).
7062 pub inline fn @"vftint.lu.d"(p0: Register, p1: Register) Instruction {
7063 return encodeVdVj(0x729e5c00, p0, p1);
7064 }
7065
7066 /// Encodes a `vftint.w.d` instruction (requires lsx).
7067 pub inline fn @"vftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
7068 return encodeVdVjVk(0x71498000, p0, p1, p2);
7069 }
7070
7071 /// Encodes a `vftint.w.s` instruction (requires lsx).
7072 pub inline fn @"vftint.w.s"(p0: Register, p1: Register) Instruction {
7073 return encodeVdVj(0x729e3000, p0, p1);
7074 }
7075
7076 /// Encodes a `vftint.wu.s` instruction (requires lsx).
7077 pub inline fn @"vftint.wu.s"(p0: Register, p1: Register) Instruction {
7078 return encodeVdVj(0x729e5800, p0, p1);
7079 }
7080
7081 /// Encodes a `vftinth.l.s` instruction (requires lsx).
7082 pub inline fn @"vftinth.l.s"(p0: Register, p1: Register) Instruction {
7083 return encodeVdVj(0x729e8400, p0, p1);
7084 }
7085
7086 /// Encodes a `vftintl.l.s` instruction (requires lsx).
7087 pub inline fn @"vftintl.l.s"(p0: Register, p1: Register) Instruction {
7088 return encodeVdVj(0x729e8000, p0, p1);
7089 }
7090
7091 /// Encodes a `vftintrm.l.d` instruction (requires lsx).
7092 pub inline fn @"vftintrm.l.d"(p0: Register, p1: Register) Instruction {
7093 return encodeVdVj(0x729e3c00, p0, p1);
7094 }
7095
7096 /// Encodes a `vftintrm.w.d` instruction (requires lsx).
7097 pub inline fn @"vftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
7098 return encodeVdVjVk(0x714a0000, p0, p1, p2);
7099 }
7100
7101 /// Encodes a `vftintrm.w.s` instruction (requires lsx).
7102 pub inline fn @"vftintrm.w.s"(p0: Register, p1: Register) Instruction {
7103 return encodeVdVj(0x729e3800, p0, p1);
7104 }
7105
7106 /// Encodes a `vftintrmh.l.s` instruction (requires lsx).
7107 pub inline fn @"vftintrmh.l.s"(p0: Register, p1: Register) Instruction {
7108 return encodeVdVj(0x729e8c00, p0, p1);
7109 }
7110
7111 /// Encodes a `vftintrml.l.s` instruction (requires lsx).
7112 pub inline fn @"vftintrml.l.s"(p0: Register, p1: Register) Instruction {
7113 return encodeVdVj(0x729e8800, p0, p1);
7114 }
7115
7116 /// Encodes a `vftintrne.l.d` instruction (requires lsx).
7117 pub inline fn @"vftintrne.l.d"(p0: Register, p1: Register) Instruction {
7118 return encodeVdVj(0x729e5400, p0, p1);
7119 }
7120
7121 /// Encodes a `vftintrne.w.d` instruction (requires lsx).
7122 pub inline fn @"vftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
7123 return encodeVdVjVk(0x714b8000, p0, p1, p2);
7124 }
7125
7126 /// Encodes a `vftintrne.w.s` instruction (requires lsx).
7127 pub inline fn @"vftintrne.w.s"(p0: Register, p1: Register) Instruction {
7128 return encodeVdVj(0x729e5000, p0, p1);
7129 }
7130
7131 /// Encodes a `vftintrneh.l.s` instruction (requires lsx).
7132 pub inline fn @"vftintrneh.l.s"(p0: Register, p1: Register) Instruction {
7133 return encodeVdVj(0x729ea400, p0, p1);
7134 }
7135
7136 /// Encodes a `vftintrnel.l.s` instruction (requires lsx).
7137 pub inline fn @"vftintrnel.l.s"(p0: Register, p1: Register) Instruction {
7138 return encodeVdVj(0x729ea000, p0, p1);
7139 }
7140
7141 /// Encodes a `vftintrp.l.d` instruction (requires lsx).
7142 pub inline fn @"vftintrp.l.d"(p0: Register, p1: Register) Instruction {
7143 return encodeVdVj(0x729e4400, p0, p1);
7144 }
7145
7146 /// Encodes a `vftintrp.w.d` instruction (requires lsx).
7147 pub inline fn @"vftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
7148 return encodeVdVjVk(0x714a8000, p0, p1, p2);
7149 }
7150
7151 /// Encodes a `vftintrp.w.s` instruction (requires lsx).
7152 pub inline fn @"vftintrp.w.s"(p0: Register, p1: Register) Instruction {
7153 return encodeVdVj(0x729e4000, p0, p1);
7154 }
7155
7156 /// Encodes a `vftintrph.l.s` instruction (requires lsx).
7157 pub inline fn @"vftintrph.l.s"(p0: Register, p1: Register) Instruction {
7158 return encodeVdVj(0x729e9400, p0, p1);
7159 }
7160
7161 /// Encodes a `vftintrpl.l.s` instruction (requires lsx).
7162 pub inline fn @"vftintrpl.l.s"(p0: Register, p1: Register) Instruction {
7163 return encodeVdVj(0x729e9000, p0, p1);
7164 }
7165
7166 /// Encodes a `vftintrz.l.d` instruction (requires lsx).
7167 pub inline fn @"vftintrz.l.d"(p0: Register, p1: Register) Instruction {
7168 return encodeVdVj(0x729e4c00, p0, p1);
7169 }
7170
7171 /// Encodes a `vftintrz.lu.d` instruction (requires lsx).
7172 pub inline fn @"vftintrz.lu.d"(p0: Register, p1: Register) Instruction {
7173 return encodeVdVj(0x729e7400, p0, p1);
7174 }
7175
7176 /// Encodes a `vftintrz.w.d` instruction (requires lsx).
7177 pub inline fn @"vftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
7178 return encodeVdVjVk(0x714b0000, p0, p1, p2);
7179 }
7180
7181 /// Encodes a `vftintrz.w.s` instruction (requires lsx).
7182 pub inline fn @"vftintrz.w.s"(p0: Register, p1: Register) Instruction {
7183 return encodeVdVj(0x729e4800, p0, p1);
7184 }
7185
7186 /// Encodes a `vftintrz.wu.s` instruction (requires lsx).
7187 pub inline fn @"vftintrz.wu.s"(p0: Register, p1: Register) Instruction {
7188 return encodeVdVj(0x729e7000, p0, p1);
7189 }
7190
7191 /// Encodes a `vftintrzh.l.s` instruction (requires lsx).
7192 pub inline fn @"vftintrzh.l.s"(p0: Register, p1: Register) Instruction {
7193 return encodeVdVj(0x729e9c00, p0, p1);
7194 }
7195
7196 /// Encodes a `vftintrzl.l.s` instruction (requires lsx).
7197 pub inline fn @"vftintrzl.l.s"(p0: Register, p1: Register) Instruction {
7198 return encodeVdVj(0x729e9800, p0, p1);
7199 }
7200
7201 /// Encodes a `vhaddw.d.w` instruction (requires lsx).
7202 pub inline fn @"vhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7203 return encodeVdVjVk(0x70550000, p0, p1, p2);
7204 }
7205
7206 /// Encodes a `vhaddw.du.wu` instruction (requires lsx).
7207 pub inline fn @"vhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7208 return encodeVdVjVk(0x70590000, p0, p1, p2);
7209 }
7210
7211 /// Encodes a `vhaddw.h.b` instruction (requires lsx).
7212 pub inline fn @"vhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7213 return encodeVdVjVk(0x70540000, p0, p1, p2);
7214 }
7215
7216 /// Encodes a `vhaddw.hu.bu` instruction (requires lsx).
7217 pub inline fn @"vhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7218 return encodeVdVjVk(0x70580000, p0, p1, p2);
7219 }
7220
7221 /// Encodes a `vhaddw.q.d` instruction (requires lsx).
7222 pub inline fn @"vhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7223 return encodeVdVjVk(0x70558000, p0, p1, p2);
7224 }
7225
7226 /// Encodes a `vhaddw.qu.du` instruction (requires lsx).
7227 pub inline fn @"vhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction {
7228 return encodeVdVjVk(0x70598000, p0, p1, p2);
7229 }
7230
7231 /// Encodes a `vhaddw.w.h` instruction (requires lsx).
7232 pub inline fn @"vhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7233 return encodeVdVjVk(0x70548000, p0, p1, p2);
7234 }
7235
7236 /// Encodes a `vhaddw.wu.hu` instruction (requires lsx).
7237 pub inline fn @"vhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7238 return encodeVdVjVk(0x70588000, p0, p1, p2);
7239 }
7240
7241 /// Encodes a `vhsubw.d.w` instruction (requires lsx).
7242 pub inline fn @"vhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7243 return encodeVdVjVk(0x70570000, p0, p1, p2);
7244 }
7245
7246 /// Encodes a `vhsubw.du.wu` instruction (requires lsx).
7247 pub inline fn @"vhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7248 return encodeVdVjVk(0x705b0000, p0, p1, p2);
7249 }
7250
7251 /// Encodes a `vhsubw.h.b` instruction (requires lsx).
7252 pub inline fn @"vhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7253 return encodeVdVjVk(0x70560000, p0, p1, p2);
7254 }
7255
7256 /// Encodes a `vhsubw.hu.bu` instruction (requires lsx).
7257 pub inline fn @"vhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7258 return encodeVdVjVk(0x705a0000, p0, p1, p2);
7259 }
7260
7261 /// Encodes a `vhsubw.q.d` instruction (requires lsx).
7262 pub inline fn @"vhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7263 return encodeVdVjVk(0x70578000, p0, p1, p2);
7264 }
7265
7266 /// Encodes a `vhsubw.qu.du` instruction (requires lsx).
7267 pub inline fn @"vhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction {
7268 return encodeVdVjVk(0x705b8000, p0, p1, p2);
7269 }
7270
7271 /// Encodes a `vhsubw.w.h` instruction (requires lsx).
7272 pub inline fn @"vhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7273 return encodeVdVjVk(0x70568000, p0, p1, p2);
7274 }
7275
7276 /// Encodes a `vhsubw.wu.hu` instruction (requires lsx).
7277 pub inline fn @"vhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7278 return encodeVdVjVk(0x705a8000, p0, p1, p2);
7279 }
7280
7281 /// Encodes a `vilvh.b` instruction (requires lsx).
7282 pub inline fn @"vilvh.b"(p0: Register, p1: Register, p2: Register) Instruction {
7283 return encodeVdVjVk(0x711c0000, p0, p1, p2);
7284 }
7285
7286 /// Encodes a `vilvh.d` instruction (requires lsx).
7287 pub inline fn @"vilvh.d"(p0: Register, p1: Register, p2: Register) Instruction {
7288 return encodeVdVjVk(0x711d8000, p0, p1, p2);
7289 }
7290
7291 /// Encodes a `vilvh.h` instruction (requires lsx).
7292 pub inline fn @"vilvh.h"(p0: Register, p1: Register, p2: Register) Instruction {
7293 return encodeVdVjVk(0x711c8000, p0, p1, p2);
7294 }
7295
7296 /// Encodes a `vilvh.w` instruction (requires lsx).
7297 pub inline fn @"vilvh.w"(p0: Register, p1: Register, p2: Register) Instruction {
7298 return encodeVdVjVk(0x711d0000, p0, p1, p2);
7299 }
7300
7301 /// Encodes a `vilvl.b` instruction (requires lsx).
7302 pub inline fn @"vilvl.b"(p0: Register, p1: Register, p2: Register) Instruction {
7303 return encodeVdVjVk(0x711a0000, p0, p1, p2);
7304 }
7305
7306 /// Encodes a `vilvl.d` instruction (requires lsx).
7307 pub inline fn @"vilvl.d"(p0: Register, p1: Register, p2: Register) Instruction {
7308 return encodeVdVjVk(0x711b8000, p0, p1, p2);
7309 }
7310
7311 /// Encodes a `vilvl.h` instruction (requires lsx).
7312 pub inline fn @"vilvl.h"(p0: Register, p1: Register, p2: Register) Instruction {
7313 return encodeVdVjVk(0x711a8000, p0, p1, p2);
7314 }
7315
7316 /// Encodes a `vilvl.w` instruction (requires lsx).
7317 pub inline fn @"vilvl.w"(p0: Register, p1: Register, p2: Register) Instruction {
7318 return encodeVdVjVk(0x711b0000, p0, p1, p2);
7319 }
7320
7321 /// Encodes a `vinsgr2vr.b` instruction (requires lsx).
7322 pub inline fn @"vinsgr2vr.b"(p0: Register, p1: Register, p2: u4) Instruction {
7323 return encodeVdJUk4(0x72eb8000, p0, p1, p2);
7324 }
7325
7326 /// Encodes a `vinsgr2vr.d` instruction (requires lsx).
7327 pub inline fn @"vinsgr2vr.d"(p0: Register, p1: Register, p2: u1) Instruction {
7328 return encodeVdJUk1(0x72ebf000, p0, p1, p2);
7329 }
7330
7331 /// Encodes a `vinsgr2vr.h` instruction (requires lsx).
7332 pub inline fn @"vinsgr2vr.h"(p0: Register, p1: Register, p2: u3) Instruction {
7333 return encodeVdJUk3(0x72ebc000, p0, p1, p2);
7334 }
7335
7336 /// Encodes a `vinsgr2vr.w` instruction (requires lsx).
7337 pub inline fn @"vinsgr2vr.w"(p0: Register, p1: Register, p2: u2) Instruction {
7338 return encodeVdJUk2(0x72ebe000, p0, p1, p2);
7339 }
7340
7341 /// Encodes a `vld` instruction (requires lsx).
7342 pub inline fn vld(p0: Register, p1: Register, p2: i12) Instruction {
7343 return encodeVdJSk12(0x2c000000, p0, p1, p2);
7344 }
7345
7346 /// Encodes a `vldi` instruction (requires lsx).
7347 pub inline fn vldi(p0: Register, p1: i13) Instruction {
7348 return encodeVdSj13(0x73e00000, p0, p1);
7349 }
7350
7351 /// Encodes a `vldrepl.b` instruction (requires lsx).
7352 pub inline fn @"vldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction {
7353 return encodeVdJSk12(0x30800000, p0, p1, p2);
7354 }
7355
7356 /// Encodes a `vldrepl.d` instruction (requires lsx).
7357 pub inline fn @"vldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction {
7358 return encodeVdJSk9ps3(0x30100000, p0, p1, p2);
7359 }
7360
7361 /// Encodes a `vldrepl.h` instruction (requires lsx).
7362 pub inline fn @"vldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction {
7363 return encodeVdJSk11ps1(0x30400000, p0, p1, p2);
7364 }
7365
7366 /// Encodes a `vldrepl.w` instruction (requires lsx).
7367 pub inline fn @"vldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction {
7368 return encodeVdJSk10ps2(0x30200000, p0, p1, p2);
7369 }
7370
7371 /// Encodes a `vldx` instruction (requires lsx).
7372 pub inline fn vldx(p0: Register, p1: Register, p2: Register) Instruction {
7373 return encodeVdJK(0x38400000, p0, p1, p2);
7374 }
7375
7376 /// Encodes a `vmadd.b` instruction (requires lsx).
7377 pub inline fn @"vmadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
7378 return encodeVdVjVk(0x70a80000, p0, p1, p2);
7379 }
7380
7381 /// Encodes a `vmadd.d` instruction (requires lsx).
7382 pub inline fn @"vmadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
7383 return encodeVdVjVk(0x70a98000, p0, p1, p2);
7384 }
7385
7386 /// Encodes a `vmadd.h` instruction (requires lsx).
7387 pub inline fn @"vmadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
7388 return encodeVdVjVk(0x70a88000, p0, p1, p2);
7389 }
7390
7391 /// Encodes a `vmadd.w` instruction (requires lsx).
7392 pub inline fn @"vmadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
7393 return encodeVdVjVk(0x70a90000, p0, p1, p2);
7394 }
7395
7396 /// Encodes a `vmaddwev.d.w` instruction (requires lsx).
7397 pub inline fn @"vmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7398 return encodeVdVjVk(0x70ad0000, p0, p1, p2);
7399 }
7400
7401 /// Encodes a `vmaddwev.d.wu` instruction (requires lsx).
7402 pub inline fn @"vmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7403 return encodeVdVjVk(0x70b50000, p0, p1, p2);
7404 }
7405
7406 /// Encodes a `vmaddwev.d.wu.w` instruction (requires lsx).
7407 pub inline fn @"vmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
7408 return encodeVdVjVk(0x70bd0000, p0, p1, p2);
7409 }
7410
7411 /// Encodes a `vmaddwev.h.b` instruction (requires lsx).
7412 pub inline fn @"vmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7413 return encodeVdVjVk(0x70ac0000, p0, p1, p2);
7414 }
7415
7416 /// Encodes a `vmaddwev.h.bu` instruction (requires lsx).
7417 pub inline fn @"vmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7418 return encodeVdVjVk(0x70b40000, p0, p1, p2);
7419 }
7420
7421 /// Encodes a `vmaddwev.h.bu.b` instruction (requires lsx).
7422 pub inline fn @"vmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
7423 return encodeVdVjVk(0x70bc0000, p0, p1, p2);
7424 }
7425
7426 /// Encodes a `vmaddwev.q.d` instruction (requires lsx).
7427 pub inline fn @"vmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7428 return encodeVdVjVk(0x70ad8000, p0, p1, p2);
7429 }
7430
7431 /// Encodes a `vmaddwev.q.du` instruction (requires lsx).
7432 pub inline fn @"vmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
7433 return encodeVdVjVk(0x70b58000, p0, p1, p2);
7434 }
7435
7436 /// Encodes a `vmaddwev.q.du.d` instruction (requires lsx).
7437 pub inline fn @"vmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
7438 return encodeVdVjVk(0x70bd8000, p0, p1, p2);
7439 }
7440
7441 /// Encodes a `vmaddwev.w.h` instruction (requires lsx).
7442 pub inline fn @"vmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7443 return encodeVdVjVk(0x70ac8000, p0, p1, p2);
7444 }
7445
7446 /// Encodes a `vmaddwev.w.hu` instruction (requires lsx).
7447 pub inline fn @"vmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7448 return encodeVdVjVk(0x70b48000, p0, p1, p2);
7449 }
7450
7451 /// Encodes a `vmaddwev.w.hu.h` instruction (requires lsx).
7452 pub inline fn @"vmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
7453 return encodeVdVjVk(0x70bc8000, p0, p1, p2);
7454 }
7455
7456 /// Encodes a `vmaddwod.d.w` instruction (requires lsx).
7457 pub inline fn @"vmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7458 return encodeVdVjVk(0x70af0000, p0, p1, p2);
7459 }
7460
7461 /// Encodes a `vmaddwod.d.wu` instruction (requires lsx).
7462 pub inline fn @"vmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7463 return encodeVdVjVk(0x70b70000, p0, p1, p2);
7464 }
7465
7466 /// Encodes a `vmaddwod.d.wu.w` instruction (requires lsx).
7467 pub inline fn @"vmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
7468 return encodeVdVjVk(0x70bf0000, p0, p1, p2);
7469 }
7470
7471 /// Encodes a `vmaddwod.h.b` instruction (requires lsx).
7472 pub inline fn @"vmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7473 return encodeVdVjVk(0x70ae0000, p0, p1, p2);
7474 }
7475
7476 /// Encodes a `vmaddwod.h.bu` instruction (requires lsx).
7477 pub inline fn @"vmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7478 return encodeVdVjVk(0x70b60000, p0, p1, p2);
7479 }
7480
7481 /// Encodes a `vmaddwod.h.bu.b` instruction (requires lsx).
7482 pub inline fn @"vmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
7483 return encodeVdVjVk(0x70be0000, p0, p1, p2);
7484 }
7485
7486 /// Encodes a `vmaddwod.q.d` instruction (requires lsx).
7487 pub inline fn @"vmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7488 return encodeVdVjVk(0x70af8000, p0, p1, p2);
7489 }
7490
7491 /// Encodes a `vmaddwod.q.du` instruction (requires lsx).
7492 pub inline fn @"vmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
7493 return encodeVdVjVk(0x70b78000, p0, p1, p2);
7494 }
7495
7496 /// Encodes a `vmaddwod.q.du.d` instruction (requires lsx).
7497 pub inline fn @"vmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
7498 return encodeVdVjVk(0x70bf8000, p0, p1, p2);
7499 }
7500
7501 /// Encodes a `vmaddwod.w.h` instruction (requires lsx).
7502 pub inline fn @"vmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7503 return encodeVdVjVk(0x70ae8000, p0, p1, p2);
7504 }
7505
7506 /// Encodes a `vmaddwod.w.hu` instruction (requires lsx).
7507 pub inline fn @"vmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7508 return encodeVdVjVk(0x70b68000, p0, p1, p2);
7509 }
7510
7511 /// Encodes a `vmaddwod.w.hu.h` instruction (requires lsx).
7512 pub inline fn @"vmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
7513 return encodeVdVjVk(0x70be8000, p0, p1, p2);
7514 }
7515
7516 /// Encodes a `vmax.b` instruction (requires lsx).
7517 pub inline fn @"vmax.b"(p0: Register, p1: Register, p2: Register) Instruction {
7518 return encodeVdVjVk(0x70700000, p0, p1, p2);
7519 }
7520
7521 /// Encodes a `vmax.bu` instruction (requires lsx).
7522 pub inline fn @"vmax.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7523 return encodeVdVjVk(0x70740000, p0, p1, p2);
7524 }
7525
7526 /// Encodes a `vmax.d` instruction (requires lsx).
7527 pub inline fn @"vmax.d"(p0: Register, p1: Register, p2: Register) Instruction {
7528 return encodeVdVjVk(0x70718000, p0, p1, p2);
7529 }
7530
7531 /// Encodes a `vmax.du` instruction (requires lsx).
7532 pub inline fn @"vmax.du"(p0: Register, p1: Register, p2: Register) Instruction {
7533 return encodeVdVjVk(0x70758000, p0, p1, p2);
7534 }
7535
7536 /// Encodes a `vmax.h` instruction (requires lsx).
7537 pub inline fn @"vmax.h"(p0: Register, p1: Register, p2: Register) Instruction {
7538 return encodeVdVjVk(0x70708000, p0, p1, p2);
7539 }
7540
7541 /// Encodes a `vmax.hu` instruction (requires lsx).
7542 pub inline fn @"vmax.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7543 return encodeVdVjVk(0x70748000, p0, p1, p2);
7544 }
7545
7546 /// Encodes a `vmax.w` instruction (requires lsx).
7547 pub inline fn @"vmax.w"(p0: Register, p1: Register, p2: Register) Instruction {
7548 return encodeVdVjVk(0x70710000, p0, p1, p2);
7549 }
7550
7551 /// Encodes a `vmax.wu` instruction (requires lsx).
7552 pub inline fn @"vmax.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7553 return encodeVdVjVk(0x70750000, p0, p1, p2);
7554 }
7555
7556 /// Encodes a `vmaxi.b` instruction (requires lsx).
7557 pub inline fn @"vmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction {
7558 return encodeVdVjSk5(0x72900000, p0, p1, p2);
7559 }
7560
7561 /// Encodes a `vmaxi.bu` instruction (requires lsx).
7562 pub inline fn @"vmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
7563 return encodeVdVjUk5(0x72940000, p0, p1, p2);
7564 }
7565
7566 /// Encodes a `vmaxi.d` instruction (requires lsx).
7567 pub inline fn @"vmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction {
7568 return encodeVdVjSk5(0x72918000, p0, p1, p2);
7569 }
7570
7571 /// Encodes a `vmaxi.du` instruction (requires lsx).
7572 pub inline fn @"vmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction {
7573 return encodeVdVjUk5(0x72958000, p0, p1, p2);
7574 }
7575
7576 /// Encodes a `vmaxi.h` instruction (requires lsx).
7577 pub inline fn @"vmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction {
7578 return encodeVdVjSk5(0x72908000, p0, p1, p2);
7579 }
7580
7581 /// Encodes a `vmaxi.hu` instruction (requires lsx).
7582 pub inline fn @"vmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
7583 return encodeVdVjUk5(0x72948000, p0, p1, p2);
7584 }
7585
7586 /// Encodes a `vmaxi.w` instruction (requires lsx).
7587 pub inline fn @"vmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction {
7588 return encodeVdVjSk5(0x72910000, p0, p1, p2);
7589 }
7590
7591 /// Encodes a `vmaxi.wu` instruction (requires lsx).
7592 pub inline fn @"vmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
7593 return encodeVdVjUk5(0x72950000, p0, p1, p2);
7594 }
7595
7596 /// Encodes a `vmepatmsk.v` instruction (requires lsx).
7597 pub inline fn @"vmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction {
7598 return encodeVdUj5Uk5(0x729b8000, p0, p1, p2);
7599 }
7600
7601 /// Encodes a `vmin.b` instruction (requires lsx).
7602 pub inline fn @"vmin.b"(p0: Register, p1: Register, p2: Register) Instruction {
7603 return encodeVdVjVk(0x70720000, p0, p1, p2);
7604 }
7605
7606 /// Encodes a `vmin.bu` instruction (requires lsx).
7607 pub inline fn @"vmin.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7608 return encodeVdVjVk(0x70760000, p0, p1, p2);
7609 }
7610
7611 /// Encodes a `vmin.d` instruction (requires lsx).
7612 pub inline fn @"vmin.d"(p0: Register, p1: Register, p2: Register) Instruction {
7613 return encodeVdVjVk(0x70738000, p0, p1, p2);
7614 }
7615
7616 /// Encodes a `vmin.du` instruction (requires lsx).
7617 pub inline fn @"vmin.du"(p0: Register, p1: Register, p2: Register) Instruction {
7618 return encodeVdVjVk(0x70778000, p0, p1, p2);
7619 }
7620
7621 /// Encodes a `vmin.h` instruction (requires lsx).
7622 pub inline fn @"vmin.h"(p0: Register, p1: Register, p2: Register) Instruction {
7623 return encodeVdVjVk(0x70728000, p0, p1, p2);
7624 }
7625
7626 /// Encodes a `vmin.hu` instruction (requires lsx).
7627 pub inline fn @"vmin.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7628 return encodeVdVjVk(0x70768000, p0, p1, p2);
7629 }
7630
7631 /// Encodes a `vmin.w` instruction (requires lsx).
7632 pub inline fn @"vmin.w"(p0: Register, p1: Register, p2: Register) Instruction {
7633 return encodeVdVjVk(0x70730000, p0, p1, p2);
7634 }
7635
7636 /// Encodes a `vmin.wu` instruction (requires lsx).
7637 pub inline fn @"vmin.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7638 return encodeVdVjVk(0x70770000, p0, p1, p2);
7639 }
7640
7641 /// Encodes a `vmini.b` instruction (requires lsx).
7642 pub inline fn @"vmini.b"(p0: Register, p1: Register, p2: i5) Instruction {
7643 return encodeVdVjSk5(0x72920000, p0, p1, p2);
7644 }
7645
7646 /// Encodes a `vmini.bu` instruction (requires lsx).
7647 pub inline fn @"vmini.bu"(p0: Register, p1: Register, p2: u5) Instruction {
7648 return encodeVdVjUk5(0x72960000, p0, p1, p2);
7649 }
7650
7651 /// Encodes a `vmini.d` instruction (requires lsx).
7652 pub inline fn @"vmini.d"(p0: Register, p1: Register, p2: i5) Instruction {
7653 return encodeVdVjSk5(0x72938000, p0, p1, p2);
7654 }
7655
7656 /// Encodes a `vmini.du` instruction (requires lsx).
7657 pub inline fn @"vmini.du"(p0: Register, p1: Register, p2: u5) Instruction {
7658 return encodeVdVjUk5(0x72978000, p0, p1, p2);
7659 }
7660
7661 /// Encodes a `vmini.h` instruction (requires lsx).
7662 pub inline fn @"vmini.h"(p0: Register, p1: Register, p2: i5) Instruction {
7663 return encodeVdVjSk5(0x72928000, p0, p1, p2);
7664 }
7665
7666 /// Encodes a `vmini.hu` instruction (requires lsx).
7667 pub inline fn @"vmini.hu"(p0: Register, p1: Register, p2: u5) Instruction {
7668 return encodeVdVjUk5(0x72968000, p0, p1, p2);
7669 }
7670
7671 /// Encodes a `vmini.w` instruction (requires lsx).
7672 pub inline fn @"vmini.w"(p0: Register, p1: Register, p2: i5) Instruction {
7673 return encodeVdVjSk5(0x72930000, p0, p1, p2);
7674 }
7675
7676 /// Encodes a `vmini.wu` instruction (requires lsx).
7677 pub inline fn @"vmini.wu"(p0: Register, p1: Register, p2: u5) Instruction {
7678 return encodeVdVjUk5(0x72970000, p0, p1, p2);
7679 }
7680
7681 /// Encodes a `vmod.b` instruction (requires lsx).
7682 pub inline fn @"vmod.b"(p0: Register, p1: Register, p2: Register) Instruction {
7683 return encodeVdVjVk(0x70e20000, p0, p1, p2);
7684 }
7685
7686 /// Encodes a `vmod.bu` instruction (requires lsx).
7687 pub inline fn @"vmod.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7688 return encodeVdVjVk(0x70e60000, p0, p1, p2);
7689 }
7690
7691 /// Encodes a `vmod.d` instruction (requires lsx).
7692 pub inline fn @"vmod.d"(p0: Register, p1: Register, p2: Register) Instruction {
7693 return encodeVdVjVk(0x70e38000, p0, p1, p2);
7694 }
7695
7696 /// Encodes a `vmod.du` instruction (requires lsx).
7697 pub inline fn @"vmod.du"(p0: Register, p1: Register, p2: Register) Instruction {
7698 return encodeVdVjVk(0x70e78000, p0, p1, p2);
7699 }
7700
7701 /// Encodes a `vmod.h` instruction (requires lsx).
7702 pub inline fn @"vmod.h"(p0: Register, p1: Register, p2: Register) Instruction {
7703 return encodeVdVjVk(0x70e28000, p0, p1, p2);
7704 }
7705
7706 /// Encodes a `vmod.hu` instruction (requires lsx).
7707 pub inline fn @"vmod.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7708 return encodeVdVjVk(0x70e68000, p0, p1, p2);
7709 }
7710
7711 /// Encodes a `vmod.w` instruction (requires lsx).
7712 pub inline fn @"vmod.w"(p0: Register, p1: Register, p2: Register) Instruction {
7713 return encodeVdVjVk(0x70e30000, p0, p1, p2);
7714 }
7715
7716 /// Encodes a `vmod.wu` instruction (requires lsx).
7717 pub inline fn @"vmod.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7718 return encodeVdVjVk(0x70e70000, p0, p1, p2);
7719 }
7720
7721 /// Encodes a `vmskgez.b` instruction (requires lsx).
7722 pub inline fn @"vmskgez.b"(p0: Register, p1: Register) Instruction {
7723 return encodeVdVj(0x729c5000, p0, p1);
7724 }
7725
7726 /// Encodes a `vmskltz.b` instruction (requires lsx).
7727 pub inline fn @"vmskltz.b"(p0: Register, p1: Register) Instruction {
7728 return encodeVdVj(0x729c4000, p0, p1);
7729 }
7730
7731 /// Encodes a `vmskltz.d` instruction (requires lsx).
7732 pub inline fn @"vmskltz.d"(p0: Register, p1: Register) Instruction {
7733 return encodeVdVj(0x729c4c00, p0, p1);
7734 }
7735
7736 /// Encodes a `vmskltz.h` instruction (requires lsx).
7737 pub inline fn @"vmskltz.h"(p0: Register, p1: Register) Instruction {
7738 return encodeVdVj(0x729c4400, p0, p1);
7739 }
7740
7741 /// Encodes a `vmskltz.w` instruction (requires lsx).
7742 pub inline fn @"vmskltz.w"(p0: Register, p1: Register) Instruction {
7743 return encodeVdVj(0x729c4800, p0, p1);
7744 }
7745
7746 /// Encodes a `vmsknz.b` instruction (requires lsx).
7747 pub inline fn @"vmsknz.b"(p0: Register, p1: Register) Instruction {
7748 return encodeVdVj(0x729c6000, p0, p1);
7749 }
7750
7751 /// Encodes a `vmsub.b` instruction (requires lsx).
7752 pub inline fn @"vmsub.b"(p0: Register, p1: Register, p2: Register) Instruction {
7753 return encodeVdVjVk(0x70aa0000, p0, p1, p2);
7754 }
7755
7756 /// Encodes a `vmsub.d` instruction (requires lsx).
7757 pub inline fn @"vmsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
7758 return encodeVdVjVk(0x70ab8000, p0, p1, p2);
7759 }
7760
7761 /// Encodes a `vmsub.h` instruction (requires lsx).
7762 pub inline fn @"vmsub.h"(p0: Register, p1: Register, p2: Register) Instruction {
7763 return encodeVdVjVk(0x70aa8000, p0, p1, p2);
7764 }
7765
7766 /// Encodes a `vmsub.w` instruction (requires lsx).
7767 pub inline fn @"vmsub.w"(p0: Register, p1: Register, p2: Register) Instruction {
7768 return encodeVdVjVk(0x70ab0000, p0, p1, p2);
7769 }
7770
7771 /// Encodes a `vmuh.b` instruction (requires lsx).
7772 pub inline fn @"vmuh.b"(p0: Register, p1: Register, p2: Register) Instruction {
7773 return encodeVdVjVk(0x70860000, p0, p1, p2);
7774 }
7775
7776 /// Encodes a `vmuh.bu` instruction (requires lsx).
7777 pub inline fn @"vmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7778 return encodeVdVjVk(0x70880000, p0, p1, p2);
7779 }
7780
7781 /// Encodes a `vmuh.d` instruction (requires lsx).
7782 pub inline fn @"vmuh.d"(p0: Register, p1: Register, p2: Register) Instruction {
7783 return encodeVdVjVk(0x70878000, p0, p1, p2);
7784 }
7785
7786 /// Encodes a `vmuh.du` instruction (requires lsx).
7787 pub inline fn @"vmuh.du"(p0: Register, p1: Register, p2: Register) Instruction {
7788 return encodeVdVjVk(0x70898000, p0, p1, p2);
7789 }
7790
7791 /// Encodes a `vmuh.h` instruction (requires lsx).
7792 pub inline fn @"vmuh.h"(p0: Register, p1: Register, p2: Register) Instruction {
7793 return encodeVdVjVk(0x70868000, p0, p1, p2);
7794 }
7795
7796 /// Encodes a `vmuh.hu` instruction (requires lsx).
7797 pub inline fn @"vmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7798 return encodeVdVjVk(0x70888000, p0, p1, p2);
7799 }
7800
7801 /// Encodes a `vmuh.w` instruction (requires lsx).
7802 pub inline fn @"vmuh.w"(p0: Register, p1: Register, p2: Register) Instruction {
7803 return encodeVdVjVk(0x70870000, p0, p1, p2);
7804 }
7805
7806 /// Encodes a `vmuh.wu` instruction (requires lsx).
7807 pub inline fn @"vmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7808 return encodeVdVjVk(0x70890000, p0, p1, p2);
7809 }
7810
7811 /// Encodes a `vmul.b` instruction (requires lsx).
7812 pub inline fn @"vmul.b"(p0: Register, p1: Register, p2: Register) Instruction {
7813 return encodeVdVjVk(0x70840000, p0, p1, p2);
7814 }
7815
7816 /// Encodes a `vmul.d` instruction (requires lsx).
7817 pub inline fn @"vmul.d"(p0: Register, p1: Register, p2: Register) Instruction {
7818 return encodeVdVjVk(0x70858000, p0, p1, p2);
7819 }
7820
7821 /// Encodes a `vmul.h` instruction (requires lsx).
7822 pub inline fn @"vmul.h"(p0: Register, p1: Register, p2: Register) Instruction {
7823 return encodeVdVjVk(0x70848000, p0, p1, p2);
7824 }
7825
7826 /// Encodes a `vmul.w` instruction (requires lsx).
7827 pub inline fn @"vmul.w"(p0: Register, p1: Register, p2: Register) Instruction {
7828 return encodeVdVjVk(0x70850000, p0, p1, p2);
7829 }
7830
7831 /// Encodes a `vmulwev.d.w` instruction (requires lsx).
7832 pub inline fn @"vmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7833 return encodeVdVjVk(0x70910000, p0, p1, p2);
7834 }
7835
7836 /// Encodes a `vmulwev.d.wu` instruction (requires lsx).
7837 pub inline fn @"vmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7838 return encodeVdVjVk(0x70990000, p0, p1, p2);
7839 }
7840
7841 /// Encodes a `vmulwev.d.wu.w` instruction (requires lsx).
7842 pub inline fn @"vmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
7843 return encodeVdVjVk(0x70a10000, p0, p1, p2);
7844 }
7845
7846 /// Encodes a `vmulwev.h.b` instruction (requires lsx).
7847 pub inline fn @"vmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7848 return encodeVdVjVk(0x70900000, p0, p1, p2);
7849 }
7850
7851 /// Encodes a `vmulwev.h.bu` instruction (requires lsx).
7852 pub inline fn @"vmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7853 return encodeVdVjVk(0x70980000, p0, p1, p2);
7854 }
7855
7856 /// Encodes a `vmulwev.h.bu.b` instruction (requires lsx).
7857 pub inline fn @"vmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
7858 return encodeVdVjVk(0x70a00000, p0, p1, p2);
7859 }
7860
7861 /// Encodes a `vmulwev.q.d` instruction (requires lsx).
7862 pub inline fn @"vmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7863 return encodeVdVjVk(0x70918000, p0, p1, p2);
7864 }
7865
7866 /// Encodes a `vmulwev.q.du` instruction (requires lsx).
7867 pub inline fn @"vmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
7868 return encodeVdVjVk(0x70998000, p0, p1, p2);
7869 }
7870
7871 /// Encodes a `vmulwev.q.du.d` instruction (requires lsx).
7872 pub inline fn @"vmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
7873 return encodeVdVjVk(0x70a18000, p0, p1, p2);
7874 }
7875
7876 /// Encodes a `vmulwev.w.h` instruction (requires lsx).
7877 pub inline fn @"vmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7878 return encodeVdVjVk(0x70908000, p0, p1, p2);
7879 }
7880
7881 /// Encodes a `vmulwev.w.hu` instruction (requires lsx).
7882 pub inline fn @"vmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7883 return encodeVdVjVk(0x70988000, p0, p1, p2);
7884 }
7885
7886 /// Encodes a `vmulwev.w.hu.h` instruction (requires lsx).
7887 pub inline fn @"vmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
7888 return encodeVdVjVk(0x70a08000, p0, p1, p2);
7889 }
7890
7891 /// Encodes a `vmulwod.d.w` instruction (requires lsx).
7892 pub inline fn @"vmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
7893 return encodeVdVjVk(0x70930000, p0, p1, p2);
7894 }
7895
7896 /// Encodes a `vmulwod.d.wu` instruction (requires lsx).
7897 pub inline fn @"vmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
7898 return encodeVdVjVk(0x709b0000, p0, p1, p2);
7899 }
7900
7901 /// Encodes a `vmulwod.d.wu.w` instruction (requires lsx).
7902 pub inline fn @"vmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
7903 return encodeVdVjVk(0x70a30000, p0, p1, p2);
7904 }
7905
7906 /// Encodes a `vmulwod.h.b` instruction (requires lsx).
7907 pub inline fn @"vmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
7908 return encodeVdVjVk(0x70920000, p0, p1, p2);
7909 }
7910
7911 /// Encodes a `vmulwod.h.bu` instruction (requires lsx).
7912 pub inline fn @"vmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
7913 return encodeVdVjVk(0x709a0000, p0, p1, p2);
7914 }
7915
7916 /// Encodes a `vmulwod.h.bu.b` instruction (requires lsx).
7917 pub inline fn @"vmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
7918 return encodeVdVjVk(0x70a20000, p0, p1, p2);
7919 }
7920
7921 /// Encodes a `vmulwod.q.d` instruction (requires lsx).
7922 pub inline fn @"vmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
7923 return encodeVdVjVk(0x70938000, p0, p1, p2);
7924 }
7925
7926 /// Encodes a `vmulwod.q.du` instruction (requires lsx).
7927 pub inline fn @"vmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
7928 return encodeVdVjVk(0x709b8000, p0, p1, p2);
7929 }
7930
7931 /// Encodes a `vmulwod.q.du.d` instruction (requires lsx).
7932 pub inline fn @"vmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
7933 return encodeVdVjVk(0x70a38000, p0, p1, p2);
7934 }
7935
7936 /// Encodes a `vmulwod.w.h` instruction (requires lsx).
7937 pub inline fn @"vmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
7938 return encodeVdVjVk(0x70928000, p0, p1, p2);
7939 }
7940
7941 /// Encodes a `vmulwod.w.hu` instruction (requires lsx).
7942 pub inline fn @"vmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
7943 return encodeVdVjVk(0x709a8000, p0, p1, p2);
7944 }
7945
7946 /// Encodes a `vmulwod.w.hu.h` instruction (requires lsx).
7947 pub inline fn @"vmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
7948 return encodeVdVjVk(0x70a28000, p0, p1, p2);
7949 }
7950
7951 /// Encodes a `vneg.b` instruction (requires lsx).
7952 pub inline fn @"vneg.b"(p0: Register, p1: Register) Instruction {
7953 return encodeVdVj(0x729c3000, p0, p1);
7954 }
7955
7956 /// Encodes a `vneg.d` instruction (requires lsx).
7957 pub inline fn @"vneg.d"(p0: Register, p1: Register) Instruction {
7958 return encodeVdVj(0x729c3c00, p0, p1);
7959 }
7960
7961 /// Encodes a `vneg.h` instruction (requires lsx).
7962 pub inline fn @"vneg.h"(p0: Register, p1: Register) Instruction {
7963 return encodeVdVj(0x729c3400, p0, p1);
7964 }
7965
7966 /// Encodes a `vneg.w` instruction (requires lsx).
7967 pub inline fn @"vneg.w"(p0: Register, p1: Register) Instruction {
7968 return encodeVdVj(0x729c3800, p0, p1);
7969 }
7970
7971 /// Encodes a `vnor.v` instruction (requires lsx).
7972 pub inline fn @"vnor.v"(p0: Register, p1: Register, p2: Register) Instruction {
7973 return encodeVdVjVk(0x71278000, p0, p1, p2);
7974 }
7975
7976 /// Encodes a `vnori.b` instruction (requires lsx).
7977 pub inline fn @"vnori.b"(p0: Register, p1: Register, p2: u8) Instruction {
7978 return encodeVdVjUk8(0x73dc0000, p0, p1, p2);
7979 }
7980
7981 /// Encodes a `vor.v` instruction (requires lsx).
7982 pub inline fn @"vor.v"(p0: Register, p1: Register, p2: Register) Instruction {
7983 return encodeVdVjVk(0x71268000, p0, p1, p2);
7984 }
7985
7986 /// Encodes a `vori.b` instruction (requires lsx).
7987 pub inline fn @"vori.b"(p0: Register, p1: Register, p2: u8) Instruction {
7988 return encodeVdVjUk8(0x73d40000, p0, p1, p2);
7989 }
7990
7991 /// Encodes a `vorn.v` instruction (requires lsx).
7992 pub inline fn @"vorn.v"(p0: Register, p1: Register, p2: Register) Instruction {
7993 return encodeVdVjVk(0x71288000, p0, p1, p2);
7994 }
7995
7996 /// Encodes a `vpackev.b` instruction (requires lsx).
7997 pub inline fn @"vpackev.b"(p0: Register, p1: Register, p2: Register) Instruction {
7998 return encodeVdVjVk(0x71160000, p0, p1, p2);
7999 }
8000
8001 /// Encodes a `vpackev.d` instruction (requires lsx).
8002 pub inline fn @"vpackev.d"(p0: Register, p1: Register, p2: Register) Instruction {
8003 return encodeVdVjVk(0x71178000, p0, p1, p2);
8004 }
8005
8006 /// Encodes a `vpackev.h` instruction (requires lsx).
8007 pub inline fn @"vpackev.h"(p0: Register, p1: Register, p2: Register) Instruction {
8008 return encodeVdVjVk(0x71168000, p0, p1, p2);
8009 }
8010
8011 /// Encodes a `vpackev.w` instruction (requires lsx).
8012 pub inline fn @"vpackev.w"(p0: Register, p1: Register, p2: Register) Instruction {
8013 return encodeVdVjVk(0x71170000, p0, p1, p2);
8014 }
8015
8016 /// Encodes a `vpackod.b` instruction (requires lsx).
8017 pub inline fn @"vpackod.b"(p0: Register, p1: Register, p2: Register) Instruction {
8018 return encodeVdVjVk(0x71180000, p0, p1, p2);
8019 }
8020
8021 /// Encodes a `vpackod.d` instruction (requires lsx).
8022 pub inline fn @"vpackod.d"(p0: Register, p1: Register, p2: Register) Instruction {
8023 return encodeVdVjVk(0x71198000, p0, p1, p2);
8024 }
8025
8026 /// Encodes a `vpackod.h` instruction (requires lsx).
8027 pub inline fn @"vpackod.h"(p0: Register, p1: Register, p2: Register) Instruction {
8028 return encodeVdVjVk(0x71188000, p0, p1, p2);
8029 }
8030
8031 /// Encodes a `vpackod.w` instruction (requires lsx).
8032 pub inline fn @"vpackod.w"(p0: Register, p1: Register, p2: Register) Instruction {
8033 return encodeVdVjVk(0x71190000, p0, p1, p2);
8034 }
8035
8036 /// Encodes a `vpcnt.b` instruction (requires lsx).
8037 pub inline fn @"vpcnt.b"(p0: Register, p1: Register) Instruction {
8038 return encodeVdVj(0x729c2000, p0, p1);
8039 }
8040
8041 /// Encodes a `vpcnt.d` instruction (requires lsx).
8042 pub inline fn @"vpcnt.d"(p0: Register, p1: Register) Instruction {
8043 return encodeVdVj(0x729c2c00, p0, p1);
8044 }
8045
8046 /// Encodes a `vpcnt.h` instruction (requires lsx).
8047 pub inline fn @"vpcnt.h"(p0: Register, p1: Register) Instruction {
8048 return encodeVdVj(0x729c2400, p0, p1);
8049 }
8050
8051 /// Encodes a `vpcnt.w` instruction (requires lsx).
8052 pub inline fn @"vpcnt.w"(p0: Register, p1: Register) Instruction {
8053 return encodeVdVj(0x729c2800, p0, p1);
8054 }
8055
8056 /// Encodes a `vpermi.w` instruction (requires lsx).
8057 pub inline fn @"vpermi.w"(p0: Register, p1: Register, p2: u8) Instruction {
8058 return encodeVdVjUk8(0x73e40000, p0, p1, p2);
8059 }
8060
8061 /// Encodes a `vpickev.b` instruction (requires lsx).
8062 pub inline fn @"vpickev.b"(p0: Register, p1: Register, p2: Register) Instruction {
8063 return encodeVdVjVk(0x711e0000, p0, p1, p2);
8064 }
8065
8066 /// Encodes a `vpickev.d` instruction (requires lsx).
8067 pub inline fn @"vpickev.d"(p0: Register, p1: Register, p2: Register) Instruction {
8068 return encodeVdVjVk(0x711f8000, p0, p1, p2);
8069 }
8070
8071 /// Encodes a `vpickev.h` instruction (requires lsx).
8072 pub inline fn @"vpickev.h"(p0: Register, p1: Register, p2: Register) Instruction {
8073 return encodeVdVjVk(0x711e8000, p0, p1, p2);
8074 }
8075
8076 /// Encodes a `vpickev.w` instruction (requires lsx).
8077 pub inline fn @"vpickev.w"(p0: Register, p1: Register, p2: Register) Instruction {
8078 return encodeVdVjVk(0x711f0000, p0, p1, p2);
8079 }
8080
8081 /// Encodes a `vpickod.b` instruction (requires lsx).
8082 pub inline fn @"vpickod.b"(p0: Register, p1: Register, p2: Register) Instruction {
8083 return encodeVdVjVk(0x71200000, p0, p1, p2);
8084 }
8085
8086 /// Encodes a `vpickod.d` instruction (requires lsx).
8087 pub inline fn @"vpickod.d"(p0: Register, p1: Register, p2: Register) Instruction {
8088 return encodeVdVjVk(0x71218000, p0, p1, p2);
8089 }
8090
8091 /// Encodes a `vpickod.h` instruction (requires lsx).
8092 pub inline fn @"vpickod.h"(p0: Register, p1: Register, p2: Register) Instruction {
8093 return encodeVdVjVk(0x71208000, p0, p1, p2);
8094 }
8095
8096 /// Encodes a `vpickod.w` instruction (requires lsx).
8097 pub inline fn @"vpickod.w"(p0: Register, p1: Register, p2: Register) Instruction {
8098 return encodeVdVjVk(0x71210000, p0, p1, p2);
8099 }
8100
8101 /// Encodes a `vpickve2gr.b` instruction (requires lsx).
8102 pub inline fn @"vpickve2gr.b"(p0: Register, p1: Register, p2: u4) Instruction {
8103 return encodeDVjUk4(0x72ef8000, p0, p1, p2);
8104 }
8105
8106 /// Encodes a `vpickve2gr.bu` instruction (requires lsx).
8107 pub inline fn @"vpickve2gr.bu"(p0: Register, p1: Register, p2: u4) Instruction {
8108 return encodeDVjUk4(0x72f38000, p0, p1, p2);
8109 }
8110
8111 /// Encodes a `vpickve2gr.d` instruction (requires lsx).
8112 pub inline fn @"vpickve2gr.d"(p0: Register, p1: Register, p2: u1) Instruction {
8113 return encodeDVjUk1(0x72eff000, p0, p1, p2);
8114 }
8115
8116 /// Encodes a `vpickve2gr.du` instruction (requires lsx).
8117 pub inline fn @"vpickve2gr.du"(p0: Register, p1: Register, p2: u1) Instruction {
8118 return encodeDVjUk1(0x72f3f000, p0, p1, p2);
8119 }
8120
8121 /// Encodes a `vpickve2gr.h` instruction (requires lsx).
8122 pub inline fn @"vpickve2gr.h"(p0: Register, p1: Register, p2: u3) Instruction {
8123 return encodeDVjUk3(0x72efc000, p0, p1, p2);
8124 }
8125
8126 /// Encodes a `vpickve2gr.hu` instruction (requires lsx).
8127 pub inline fn @"vpickve2gr.hu"(p0: Register, p1: Register, p2: u3) Instruction {
8128 return encodeDVjUk3(0x72f3c000, p0, p1, p2);
8129 }
8130
8131 /// Encodes a `vpickve2gr.w` instruction (requires lsx).
8132 pub inline fn @"vpickve2gr.w"(p0: Register, p1: Register, p2: u2) Instruction {
8133 return encodeDVjUk2(0x72efe000, p0, p1, p2);
8134 }
8135
8136 /// Encodes a `vpickve2gr.wu` instruction (requires lsx).
8137 pub inline fn @"vpickve2gr.wu"(p0: Register, p1: Register, p2: u2) Instruction {
8138 return encodeDVjUk2(0x72f3e000, p0, p1, p2);
8139 }
8140
8141 /// Encodes a `vreplgr2vr.b` instruction (requires lsx).
8142 pub inline fn @"vreplgr2vr.b"(p0: Register, p1: Register) Instruction {
8143 return encodeVdJ(0x729f0000, p0, p1);
8144 }
8145
8146 /// Encodes a `vreplgr2vr.d` instruction (requires lsx).
8147 pub inline fn @"vreplgr2vr.d"(p0: Register, p1: Register) Instruction {
8148 return encodeVdJ(0x729f0c00, p0, p1);
8149 }
8150
8151 /// Encodes a `vreplgr2vr.h` instruction (requires lsx).
8152 pub inline fn @"vreplgr2vr.h"(p0: Register, p1: Register) Instruction {
8153 return encodeVdJ(0x729f0400, p0, p1);
8154 }
8155
8156 /// Encodes a `vreplgr2vr.w` instruction (requires lsx).
8157 pub inline fn @"vreplgr2vr.w"(p0: Register, p1: Register) Instruction {
8158 return encodeVdJ(0x729f0800, p0, p1);
8159 }
8160
8161 /// Encodes a `vreplve.b` instruction (requires lsx).
8162 pub inline fn @"vreplve.b"(p0: Register, p1: Register, p2: Register) Instruction {
8163 return encodeVdVjK(0x71220000, p0, p1, p2);
8164 }
8165
8166 /// Encodes a `vreplve.d` instruction (requires lsx).
8167 pub inline fn @"vreplve.d"(p0: Register, p1: Register, p2: Register) Instruction {
8168 return encodeVdVjK(0x71238000, p0, p1, p2);
8169 }
8170
8171 /// Encodes a `vreplve.h` instruction (requires lsx).
8172 pub inline fn @"vreplve.h"(p0: Register, p1: Register, p2: Register) Instruction {
8173 return encodeVdVjK(0x71228000, p0, p1, p2);
8174 }
8175
8176 /// Encodes a `vreplve.w` instruction (requires lsx).
8177 pub inline fn @"vreplve.w"(p0: Register, p1: Register, p2: Register) Instruction {
8178 return encodeVdVjK(0x71230000, p0, p1, p2);
8179 }
8180
8181 /// Encodes a `vreplvei.b` instruction (requires lsx).
8182 pub inline fn @"vreplvei.b"(p0: Register, p1: Register, p2: u4) Instruction {
8183 return encodeVdVjUk4(0x72f78000, p0, p1, p2);
8184 }
8185
8186 /// Encodes a `vreplvei.d` instruction (requires lsx).
8187 pub inline fn @"vreplvei.d"(p0: Register, p1: Register, p2: u1) Instruction {
8188 return encodeVdVjUk1(0x72f7f000, p0, p1, p2);
8189 }
8190
8191 /// Encodes a `vreplvei.h` instruction (requires lsx).
8192 pub inline fn @"vreplvei.h"(p0: Register, p1: Register, p2: u3) Instruction {
8193 return encodeVdVjUk3(0x72f7c000, p0, p1, p2);
8194 }
8195
8196 /// Encodes a `vreplvei.w` instruction (requires lsx).
8197 pub inline fn @"vreplvei.w"(p0: Register, p1: Register, p2: u2) Instruction {
8198 return encodeVdVjUk2(0x72f7e000, p0, p1, p2);
8199 }
8200
8201 /// Encodes a `vrotr.b` instruction (requires lsx).
8202 pub inline fn @"vrotr.b"(p0: Register, p1: Register, p2: Register) Instruction {
8203 return encodeVdVjVk(0x70ee0000, p0, p1, p2);
8204 }
8205
8206 /// Encodes a `vrotr.d` instruction (requires lsx).
8207 pub inline fn @"vrotr.d"(p0: Register, p1: Register, p2: Register) Instruction {
8208 return encodeVdVjVk(0x70ef8000, p0, p1, p2);
8209 }
8210
8211 /// Encodes a `vrotr.h` instruction (requires lsx).
8212 pub inline fn @"vrotr.h"(p0: Register, p1: Register, p2: Register) Instruction {
8213 return encodeVdVjVk(0x70ee8000, p0, p1, p2);
8214 }
8215
8216 /// Encodes a `vrotr.w` instruction (requires lsx).
8217 pub inline fn @"vrotr.w"(p0: Register, p1: Register, p2: Register) Instruction {
8218 return encodeVdVjVk(0x70ef0000, p0, p1, p2);
8219 }
8220
8221 /// Encodes a `vrotri.b` instruction (requires lsx).
8222 pub inline fn @"vrotri.b"(p0: Register, p1: Register, p2: u3) Instruction {
8223 return encodeVdVjUk3(0x72a02000, p0, p1, p2);
8224 }
8225
8226 /// Encodes a `vrotri.d` instruction (requires lsx).
8227 pub inline fn @"vrotri.d"(p0: Register, p1: Register, p2: u6) Instruction {
8228 return encodeVdVjUk6(0x72a10000, p0, p1, p2);
8229 }
8230
8231 /// Encodes a `vrotri.h` instruction (requires lsx).
8232 pub inline fn @"vrotri.h"(p0: Register, p1: Register, p2: u4) Instruction {
8233 return encodeVdVjUk4(0x72a04000, p0, p1, p2);
8234 }
8235
8236 /// Encodes a `vrotri.w` instruction (requires lsx).
8237 pub inline fn @"vrotri.w"(p0: Register, p1: Register, p2: u5) Instruction {
8238 return encodeVdVjUk5(0x72a08000, p0, p1, p2);
8239 }
8240
8241 /// Encodes a `vsadd.b` instruction (requires lsx).
8242 pub inline fn @"vsadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
8243 return encodeVdVjVk(0x70460000, p0, p1, p2);
8244 }
8245
8246 /// Encodes a `vsadd.bu` instruction (requires lsx).
8247 pub inline fn @"vsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction {
8248 return encodeVdVjVk(0x704a0000, p0, p1, p2);
8249 }
8250
8251 /// Encodes a `vsadd.d` instruction (requires lsx).
8252 pub inline fn @"vsadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
8253 return encodeVdVjVk(0x70478000, p0, p1, p2);
8254 }
8255
8256 /// Encodes a `vsadd.du` instruction (requires lsx).
8257 pub inline fn @"vsadd.du"(p0: Register, p1: Register, p2: Register) Instruction {
8258 return encodeVdVjVk(0x704b8000, p0, p1, p2);
8259 }
8260
8261 /// Encodes a `vsadd.h` instruction (requires lsx).
8262 pub inline fn @"vsadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
8263 return encodeVdVjVk(0x70468000, p0, p1, p2);
8264 }
8265
8266 /// Encodes a `vsadd.hu` instruction (requires lsx).
8267 pub inline fn @"vsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction {
8268 return encodeVdVjVk(0x704a8000, p0, p1, p2);
8269 }
8270
8271 /// Encodes a `vsadd.w` instruction (requires lsx).
8272 pub inline fn @"vsadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
8273 return encodeVdVjVk(0x70470000, p0, p1, p2);
8274 }
8275
8276 /// Encodes a `vsadd.wu` instruction (requires lsx).
8277 pub inline fn @"vsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction {
8278 return encodeVdVjVk(0x704b0000, p0, p1, p2);
8279 }
8280
8281 /// Encodes a `vsat.b` instruction (requires lsx).
8282 pub inline fn @"vsat.b"(p0: Register, p1: Register, p2: u3) Instruction {
8283 return encodeVdVjUk3(0x73242000, p0, p1, p2);
8284 }
8285
8286 /// Encodes a `vsat.bu` instruction (requires lsx).
8287 pub inline fn @"vsat.bu"(p0: Register, p1: Register, p2: u3) Instruction {
8288 return encodeVdVjUk3(0x73282000, p0, p1, p2);
8289 }
8290
8291 /// Encodes a `vsat.d` instruction (requires lsx).
8292 pub inline fn @"vsat.d"(p0: Register, p1: Register, p2: u6) Instruction {
8293 return encodeVdVjUk6(0x73250000, p0, p1, p2);
8294 }
8295
8296 /// Encodes a `vsat.du` instruction (requires lsx).
8297 pub inline fn @"vsat.du"(p0: Register, p1: Register, p2: u6) Instruction {
8298 return encodeVdVjUk6(0x73290000, p0, p1, p2);
8299 }
8300
8301 /// Encodes a `vsat.h` instruction (requires lsx).
8302 pub inline fn @"vsat.h"(p0: Register, p1: Register, p2: u4) Instruction {
8303 return encodeVdVjUk4(0x73244000, p0, p1, p2);
8304 }
8305
8306 /// Encodes a `vsat.hu` instruction (requires lsx).
8307 pub inline fn @"vsat.hu"(p0: Register, p1: Register, p2: u4) Instruction {
8308 return encodeVdVjUk4(0x73284000, p0, p1, p2);
8309 }
8310
8311 /// Encodes a `vsat.w` instruction (requires lsx).
8312 pub inline fn @"vsat.w"(p0: Register, p1: Register, p2: u5) Instruction {
8313 return encodeVdVjUk5(0x73248000, p0, p1, p2);
8314 }
8315
8316 /// Encodes a `vsat.wu` instruction (requires lsx).
8317 pub inline fn @"vsat.wu"(p0: Register, p1: Register, p2: u5) Instruction {
8318 return encodeVdVjUk5(0x73288000, p0, p1, p2);
8319 }
8320
8321 /// Encodes a `vseq.b` instruction (requires lsx).
8322 pub inline fn @"vseq.b"(p0: Register, p1: Register, p2: Register) Instruction {
8323 return encodeVdVjVk(0x70000000, p0, p1, p2);
8324 }
8325
8326 /// Encodes a `vseq.d` instruction (requires lsx).
8327 pub inline fn @"vseq.d"(p0: Register, p1: Register, p2: Register) Instruction {
8328 return encodeVdVjVk(0x70018000, p0, p1, p2);
8329 }
8330
8331 /// Encodes a `vseq.h` instruction (requires lsx).
8332 pub inline fn @"vseq.h"(p0: Register, p1: Register, p2: Register) Instruction {
8333 return encodeVdVjVk(0x70008000, p0, p1, p2);
8334 }
8335
8336 /// Encodes a `vseq.w` instruction (requires lsx).
8337 pub inline fn @"vseq.w"(p0: Register, p1: Register, p2: Register) Instruction {
8338 return encodeVdVjVk(0x70010000, p0, p1, p2);
8339 }
8340
8341 /// Encodes a `vseqi.b` instruction (requires lsx).
8342 pub inline fn @"vseqi.b"(p0: Register, p1: Register, p2: i5) Instruction {
8343 return encodeVdVjSk5(0x72800000, p0, p1, p2);
8344 }
8345
8346 /// Encodes a `vseqi.d` instruction (requires lsx).
8347 pub inline fn @"vseqi.d"(p0: Register, p1: Register, p2: i5) Instruction {
8348 return encodeVdVjSk5(0x72818000, p0, p1, p2);
8349 }
8350
8351 /// Encodes a `vseqi.h` instruction (requires lsx).
8352 pub inline fn @"vseqi.h"(p0: Register, p1: Register, p2: i5) Instruction {
8353 return encodeVdVjSk5(0x72808000, p0, p1, p2);
8354 }
8355
8356 /// Encodes a `vseqi.w` instruction (requires lsx).
8357 pub inline fn @"vseqi.w"(p0: Register, p1: Register, p2: i5) Instruction {
8358 return encodeVdVjSk5(0x72810000, p0, p1, p2);
8359 }
8360
8361 /// Encodes a `vsetallnez.b` instruction (requires f & lsx).
8362 pub inline fn @"vsetallnez.b"(p0: Register, p1: Register) Instruction {
8363 return encodeCdVj(0x729cb000, p0, p1);
8364 }
8365
8366 /// Encodes a `vsetallnez.d` instruction (requires f & lsx).
8367 pub inline fn @"vsetallnez.d"(p0: Register, p1: Register) Instruction {
8368 return encodeCdVj(0x729cbc00, p0, p1);
8369 }
8370
8371 /// Encodes a `vsetallnez.h` instruction (requires f & lsx).
8372 pub inline fn @"vsetallnez.h"(p0: Register, p1: Register) Instruction {
8373 return encodeCdVj(0x729cb400, p0, p1);
8374 }
8375
8376 /// Encodes a `vsetallnez.w` instruction (requires f & lsx).
8377 pub inline fn @"vsetallnez.w"(p0: Register, p1: Register) Instruction {
8378 return encodeCdVj(0x729cb800, p0, p1);
8379 }
8380
8381 /// Encodes a `vsetanyeqz.b` instruction (requires f & lsx).
8382 pub inline fn @"vsetanyeqz.b"(p0: Register, p1: Register) Instruction {
8383 return encodeCdVj(0x729ca000, p0, p1);
8384 }
8385
8386 /// Encodes a `vsetanyeqz.d` instruction (requires f & lsx).
8387 pub inline fn @"vsetanyeqz.d"(p0: Register, p1: Register) Instruction {
8388 return encodeCdVj(0x729cac00, p0, p1);
8389 }
8390
8391 /// Encodes a `vsetanyeqz.h` instruction (requires f & lsx).
8392 pub inline fn @"vsetanyeqz.h"(p0: Register, p1: Register) Instruction {
8393 return encodeCdVj(0x729ca400, p0, p1);
8394 }
8395
8396 /// Encodes a `vsetanyeqz.w` instruction (requires f & lsx).
8397 pub inline fn @"vsetanyeqz.w"(p0: Register, p1: Register) Instruction {
8398 return encodeCdVj(0x729ca800, p0, p1);
8399 }
8400
8401 /// Encodes a `vseteqz.v` instruction (requires f & lsx).
8402 pub inline fn @"vseteqz.v"(p0: Register, p1: Register) Instruction {
8403 return encodeCdVj(0x729c9800, p0, p1);
8404 }
8405
8406 /// Encodes a `vsetnez.v` instruction (requires f & lsx).
8407 pub inline fn @"vsetnez.v"(p0: Register, p1: Register) Instruction {
8408 return encodeCdVj(0x729c9c00, p0, p1);
8409 }
8410
8411 /// Encodes a `vshuf.b` instruction (requires lsx).
8412 pub inline fn @"vshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
8413 return encodeVdVjVkVa(0x0d500000, p0, p1, p2, p3);
8414 }
8415
8416 /// Encodes a `vshuf.d` instruction (requires lsx).
8417 pub inline fn @"vshuf.d"(p0: Register, p1: Register, p2: Register) Instruction {
8418 return encodeVdVjVk(0x717b8000, p0, p1, p2);
8419 }
8420
8421 /// Encodes a `vshuf.h` instruction (requires lsx).
8422 pub inline fn @"vshuf.h"(p0: Register, p1: Register, p2: Register) Instruction {
8423 return encodeVdVjVk(0x717a8000, p0, p1, p2);
8424 }
8425
8426 /// Encodes a `vshuf.w` instruction (requires lsx).
8427 pub inline fn @"vshuf.w"(p0: Register, p1: Register, p2: Register) Instruction {
8428 return encodeVdVjVk(0x717b0000, p0, p1, p2);
8429 }
8430
8431 /// Encodes a `vshuf4i.b` instruction (requires lsx).
8432 pub inline fn @"vshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction {
8433 return encodeVdVjUk8(0x73900000, p0, p1, p2);
8434 }
8435
8436 /// Encodes a `vshuf4i.d` instruction (requires lsx).
8437 pub inline fn @"vshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction {
8438 return encodeVdVjUk8(0x739c0000, p0, p1, p2);
8439 }
8440
8441 /// Encodes a `vshuf4i.h` instruction (requires lsx).
8442 pub inline fn @"vshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction {
8443 return encodeVdVjUk8(0x73940000, p0, p1, p2);
8444 }
8445
8446 /// Encodes a `vshuf4i.w` instruction (requires lsx).
8447 pub inline fn @"vshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction {
8448 return encodeVdVjUk8(0x73980000, p0, p1, p2);
8449 }
8450
8451 /// Encodes a `vsigncov.b` instruction (requires lsx).
8452 pub inline fn @"vsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction {
8453 return encodeVdVjVk(0x712e0000, p0, p1, p2);
8454 }
8455
8456 /// Encodes a `vsigncov.d` instruction (requires lsx).
8457 pub inline fn @"vsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction {
8458 return encodeVdVjVk(0x712f8000, p0, p1, p2);
8459 }
8460
8461 /// Encodes a `vsigncov.h` instruction (requires lsx).
8462 pub inline fn @"vsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction {
8463 return encodeVdVjVk(0x712e8000, p0, p1, p2);
8464 }
8465
8466 /// Encodes a `vsigncov.w` instruction (requires lsx).
8467 pub inline fn @"vsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction {
8468 return encodeVdVjVk(0x712f0000, p0, p1, p2);
8469 }
8470
8471 /// Encodes a `vsle.b` instruction (requires lsx).
8472 pub inline fn @"vsle.b"(p0: Register, p1: Register, p2: Register) Instruction {
8473 return encodeVdVjVk(0x70020000, p0, p1, p2);
8474 }
8475
8476 /// Encodes a `vsle.bu` instruction (requires lsx).
8477 pub inline fn @"vsle.bu"(p0: Register, p1: Register, p2: Register) Instruction {
8478 return encodeVdVjVk(0x70040000, p0, p1, p2);
8479 }
8480
8481 /// Encodes a `vsle.d` instruction (requires lsx).
8482 pub inline fn @"vsle.d"(p0: Register, p1: Register, p2: Register) Instruction {
8483 return encodeVdVjVk(0x70038000, p0, p1, p2);
8484 }
8485
8486 /// Encodes a `vsle.du` instruction (requires lsx).
8487 pub inline fn @"vsle.du"(p0: Register, p1: Register, p2: Register) Instruction {
8488 return encodeVdVjVk(0x70058000, p0, p1, p2);
8489 }
8490
8491 /// Encodes a `vsle.h` instruction (requires lsx).
8492 pub inline fn @"vsle.h"(p0: Register, p1: Register, p2: Register) Instruction {
8493 return encodeVdVjVk(0x70028000, p0, p1, p2);
8494 }
8495
8496 /// Encodes a `vsle.hu` instruction (requires lsx).
8497 pub inline fn @"vsle.hu"(p0: Register, p1: Register, p2: Register) Instruction {
8498 return encodeVdVjVk(0x70048000, p0, p1, p2);
8499 }
8500
8501 /// Encodes a `vsle.w` instruction (requires lsx).
8502 pub inline fn @"vsle.w"(p0: Register, p1: Register, p2: Register) Instruction {
8503 return encodeVdVjVk(0x70030000, p0, p1, p2);
8504 }
8505
8506 /// Encodes a `vsle.wu` instruction (requires lsx).
8507 pub inline fn @"vsle.wu"(p0: Register, p1: Register, p2: Register) Instruction {
8508 return encodeVdVjVk(0x70050000, p0, p1, p2);
8509 }
8510
8511 /// Encodes a `vslei.b` instruction (requires lsx).
8512 pub inline fn @"vslei.b"(p0: Register, p1: Register, p2: i5) Instruction {
8513 return encodeVdVjSk5(0x72820000, p0, p1, p2);
8514 }
8515
8516 /// Encodes a `vslei.bu` instruction (requires lsx).
8517 pub inline fn @"vslei.bu"(p0: Register, p1: Register, p2: u5) Instruction {
8518 return encodeVdVjUk5(0x72840000, p0, p1, p2);
8519 }
8520
8521 /// Encodes a `vslei.d` instruction (requires lsx).
8522 pub inline fn @"vslei.d"(p0: Register, p1: Register, p2: i5) Instruction {
8523 return encodeVdVjSk5(0x72838000, p0, p1, p2);
8524 }
8525
8526 /// Encodes a `vslei.du` instruction (requires lsx).
8527 pub inline fn @"vslei.du"(p0: Register, p1: Register, p2: u5) Instruction {
8528 return encodeVdVjUk5(0x72858000, p0, p1, p2);
8529 }
8530
8531 /// Encodes a `vslei.h` instruction (requires lsx).
8532 pub inline fn @"vslei.h"(p0: Register, p1: Register, p2: i5) Instruction {
8533 return encodeVdVjSk5(0x72828000, p0, p1, p2);
8534 }
8535
8536 /// Encodes a `vslei.hu` instruction (requires lsx).
8537 pub inline fn @"vslei.hu"(p0: Register, p1: Register, p2: u5) Instruction {
8538 return encodeVdVjUk5(0x72848000, p0, p1, p2);
8539 }
8540
8541 /// Encodes a `vslei.w` instruction (requires lsx).
8542 pub inline fn @"vslei.w"(p0: Register, p1: Register, p2: i5) Instruction {
8543 return encodeVdVjSk5(0x72830000, p0, p1, p2);
8544 }
8545
8546 /// Encodes a `vslei.wu` instruction (requires lsx).
8547 pub inline fn @"vslei.wu"(p0: Register, p1: Register, p2: u5) Instruction {
8548 return encodeVdVjUk5(0x72850000, p0, p1, p2);
8549 }
8550
8551 /// Encodes a `vsll.b` instruction (requires lsx).
8552 pub inline fn @"vsll.b"(p0: Register, p1: Register, p2: Register) Instruction {
8553 return encodeVdVjVk(0x70e80000, p0, p1, p2);
8554 }
8555
8556 /// Encodes a `vsll.d` instruction (requires lsx).
8557 pub inline fn @"vsll.d"(p0: Register, p1: Register, p2: Register) Instruction {
8558 return encodeVdVjVk(0x70e98000, p0, p1, p2);
8559 }
8560
8561 /// Encodes a `vsll.h` instruction (requires lsx).
8562 pub inline fn @"vsll.h"(p0: Register, p1: Register, p2: Register) Instruction {
8563 return encodeVdVjVk(0x70e88000, p0, p1, p2);
8564 }
8565
8566 /// Encodes a `vsll.w` instruction (requires lsx).
8567 pub inline fn @"vsll.w"(p0: Register, p1: Register, p2: Register) Instruction {
8568 return encodeVdVjVk(0x70e90000, p0, p1, p2);
8569 }
8570
8571 /// Encodes a `vslli.b` instruction (requires lsx).
8572 pub inline fn @"vslli.b"(p0: Register, p1: Register, p2: u3) Instruction {
8573 return encodeVdVjUk3(0x732c2000, p0, p1, p2);
8574 }
8575
8576 /// Encodes a `vslli.d` instruction (requires lsx).
8577 pub inline fn @"vslli.d"(p0: Register, p1: Register, p2: u6) Instruction {
8578 return encodeVdVjUk6(0x732d0000, p0, p1, p2);
8579 }
8580
8581 /// Encodes a `vslli.h` instruction (requires lsx).
8582 pub inline fn @"vslli.h"(p0: Register, p1: Register, p2: u4) Instruction {
8583 return encodeVdVjUk4(0x732c4000, p0, p1, p2);
8584 }
8585
8586 /// Encodes a `vslli.w` instruction (requires lsx).
8587 pub inline fn @"vslli.w"(p0: Register, p1: Register, p2: u5) Instruction {
8588 return encodeVdVjUk5(0x732c8000, p0, p1, p2);
8589 }
8590
8591 /// Encodes a `vsllwil.d.w` instruction (requires lsx).
8592 pub inline fn @"vsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction {
8593 return encodeVdVjUk5(0x73088000, p0, p1, p2);
8594 }
8595
8596 /// Encodes a `vsllwil.du.wu` instruction (requires lsx).
8597 pub inline fn @"vsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction {
8598 return encodeVdVjUk5(0x730c8000, p0, p1, p2);
8599 }
8600
8601 /// Encodes a `vsllwil.h.b` instruction (requires lsx).
8602 pub inline fn @"vsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction {
8603 return encodeVdVjUk3(0x73082000, p0, p1, p2);
8604 }
8605
8606 /// Encodes a `vsllwil.hu.bu` instruction (requires lsx).
8607 pub inline fn @"vsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction {
8608 return encodeVdVjUk3(0x730c2000, p0, p1, p2);
8609 }
8610
8611 /// Encodes a `vsllwil.w.h` instruction (requires lsx).
8612 pub inline fn @"vsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction {
8613 return encodeVdVjUk4(0x73084000, p0, p1, p2);
8614 }
8615
8616 /// Encodes a `vsllwil.wu.hu` instruction (requires lsx).
8617 pub inline fn @"vsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction {
8618 return encodeVdVjUk4(0x730c4000, p0, p1, p2);
8619 }
8620
8621 /// Encodes a `vslt.b` instruction (requires lsx).
8622 pub inline fn @"vslt.b"(p0: Register, p1: Register, p2: Register) Instruction {
8623 return encodeVdVjVk(0x70060000, p0, p1, p2);
8624 }
8625
8626 /// Encodes a `vslt.bu` instruction (requires lsx).
8627 pub inline fn @"vslt.bu"(p0: Register, p1: Register, p2: Register) Instruction {
8628 return encodeVdVjVk(0x70080000, p0, p1, p2);
8629 }
8630
8631 /// Encodes a `vslt.d` instruction (requires lsx).
8632 pub inline fn @"vslt.d"(p0: Register, p1: Register, p2: Register) Instruction {
8633 return encodeVdVjVk(0x70078000, p0, p1, p2);
8634 }
8635
8636 /// Encodes a `vslt.du` instruction (requires lsx).
8637 pub inline fn @"vslt.du"(p0: Register, p1: Register, p2: Register) Instruction {
8638 return encodeVdVjVk(0x70098000, p0, p1, p2);
8639 }
8640
8641 /// Encodes a `vslt.h` instruction (requires lsx).
8642 pub inline fn @"vslt.h"(p0: Register, p1: Register, p2: Register) Instruction {
8643 return encodeVdVjVk(0x70068000, p0, p1, p2);
8644 }
8645
8646 /// Encodes a `vslt.hu` instruction (requires lsx).
8647 pub inline fn @"vslt.hu"(p0: Register, p1: Register, p2: Register) Instruction {
8648 return encodeVdVjVk(0x70088000, p0, p1, p2);
8649 }
8650
8651 /// Encodes a `vslt.w` instruction (requires lsx).
8652 pub inline fn @"vslt.w"(p0: Register, p1: Register, p2: Register) Instruction {
8653 return encodeVdVjVk(0x70070000, p0, p1, p2);
8654 }
8655
8656 /// Encodes a `vslt.wu` instruction (requires lsx).
8657 pub inline fn @"vslt.wu"(p0: Register, p1: Register, p2: Register) Instruction {
8658 return encodeVdVjVk(0x70090000, p0, p1, p2);
8659 }
8660
8661 /// Encodes a `vslti.b` instruction (requires lsx).
8662 pub inline fn @"vslti.b"(p0: Register, p1: Register, p2: i5) Instruction {
8663 return encodeVdVjSk5(0x72860000, p0, p1, p2);
8664 }
8665
8666 /// Encodes a `vslti.bu` instruction (requires lsx).
8667 pub inline fn @"vslti.bu"(p0: Register, p1: Register, p2: u5) Instruction {
8668 return encodeVdVjUk5(0x72880000, p0, p1, p2);
8669 }
8670
8671 /// Encodes a `vslti.d` instruction (requires lsx).
8672 pub inline fn @"vslti.d"(p0: Register, p1: Register, p2: i5) Instruction {
8673 return encodeVdVjSk5(0x72878000, p0, p1, p2);
8674 }
8675
8676 /// Encodes a `vslti.du` instruction (requires lsx).
8677 pub inline fn @"vslti.du"(p0: Register, p1: Register, p2: u5) Instruction {
8678 return encodeVdVjUk5(0x72898000, p0, p1, p2);
8679 }
8680
8681 /// Encodes a `vslti.h` instruction (requires lsx).
8682 pub inline fn @"vslti.h"(p0: Register, p1: Register, p2: i5) Instruction {
8683 return encodeVdVjSk5(0x72868000, p0, p1, p2);
8684 }
8685
8686 /// Encodes a `vslti.hu` instruction (requires lsx).
8687 pub inline fn @"vslti.hu"(p0: Register, p1: Register, p2: u5) Instruction {
8688 return encodeVdVjUk5(0x72888000, p0, p1, p2);
8689 }
8690
8691 /// Encodes a `vslti.w` instruction (requires lsx).
8692 pub inline fn @"vslti.w"(p0: Register, p1: Register, p2: i5) Instruction {
8693 return encodeVdVjSk5(0x72870000, p0, p1, p2);
8694 }
8695
8696 /// Encodes a `vslti.wu` instruction (requires lsx).
8697 pub inline fn @"vslti.wu"(p0: Register, p1: Register, p2: u5) Instruction {
8698 return encodeVdVjUk5(0x72890000, p0, p1, p2);
8699 }
8700
8701 /// Encodes a `vsra.b` instruction (requires lsx).
8702 pub inline fn @"vsra.b"(p0: Register, p1: Register, p2: Register) Instruction {
8703 return encodeVdVjVk(0x70ec0000, p0, p1, p2);
8704 }
8705
8706 /// Encodes a `vsra.d` instruction (requires lsx).
8707 pub inline fn @"vsra.d"(p0: Register, p1: Register, p2: Register) Instruction {
8708 return encodeVdVjVk(0x70ed8000, p0, p1, p2);
8709 }
8710
8711 /// Encodes a `vsra.h` instruction (requires lsx).
8712 pub inline fn @"vsra.h"(p0: Register, p1: Register, p2: Register) Instruction {
8713 return encodeVdVjVk(0x70ec8000, p0, p1, p2);
8714 }
8715
8716 /// Encodes a `vsra.w` instruction (requires lsx).
8717 pub inline fn @"vsra.w"(p0: Register, p1: Register, p2: Register) Instruction {
8718 return encodeVdVjVk(0x70ed0000, p0, p1, p2);
8719 }
8720
8721 /// Encodes a `vsrai.b` instruction (requires lsx).
8722 pub inline fn @"vsrai.b"(p0: Register, p1: Register, p2: u3) Instruction {
8723 return encodeVdVjUk3(0x73342000, p0, p1, p2);
8724 }
8725
8726 /// Encodes a `vsrai.d` instruction (requires lsx).
8727 pub inline fn @"vsrai.d"(p0: Register, p1: Register, p2: u6) Instruction {
8728 return encodeVdVjUk6(0x73350000, p0, p1, p2);
8729 }
8730
8731 /// Encodes a `vsrai.h` instruction (requires lsx).
8732 pub inline fn @"vsrai.h"(p0: Register, p1: Register, p2: u4) Instruction {
8733 return encodeVdVjUk4(0x73344000, p0, p1, p2);
8734 }
8735
8736 /// Encodes a `vsrai.w` instruction (requires lsx).
8737 pub inline fn @"vsrai.w"(p0: Register, p1: Register, p2: u5) Instruction {
8738 return encodeVdVjUk5(0x73348000, p0, p1, p2);
8739 }
8740
8741 /// Encodes a `vsran.b.h` instruction (requires lsx).
8742 pub inline fn @"vsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
8743 return encodeVdVjVk(0x70f68000, p0, p1, p2);
8744 }
8745
8746 /// Encodes a `vsran.h.w` instruction (requires lsx).
8747 pub inline fn @"vsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
8748 return encodeVdVjVk(0x70f70000, p0, p1, p2);
8749 }
8750
8751 /// Encodes a `vsran.w.d` instruction (requires lsx).
8752 pub inline fn @"vsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
8753 return encodeVdVjVk(0x70f78000, p0, p1, p2);
8754 }
8755
8756 /// Encodes a `vsrani.b.h` instruction (requires lsx).
8757 pub inline fn @"vsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
8758 return encodeVdVjUk4(0x73584000, p0, p1, p2);
8759 }
8760
8761 /// Encodes a `vsrani.d.q` instruction (requires lsx).
8762 pub inline fn @"vsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
8763 return encodeVdVjUk7(0x735a0000, p0, p1, p2);
8764 }
8765
8766 /// Encodes a `vsrani.h.w` instruction (requires lsx).
8767 pub inline fn @"vsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
8768 return encodeVdVjUk5(0x73588000, p0, p1, p2);
8769 }
8770
8771 /// Encodes a `vsrani.w.d` instruction (requires lsx).
8772 pub inline fn @"vsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
8773 return encodeVdVjUk6(0x73590000, p0, p1, p2);
8774 }
8775
8776 /// Encodes a `vsrar.b` instruction (requires lsx).
8777 pub inline fn @"vsrar.b"(p0: Register, p1: Register, p2: Register) Instruction {
8778 return encodeVdVjVk(0x70f20000, p0, p1, p2);
8779 }
8780
8781 /// Encodes a `vsrar.d` instruction (requires lsx).
8782 pub inline fn @"vsrar.d"(p0: Register, p1: Register, p2: Register) Instruction {
8783 return encodeVdVjVk(0x70f38000, p0, p1, p2);
8784 }
8785
8786 /// Encodes a `vsrar.h` instruction (requires lsx).
8787 pub inline fn @"vsrar.h"(p0: Register, p1: Register, p2: Register) Instruction {
8788 return encodeVdVjVk(0x70f28000, p0, p1, p2);
8789 }
8790
8791 /// Encodes a `vsrar.w` instruction (requires lsx).
8792 pub inline fn @"vsrar.w"(p0: Register, p1: Register, p2: Register) Instruction {
8793 return encodeVdVjVk(0x70f30000, p0, p1, p2);
8794 }
8795
8796 /// Encodes a `vsrari.b` instruction (requires lsx).
8797 pub inline fn @"vsrari.b"(p0: Register, p1: Register, p2: u3) Instruction {
8798 return encodeVdVjUk3(0x72a82000, p0, p1, p2);
8799 }
8800
8801 /// Encodes a `vsrari.d` instruction (requires lsx).
8802 pub inline fn @"vsrari.d"(p0: Register, p1: Register, p2: u6) Instruction {
8803 return encodeVdVjUk6(0x72a90000, p0, p1, p2);
8804 }
8805
8806 /// Encodes a `vsrari.h` instruction (requires lsx).
8807 pub inline fn @"vsrari.h"(p0: Register, p1: Register, p2: u4) Instruction {
8808 return encodeVdVjUk4(0x72a84000, p0, p1, p2);
8809 }
8810
8811 /// Encodes a `vsrari.w` instruction (requires lsx).
8812 pub inline fn @"vsrari.w"(p0: Register, p1: Register, p2: u5) Instruction {
8813 return encodeVdVjUk5(0x72a88000, p0, p1, p2);
8814 }
8815
8816 /// Encodes a `vsrarn.b.h` instruction (requires lsx).
8817 pub inline fn @"vsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
8818 return encodeVdVjVk(0x70fa8000, p0, p1, p2);
8819 }
8820
8821 /// Encodes a `vsrarn.h.w` instruction (requires lsx).
8822 pub inline fn @"vsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
8823 return encodeVdVjVk(0x70fb0000, p0, p1, p2);
8824 }
8825
8826 /// Encodes a `vsrarn.w.d` instruction (requires lsx).
8827 pub inline fn @"vsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
8828 return encodeVdVjVk(0x70fb8000, p0, p1, p2);
8829 }
8830
8831 /// Encodes a `vsrarni.b.h` instruction (requires lsx).
8832 pub inline fn @"vsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
8833 return encodeVdVjUk4(0x735c4000, p0, p1, p2);
8834 }
8835
8836 /// Encodes a `vsrarni.d.q` instruction (requires lsx).
8837 pub inline fn @"vsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
8838 return encodeVdVjUk7(0x735e0000, p0, p1, p2);
8839 }
8840
8841 /// Encodes a `vsrarni.h.w` instruction (requires lsx).
8842 pub inline fn @"vsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
8843 return encodeVdVjUk5(0x735c8000, p0, p1, p2);
8844 }
8845
8846 /// Encodes a `vsrarni.w.d` instruction (requires lsx).
8847 pub inline fn @"vsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
8848 return encodeVdVjUk6(0x735d0000, p0, p1, p2);
8849 }
8850
8851 /// Encodes a `vsrl.b` instruction (requires lsx).
8852 pub inline fn @"vsrl.b"(p0: Register, p1: Register, p2: Register) Instruction {
8853 return encodeVdVjVk(0x70ea0000, p0, p1, p2);
8854 }
8855
8856 /// Encodes a `vsrl.d` instruction (requires lsx).
8857 pub inline fn @"vsrl.d"(p0: Register, p1: Register, p2: Register) Instruction {
8858 return encodeVdVjVk(0x70eb8000, p0, p1, p2);
8859 }
8860
8861 /// Encodes a `vsrl.h` instruction (requires lsx).
8862 pub inline fn @"vsrl.h"(p0: Register, p1: Register, p2: Register) Instruction {
8863 return encodeVdVjVk(0x70ea8000, p0, p1, p2);
8864 }
8865
8866 /// Encodes a `vsrl.w` instruction (requires lsx).
8867 pub inline fn @"vsrl.w"(p0: Register, p1: Register, p2: Register) Instruction {
8868 return encodeVdVjVk(0x70eb0000, p0, p1, p2);
8869 }
8870
8871 /// Encodes a `vsrli.b` instruction (requires lsx).
8872 pub inline fn @"vsrli.b"(p0: Register, p1: Register, p2: u3) Instruction {
8873 return encodeVdVjUk3(0x73302000, p0, p1, p2);
8874 }
8875
8876 /// Encodes a `vsrli.d` instruction (requires lsx).
8877 pub inline fn @"vsrli.d"(p0: Register, p1: Register, p2: u6) Instruction {
8878 return encodeVdVjUk6(0x73310000, p0, p1, p2);
8879 }
8880
8881 /// Encodes a `vsrli.h` instruction (requires lsx).
8882 pub inline fn @"vsrli.h"(p0: Register, p1: Register, p2: u4) Instruction {
8883 return encodeVdVjUk4(0x73304000, p0, p1, p2);
8884 }
8885
8886 /// Encodes a `vsrli.w` instruction (requires lsx).
8887 pub inline fn @"vsrli.w"(p0: Register, p1: Register, p2: u5) Instruction {
8888 return encodeVdVjUk5(0x73308000, p0, p1, p2);
8889 }
8890
8891 /// Encodes a `vsrln.b.h` instruction (requires lsx).
8892 pub inline fn @"vsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
8893 return encodeVdVjVk(0x70f48000, p0, p1, p2);
8894 }
8895
8896 /// Encodes a `vsrln.h.w` instruction (requires lsx).
8897 pub inline fn @"vsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
8898 return encodeVdVjVk(0x70f50000, p0, p1, p2);
8899 }
8900
8901 /// Encodes a `vsrln.w.d` instruction (requires lsx).
8902 pub inline fn @"vsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
8903 return encodeVdVjVk(0x70f58000, p0, p1, p2);
8904 }
8905
8906 /// Encodes a `vsrlni.b.h` instruction (requires lsx).
8907 pub inline fn @"vsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
8908 return encodeVdVjUk4(0x73404000, p0, p1, p2);
8909 }
8910
8911 /// Encodes a `vsrlni.d.q` instruction (requires lsx).
8912 pub inline fn @"vsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
8913 return encodeVdVjUk7(0x73420000, p0, p1, p2);
8914 }
8915
8916 /// Encodes a `vsrlni.h.w` instruction (requires lsx).
8917 pub inline fn @"vsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
8918 return encodeVdVjUk5(0x73408000, p0, p1, p2);
8919 }
8920
8921 /// Encodes a `vsrlni.w.d` instruction (requires lsx).
8922 pub inline fn @"vsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
8923 return encodeVdVjUk6(0x73410000, p0, p1, p2);
8924 }
8925
8926 /// Encodes a `vsrlr.b` instruction (requires lsx).
8927 pub inline fn @"vsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction {
8928 return encodeVdVjVk(0x70f00000, p0, p1, p2);
8929 }
8930
8931 /// Encodes a `vsrlr.d` instruction (requires lsx).
8932 pub inline fn @"vsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction {
8933 return encodeVdVjVk(0x70f18000, p0, p1, p2);
8934 }
8935
8936 /// Encodes a `vsrlr.h` instruction (requires lsx).
8937 pub inline fn @"vsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction {
8938 return encodeVdVjVk(0x70f08000, p0, p1, p2);
8939 }
8940
8941 /// Encodes a `vsrlr.w` instruction (requires lsx).
8942 pub inline fn @"vsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction {
8943 return encodeVdVjVk(0x70f10000, p0, p1, p2);
8944 }
8945
8946 /// Encodes a `vsrlri.b` instruction (requires lsx).
8947 pub inline fn @"vsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction {
8948 return encodeVdVjUk3(0x72a42000, p0, p1, p2);
8949 }
8950
8951 /// Encodes a `vsrlri.d` instruction (requires lsx).
8952 pub inline fn @"vsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction {
8953 return encodeVdVjUk6(0x72a50000, p0, p1, p2);
8954 }
8955
8956 /// Encodes a `vsrlri.h` instruction (requires lsx).
8957 pub inline fn @"vsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction {
8958 return encodeVdVjUk4(0x72a44000, p0, p1, p2);
8959 }
8960
8961 /// Encodes a `vsrlri.w` instruction (requires lsx).
8962 pub inline fn @"vsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction {
8963 return encodeVdVjUk5(0x72a48000, p0, p1, p2);
8964 }
8965
8966 /// Encodes a `vsrlrn.b.h` instruction (requires lsx).
8967 pub inline fn @"vsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
8968 return encodeVdVjVk(0x70f88000, p0, p1, p2);
8969 }
8970
8971 /// Encodes a `vsrlrn.h.w` instruction (requires lsx).
8972 pub inline fn @"vsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
8973 return encodeVdVjVk(0x70f90000, p0, p1, p2);
8974 }
8975
8976 /// Encodes a `vsrlrn.w.d` instruction (requires lsx).
8977 pub inline fn @"vsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
8978 return encodeVdVjVk(0x70f98000, p0, p1, p2);
8979 }
8980
8981 /// Encodes a `vsrlrni.b.h` instruction (requires lsx).
8982 pub inline fn @"vsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
8983 return encodeVdVjUk4(0x73444000, p0, p1, p2);
8984 }
8985
8986 /// Encodes a `vsrlrni.d.q` instruction (requires lsx).
8987 pub inline fn @"vsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
8988 return encodeVdVjUk7(0x73460000, p0, p1, p2);
8989 }
8990
8991 /// Encodes a `vsrlrni.h.w` instruction (requires lsx).
8992 pub inline fn @"vsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
8993 return encodeVdVjUk5(0x73448000, p0, p1, p2);
8994 }
8995
8996 /// Encodes a `vsrlrni.w.d` instruction (requires lsx).
8997 pub inline fn @"vsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
8998 return encodeVdVjUk6(0x73450000, p0, p1, p2);
8999 }
9000
9001 /// Encodes a `vssran.b.h` instruction (requires lsx).
9002 pub inline fn @"vssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
9003 return encodeVdVjVk(0x70fe8000, p0, p1, p2);
9004 }
9005
9006 /// Encodes a `vssran.bu.h` instruction (requires lsx).
9007 pub inline fn @"vssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
9008 return encodeVdVjVk(0x71068000, p0, p1, p2);
9009 }
9010
9011 /// Encodes a `vssran.h.w` instruction (requires lsx).
9012 pub inline fn @"vssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
9013 return encodeVdVjVk(0x70ff0000, p0, p1, p2);
9014 }
9015
9016 /// Encodes a `vssran.hu.w` instruction (requires lsx).
9017 pub inline fn @"vssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
9018 return encodeVdVjVk(0x71070000, p0, p1, p2);
9019 }
9020
9021 /// Encodes a `vssran.w.d` instruction (requires lsx).
9022 pub inline fn @"vssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
9023 return encodeVdVjVk(0x70ff8000, p0, p1, p2);
9024 }
9025
9026 /// Encodes a `vssran.wu.d` instruction (requires lsx).
9027 pub inline fn @"vssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
9028 return encodeVdVjVk(0x71078000, p0, p1, p2);
9029 }
9030
9031 /// Encodes a `vssrani.b.h` instruction (requires lsx).
9032 pub inline fn @"vssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
9033 return encodeVdVjUk4(0x73604000, p0, p1, p2);
9034 }
9035
9036 /// Encodes a `vssrani.bu.h` instruction (requires lsx).
9037 pub inline fn @"vssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
9038 return encodeVdVjUk4(0x73644000, p0, p1, p2);
9039 }
9040
9041 /// Encodes a `vssrani.d.q` instruction (requires lsx).
9042 pub inline fn @"vssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
9043 return encodeVdVjUk7(0x73620000, p0, p1, p2);
9044 }
9045
9046 /// Encodes a `vssrani.du.q` instruction (requires lsx).
9047 pub inline fn @"vssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
9048 return encodeVdVjUk7(0x73660000, p0, p1, p2);
9049 }
9050
9051 /// Encodes a `vssrani.h.w` instruction (requires lsx).
9052 pub inline fn @"vssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
9053 return encodeVdVjUk5(0x73608000, p0, p1, p2);
9054 }
9055
9056 /// Encodes a `vssrani.hu.w` instruction (requires lsx).
9057 pub inline fn @"vssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
9058 return encodeVdVjUk5(0x73648000, p0, p1, p2);
9059 }
9060
9061 /// Encodes a `vssrani.w.d` instruction (requires lsx).
9062 pub inline fn @"vssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
9063 return encodeVdVjUk6(0x73610000, p0, p1, p2);
9064 }
9065
9066 /// Encodes a `vssrani.wu.d` instruction (requires lsx).
9067 pub inline fn @"vssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
9068 return encodeVdVjUk6(0x73650000, p0, p1, p2);
9069 }
9070
9071 /// Encodes a `vssrarn.b.h` instruction (requires lsx).
9072 pub inline fn @"vssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
9073 return encodeVdVjVk(0x71028000, p0, p1, p2);
9074 }
9075
9076 /// Encodes a `vssrarn.bu.h` instruction (requires lsx).
9077 pub inline fn @"vssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
9078 return encodeVdVjVk(0x710a8000, p0, p1, p2);
9079 }
9080
9081 /// Encodes a `vssrarn.h.w` instruction (requires lsx).
9082 pub inline fn @"vssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
9083 return encodeVdVjVk(0x71030000, p0, p1, p2);
9084 }
9085
9086 /// Encodes a `vssrarn.hu.w` instruction (requires lsx).
9087 pub inline fn @"vssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
9088 return encodeVdVjVk(0x710b0000, p0, p1, p2);
9089 }
9090
9091 /// Encodes a `vssrarn.w.d` instruction (requires lsx).
9092 pub inline fn @"vssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
9093 return encodeVdVjVk(0x71038000, p0, p1, p2);
9094 }
9095
9096 /// Encodes a `vssrarn.wu.d` instruction (requires lsx).
9097 pub inline fn @"vssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
9098 return encodeVdVjVk(0x710b8000, p0, p1, p2);
9099 }
9100
9101 /// Encodes a `vssrarni.b.h` instruction (requires lsx).
9102 pub inline fn @"vssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
9103 return encodeVdVjUk4(0x73684000, p0, p1, p2);
9104 }
9105
9106 /// Encodes a `vssrarni.bu.h` instruction (requires lsx).
9107 pub inline fn @"vssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
9108 return encodeVdVjUk4(0x736c4000, p0, p1, p2);
9109 }
9110
9111 /// Encodes a `vssrarni.d.q` instruction (requires lsx).
9112 pub inline fn @"vssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
9113 return encodeVdVjUk7(0x736a0000, p0, p1, p2);
9114 }
9115
9116 /// Encodes a `vssrarni.du.q` instruction (requires lsx).
9117 pub inline fn @"vssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
9118 return encodeVdVjUk7(0x736e0000, p0, p1, p2);
9119 }
9120
9121 /// Encodes a `vssrarni.h.w` instruction (requires lsx).
9122 pub inline fn @"vssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
9123 return encodeVdVjUk5(0x73688000, p0, p1, p2);
9124 }
9125
9126 /// Encodes a `vssrarni.hu.w` instruction (requires lsx).
9127 pub inline fn @"vssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
9128 return encodeVdVjUk5(0x736c8000, p0, p1, p2);
9129 }
9130
9131 /// Encodes a `vssrarni.w.d` instruction (requires lsx).
9132 pub inline fn @"vssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
9133 return encodeVdVjUk6(0x73690000, p0, p1, p2);
9134 }
9135
9136 /// Encodes a `vssrarni.wu.d` instruction (requires lsx).
9137 pub inline fn @"vssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
9138 return encodeVdVjUk6(0x736d0000, p0, p1, p2);
9139 }
9140
9141 /// Encodes a `vssrln.b.h` instruction (requires lsx).
9142 pub inline fn @"vssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
9143 return encodeVdVjVk(0x70fc8000, p0, p1, p2);
9144 }
9145
9146 /// Encodes a `vssrln.bu.h` instruction (requires lsx).
9147 pub inline fn @"vssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
9148 return encodeVdVjVk(0x71048000, p0, p1, p2);
9149 }
9150
9151 /// Encodes a `vssrln.h.w` instruction (requires lsx).
9152 pub inline fn @"vssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
9153 return encodeVdVjVk(0x70fd0000, p0, p1, p2);
9154 }
9155
9156 /// Encodes a `vssrln.hu.w` instruction (requires lsx).
9157 pub inline fn @"vssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
9158 return encodeVdVjVk(0x71050000, p0, p1, p2);
9159 }
9160
9161 /// Encodes a `vssrln.w.d` instruction (requires lsx).
9162 pub inline fn @"vssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
9163 return encodeVdVjVk(0x70fd8000, p0, p1, p2);
9164 }
9165
9166 /// Encodes a `vssrln.wu.d` instruction (requires lsx).
9167 pub inline fn @"vssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
9168 return encodeVdVjVk(0x71058000, p0, p1, p2);
9169 }
9170
9171 /// Encodes a `vssrlni.b.h` instruction (requires lsx).
9172 pub inline fn @"vssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
9173 return encodeVdVjUk4(0x73484000, p0, p1, p2);
9174 }
9175
9176 /// Encodes a `vssrlni.bu.h` instruction (requires lsx).
9177 pub inline fn @"vssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
9178 return encodeVdVjUk4(0x734c4000, p0, p1, p2);
9179 }
9180
9181 /// Encodes a `vssrlni.d.q` instruction (requires lsx).
9182 pub inline fn @"vssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
9183 return encodeVdVjUk7(0x734a0000, p0, p1, p2);
9184 }
9185
9186 /// Encodes a `vssrlni.du.q` instruction (requires lsx).
9187 pub inline fn @"vssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
9188 return encodeVdVjUk7(0x734e0000, p0, p1, p2);
9189 }
9190
9191 /// Encodes a `vssrlni.h.w` instruction (requires lsx).
9192 pub inline fn @"vssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
9193 return encodeVdVjUk5(0x73488000, p0, p1, p2);
9194 }
9195
9196 /// Encodes a `vssrlni.hu.w` instruction (requires lsx).
9197 pub inline fn @"vssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
9198 return encodeVdVjUk5(0x734c8000, p0, p1, p2);
9199 }
9200
9201 /// Encodes a `vssrlni.w.d` instruction (requires lsx).
9202 pub inline fn @"vssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
9203 return encodeVdVjUk6(0x73490000, p0, p1, p2);
9204 }
9205
9206 /// Encodes a `vssrlni.wu.d` instruction (requires lsx).
9207 pub inline fn @"vssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
9208 return encodeVdVjUk6(0x734d0000, p0, p1, p2);
9209 }
9210
9211 /// Encodes a `vssrlrn.b.h` instruction (requires lsx).
9212 pub inline fn @"vssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
9213 return encodeVdVjVk(0x71008000, p0, p1, p2);
9214 }
9215
9216 /// Encodes a `vssrlrn.bu.h` instruction (requires lsx).
9217 pub inline fn @"vssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
9218 return encodeVdVjVk(0x71088000, p0, p1, p2);
9219 }
9220
9221 /// Encodes a `vssrlrn.h.w` instruction (requires lsx).
9222 pub inline fn @"vssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
9223 return encodeVdVjVk(0x71010000, p0, p1, p2);
9224 }
9225
9226 /// Encodes a `vssrlrn.hu.w` instruction (requires lsx).
9227 pub inline fn @"vssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
9228 return encodeVdVjVk(0x71090000, p0, p1, p2);
9229 }
9230
9231 /// Encodes a `vssrlrn.w.d` instruction (requires lsx).
9232 pub inline fn @"vssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
9233 return encodeVdVjVk(0x71018000, p0, p1, p2);
9234 }
9235
9236 /// Encodes a `vssrlrn.wu.d` instruction (requires lsx).
9237 pub inline fn @"vssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
9238 return encodeVdVjVk(0x71098000, p0, p1, p2);
9239 }
9240
9241 /// Encodes a `vssrlrni.b.h` instruction (requires lsx).
9242 pub inline fn @"vssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
9243 return encodeVdVjUk4(0x73504000, p0, p1, p2);
9244 }
9245
9246 /// Encodes a `vssrlrni.bu.h` instruction (requires lsx).
9247 pub inline fn @"vssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
9248 return encodeVdVjUk4(0x73544000, p0, p1, p2);
9249 }
9250
9251 /// Encodes a `vssrlrni.d.q` instruction (requires lsx).
9252 pub inline fn @"vssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
9253 return encodeVdVjUk7(0x73520000, p0, p1, p2);
9254 }
9255
9256 /// Encodes a `vssrlrni.du.q` instruction (requires lsx).
9257 pub inline fn @"vssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
9258 return encodeVdVjUk7(0x73560000, p0, p1, p2);
9259 }
9260
9261 /// Encodes a `vssrlrni.h.w` instruction (requires lsx).
9262 pub inline fn @"vssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
9263 return encodeVdVjUk5(0x73508000, p0, p1, p2);
9264 }
9265
9266 /// Encodes a `vssrlrni.hu.w` instruction (requires lsx).
9267 pub inline fn @"vssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
9268 return encodeVdVjUk5(0x73548000, p0, p1, p2);
9269 }
9270
9271 /// Encodes a `vssrlrni.w.d` instruction (requires lsx).
9272 pub inline fn @"vssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
9273 return encodeVdVjUk6(0x73510000, p0, p1, p2);
9274 }
9275
9276 /// Encodes a `vssrlrni.wu.d` instruction (requires lsx).
9277 pub inline fn @"vssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
9278 return encodeVdVjUk6(0x73550000, p0, p1, p2);
9279 }
9280
9281 /// Encodes a `vssub.b` instruction (requires lsx).
9282 pub inline fn @"vssub.b"(p0: Register, p1: Register, p2: Register) Instruction {
9283 return encodeVdVjVk(0x70480000, p0, p1, p2);
9284 }
9285
9286 /// Encodes a `vssub.bu` instruction (requires lsx).
9287 pub inline fn @"vssub.bu"(p0: Register, p1: Register, p2: Register) Instruction {
9288 return encodeVdVjVk(0x704c0000, p0, p1, p2);
9289 }
9290
9291 /// Encodes a `vssub.d` instruction (requires lsx).
9292 pub inline fn @"vssub.d"(p0: Register, p1: Register, p2: Register) Instruction {
9293 return encodeVdVjVk(0x70498000, p0, p1, p2);
9294 }
9295
9296 /// Encodes a `vssub.du` instruction (requires lsx).
9297 pub inline fn @"vssub.du"(p0: Register, p1: Register, p2: Register) Instruction {
9298 return encodeVdVjVk(0x704d8000, p0, p1, p2);
9299 }
9300
9301 /// Encodes a `vssub.h` instruction (requires lsx).
9302 pub inline fn @"vssub.h"(p0: Register, p1: Register, p2: Register) Instruction {
9303 return encodeVdVjVk(0x70488000, p0, p1, p2);
9304 }
9305
9306 /// Encodes a `vssub.hu` instruction (requires lsx).
9307 pub inline fn @"vssub.hu"(p0: Register, p1: Register, p2: Register) Instruction {
9308 return encodeVdVjVk(0x704c8000, p0, p1, p2);
9309 }
9310
9311 /// Encodes a `vssub.w` instruction (requires lsx).
9312 pub inline fn @"vssub.w"(p0: Register, p1: Register, p2: Register) Instruction {
9313 return encodeVdVjVk(0x70490000, p0, p1, p2);
9314 }
9315
9316 /// Encodes a `vssub.wu` instruction (requires lsx).
9317 pub inline fn @"vssub.wu"(p0: Register, p1: Register, p2: Register) Instruction {
9318 return encodeVdVjVk(0x704d0000, p0, p1, p2);
9319 }
9320
9321 /// Encodes a `vst` instruction (requires lsx).
9322 pub inline fn vst(p0: Register, p1: Register, p2: i12) Instruction {
9323 return encodeVdJSk12(0x2c400000, p0, p1, p2);
9324 }
9325
9326 /// Encodes a `vstelm.b` instruction (requires lsx).
9327 pub inline fn @"vstelm.b"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction {
9328 return encodeVdJSk8Un4(0x31800000, p0, p1, p2, p3);
9329 }
9330
9331 /// Encodes a `vstelm.d` instruction (requires lsx).
9332 pub inline fn @"vstelm.d"(p0: Register, p1: Register, p2: i8, p3: u1) Instruction {
9333 return encodeVdJSk8ps3Un1(0x31100000, p0, p1, p2, p3);
9334 }
9335
9336 /// Encodes a `vstelm.h` instruction (requires lsx).
9337 pub inline fn @"vstelm.h"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
9338 return encodeVdJSk8ps1Un3(0x31400000, p0, p1, p2, p3);
9339 }
9340
9341 /// Encodes a `vstelm.w` instruction (requires lsx).
9342 pub inline fn @"vstelm.w"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
9343 return encodeVdJSk8ps2Un2(0x31200000, p0, p1, p2, p3);
9344 }
9345
9346 /// Encodes a `vstx` instruction (requires lsx).
9347 pub inline fn vstx(p0: Register, p1: Register, p2: Register) Instruction {
9348 return encodeVdJK(0x38440000, p0, p1, p2);
9349 }
9350
9351 /// Encodes a `vsub.b` instruction (requires lsx).
9352 pub inline fn @"vsub.b"(p0: Register, p1: Register, p2: Register) Instruction {
9353 return encodeVdVjVk(0x700c0000, p0, p1, p2);
9354 }
9355
9356 /// Encodes a `vsub.d` instruction (requires lsx).
9357 pub inline fn @"vsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
9358 return encodeVdVjVk(0x700d8000, p0, p1, p2);
9359 }
9360
9361 /// Encodes a `vsub.h` instruction (requires lsx).
9362 pub inline fn @"vsub.h"(p0: Register, p1: Register, p2: Register) Instruction {
9363 return encodeVdVjVk(0x700c8000, p0, p1, p2);
9364 }
9365
9366 /// Encodes a `vsub.q` instruction (requires lsx).
9367 pub inline fn @"vsub.q"(p0: Register, p1: Register, p2: Register) Instruction {
9368 return encodeVdVjVk(0x712d8000, p0, p1, p2);
9369 }
9370
9371 /// Encodes a `vsub.w` instruction (requires lsx).
9372 pub inline fn @"vsub.w"(p0: Register, p1: Register, p2: Register) Instruction {
9373 return encodeVdVjVk(0x700d0000, p0, p1, p2);
9374 }
9375
9376 /// Encodes a `vsubi.bu` instruction (requires lsx).
9377 pub inline fn @"vsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
9378 return encodeVdVjUk5(0x728c0000, p0, p1, p2);
9379 }
9380
9381 /// Encodes a `vsubi.du` instruction (requires lsx).
9382 pub inline fn @"vsubi.du"(p0: Register, p1: Register, p2: u5) Instruction {
9383 return encodeVdVjUk5(0x728d8000, p0, p1, p2);
9384 }
9385
9386 /// Encodes a `vsubi.hu` instruction (requires lsx).
9387 pub inline fn @"vsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
9388 return encodeVdVjUk5(0x728c8000, p0, p1, p2);
9389 }
9390
9391 /// Encodes a `vsubi.wu` instruction (requires lsx).
9392 pub inline fn @"vsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
9393 return encodeVdVjUk5(0x728d0000, p0, p1, p2);
9394 }
9395
9396 /// Encodes a `vsubwev.d.w` instruction (requires lsx).
9397 pub inline fn @"vsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
9398 return encodeVdVjVk(0x70210000, p0, p1, p2);
9399 }
9400
9401 /// Encodes a `vsubwev.d.wu` instruction (requires lsx).
9402 pub inline fn @"vsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
9403 return encodeVdVjVk(0x70310000, p0, p1, p2);
9404 }
9405
9406 /// Encodes a `vsubwev.h.b` instruction (requires lsx).
9407 pub inline fn @"vsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
9408 return encodeVdVjVk(0x70200000, p0, p1, p2);
9409 }
9410
9411 /// Encodes a `vsubwev.h.bu` instruction (requires lsx).
9412 pub inline fn @"vsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
9413 return encodeVdVjVk(0x70300000, p0, p1, p2);
9414 }
9415
9416 /// Encodes a `vsubwev.q.d` instruction (requires lsx).
9417 pub inline fn @"vsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
9418 return encodeVdVjVk(0x70218000, p0, p1, p2);
9419 }
9420
9421 /// Encodes a `vsubwev.q.du` instruction (requires lsx).
9422 pub inline fn @"vsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
9423 return encodeVdVjVk(0x70318000, p0, p1, p2);
9424 }
9425
9426 /// Encodes a `vsubwev.w.h` instruction (requires lsx).
9427 pub inline fn @"vsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
9428 return encodeVdVjVk(0x70208000, p0, p1, p2);
9429 }
9430
9431 /// Encodes a `vsubwev.w.hu` instruction (requires lsx).
9432 pub inline fn @"vsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
9433 return encodeVdVjVk(0x70308000, p0, p1, p2);
9434 }
9435
9436 /// Encodes a `vsubwod.d.w` instruction (requires lsx).
9437 pub inline fn @"vsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
9438 return encodeVdVjVk(0x70250000, p0, p1, p2);
9439 }
9440
9441 /// Encodes a `vsubwod.d.wu` instruction (requires lsx).
9442 pub inline fn @"vsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
9443 return encodeVdVjVk(0x70350000, p0, p1, p2);
9444 }
9445
9446 /// Encodes a `vsubwod.h.b` instruction (requires lsx).
9447 pub inline fn @"vsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
9448 return encodeVdVjVk(0x70240000, p0, p1, p2);
9449 }
9450
9451 /// Encodes a `vsubwod.h.bu` instruction (requires lsx).
9452 pub inline fn @"vsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
9453 return encodeVdVjVk(0x70340000, p0, p1, p2);
9454 }
9455
9456 /// Encodes a `vsubwod.q.d` instruction (requires lsx).
9457 pub inline fn @"vsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
9458 return encodeVdVjVk(0x70258000, p0, p1, p2);
9459 }
9460
9461 /// Encodes a `vsubwod.q.du` instruction (requires lsx).
9462 pub inline fn @"vsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
9463 return encodeVdVjVk(0x70358000, p0, p1, p2);
9464 }
9465
9466 /// Encodes a `vsubwod.w.h` instruction (requires lsx).
9467 pub inline fn @"vsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
9468 return encodeVdVjVk(0x70248000, p0, p1, p2);
9469 }
9470
9471 /// Encodes a `vsubwod.w.hu` instruction (requires lsx).
9472 pub inline fn @"vsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
9473 return encodeVdVjVk(0x70348000, p0, p1, p2);
9474 }
9475
9476 /// Encodes a `vxor.v` instruction (requires lsx).
9477 pub inline fn @"vxor.v"(p0: Register, p1: Register, p2: Register) Instruction {
9478 return encodeVdVjVk(0x71270000, p0, p1, p2);
9479 }
9480
9481 /// Encodes a `vxori.b` instruction (requires lsx).
9482 pub inline fn @"vxori.b"(p0: Register, p1: Register, p2: u8) Instruction {
9483 return encodeVdVjUk8(0x73d80000, p0, p1, p2);
9484 }
9485
9486 /// Encodes a `x86adc.b` instruction (requires 64bit).
9487 pub inline fn @"x86adc.b"(p0: Register, p1: Register) Instruction {
9488 return encodeJK(0x003f000c, p0, p1);
9489 }
9490
9491 /// Encodes a `x86adc.d` instruction (requires 64bit).
9492 pub inline fn @"x86adc.d"(p0: Register, p1: Register) Instruction {
9493 return encodeJK(0x003f000f, p0, p1);
9494 }
9495
9496 /// Encodes a `x86adc.h` instruction (requires 64bit).
9497 pub inline fn @"x86adc.h"(p0: Register, p1: Register) Instruction {
9498 return encodeJK(0x003f000d, p0, p1);
9499 }
9500
9501 /// Encodes a `x86adc.w` instruction (requires 64bit).
9502 pub inline fn @"x86adc.w"(p0: Register, p1: Register) Instruction {
9503 return encodeJK(0x003f000e, p0, p1);
9504 }
9505
9506 /// Encodes a `x86add.b` instruction (requires 64bit).
9507 pub inline fn @"x86add.b"(p0: Register, p1: Register) Instruction {
9508 return encodeJK(0x003f0004, p0, p1);
9509 }
9510
9511 /// Encodes a `x86add.d` instruction (requires 64bit).
9512 pub inline fn @"x86add.d"(p0: Register, p1: Register) Instruction {
9513 return encodeJK(0x003f0007, p0, p1);
9514 }
9515
9516 /// Encodes a `x86add.du` instruction (requires 64bit).
9517 pub inline fn @"x86add.du"(p0: Register, p1: Register) Instruction {
9518 return encodeJK(0x003f0001, p0, p1);
9519 }
9520
9521 /// Encodes a `x86add.h` instruction (requires 64bit).
9522 pub inline fn @"x86add.h"(p0: Register, p1: Register) Instruction {
9523 return encodeJK(0x003f0005, p0, p1);
9524 }
9525
9526 /// Encodes a `x86add.w` instruction (requires 64bit).
9527 pub inline fn @"x86add.w"(p0: Register, p1: Register) Instruction {
9528 return encodeJK(0x003f0006, p0, p1);
9529 }
9530
9531 /// Encodes a `x86add.wu` instruction (requires 64bit).
9532 pub inline fn @"x86add.wu"(p0: Register, p1: Register) Instruction {
9533 return encodeJK(0x003f0000, p0, p1);
9534 }
9535
9536 /// Encodes a `x86and.b` instruction (requires 64bit).
9537 pub inline fn @"x86and.b"(p0: Register, p1: Register) Instruction {
9538 return encodeJK(0x003f8010, p0, p1);
9539 }
9540
9541 /// Encodes a `x86and.d` instruction (requires 64bit).
9542 pub inline fn @"x86and.d"(p0: Register, p1: Register) Instruction {
9543 return encodeJK(0x003f8013, p0, p1);
9544 }
9545
9546 /// Encodes a `x86and.h` instruction (requires 64bit).
9547 pub inline fn @"x86and.h"(p0: Register, p1: Register) Instruction {
9548 return encodeJK(0x003f8011, p0, p1);
9549 }
9550
9551 /// Encodes a `x86and.w` instruction (requires 64bit).
9552 pub inline fn @"x86and.w"(p0: Register, p1: Register) Instruction {
9553 return encodeJK(0x003f8012, p0, p1);
9554 }
9555
9556 /// Encodes a `x86clrtm` instruction (requires 64bit).
9557 pub inline fn x86clrtm() Instruction {
9558 return encodeEMPTY(0x00008028);
9559 }
9560
9561 /// Encodes a `x86dec.b` instruction (requires 64bit).
9562 pub inline fn @"x86dec.b"(p0: Register) Instruction {
9563 return encodeJ(0x00008004, p0);
9564 }
9565
9566 /// Encodes a `x86dec.d` instruction (requires 64bit).
9567 pub inline fn @"x86dec.d"(p0: Register) Instruction {
9568 return encodeJ(0x00008007, p0);
9569 }
9570
9571 /// Encodes a `x86dec.h` instruction (requires 64bit).
9572 pub inline fn @"x86dec.h"(p0: Register) Instruction {
9573 return encodeJ(0x00008005, p0);
9574 }
9575
9576 /// Encodes a `x86dec.w` instruction (requires 64bit).
9577 pub inline fn @"x86dec.w"(p0: Register) Instruction {
9578 return encodeJ(0x00008006, p0);
9579 }
9580
9581 /// Encodes a `x86dectop` instruction (requires 64bit).
9582 pub inline fn x86dectop() Instruction {
9583 return encodeEMPTY(0x00008029);
9584 }
9585
9586 /// Encodes a `x86inc.b` instruction (requires 64bit).
9587 pub inline fn @"x86inc.b"(p0: Register) Instruction {
9588 return encodeJ(0x00008000, p0);
9589 }
9590
9591 /// Encodes a `x86inc.d` instruction (requires 64bit).
9592 pub inline fn @"x86inc.d"(p0: Register) Instruction {
9593 return encodeJ(0x00008003, p0);
9594 }
9595
9596 /// Encodes a `x86inc.h` instruction (requires 64bit).
9597 pub inline fn @"x86inc.h"(p0: Register) Instruction {
9598 return encodeJ(0x00008001, p0);
9599 }
9600
9601 /// Encodes a `x86inc.w` instruction (requires 64bit).
9602 pub inline fn @"x86inc.w"(p0: Register) Instruction {
9603 return encodeJ(0x00008002, p0);
9604 }
9605
9606 /// Encodes a `x86inctop` instruction (requires 64bit).
9607 pub inline fn x86inctop() Instruction {
9608 return encodeEMPTY(0x00008009);
9609 }
9610
9611 /// Encodes a `x86mfflag` instruction (requires 64bit).
9612 pub inline fn x86mfflag(p0: Register, p1: u8) Instruction {
9613 return encodeDUk8(0x005c0000, p0, p1);
9614 }
9615
9616 /// Encodes a `x86mftop` instruction (requires 64bit).
9617 pub inline fn x86mftop(p0: Register) Instruction {
9618 return encodeD(0x00007400, p0);
9619 }
9620
9621 /// Encodes a `x86mtflag` instruction (requires 64bit).
9622 pub inline fn x86mtflag(p0: Register, p1: u8) Instruction {
9623 return encodeDUk8(0x005c0020, p0, p1);
9624 }
9625
9626 /// Encodes a `x86mttop` instruction (requires 64bit).
9627 pub inline fn x86mttop(p0: u3) Instruction {
9628 return encodeUj3(0x00007000, p0);
9629 }
9630
9631 /// Encodes a `x86mul.b` instruction (requires 64bit).
9632 pub inline fn @"x86mul.b"(p0: Register, p1: Register) Instruction {
9633 return encodeJK(0x003e8000, p0, p1);
9634 }
9635
9636 /// Encodes a `x86mul.bu` instruction (requires 64bit).
9637 pub inline fn @"x86mul.bu"(p0: Register, p1: Register) Instruction {
9638 return encodeJK(0x003e8004, p0, p1);
9639 }
9640
9641 /// Encodes a `x86mul.d` instruction (requires 64bit).
9642 pub inline fn @"x86mul.d"(p0: Register, p1: Register) Instruction {
9643 return encodeJK(0x003e8003, p0, p1);
9644 }
9645
9646 /// Encodes a `x86mul.du` instruction (requires 64bit).
9647 pub inline fn @"x86mul.du"(p0: Register, p1: Register) Instruction {
9648 return encodeJK(0x003e8007, p0, p1);
9649 }
9650
9651 /// Encodes a `x86mul.h` instruction (requires 64bit).
9652 pub inline fn @"x86mul.h"(p0: Register, p1: Register) Instruction {
9653 return encodeJK(0x003e8001, p0, p1);
9654 }
9655
9656 /// Encodes a `x86mul.hu` instruction (requires 64bit).
9657 pub inline fn @"x86mul.hu"(p0: Register, p1: Register) Instruction {
9658 return encodeJK(0x003e8005, p0, p1);
9659 }
9660
9661 /// Encodes a `x86mul.w` instruction (requires 64bit).
9662 pub inline fn @"x86mul.w"(p0: Register, p1: Register) Instruction {
9663 return encodeJK(0x003e8002, p0, p1);
9664 }
9665
9666 /// Encodes a `x86mul.wu` instruction (requires 64bit).
9667 pub inline fn @"x86mul.wu"(p0: Register, p1: Register) Instruction {
9668 return encodeJK(0x003e8006, p0, p1);
9669 }
9670
9671 /// Encodes a `x86or.b` instruction (requires 64bit).
9672 pub inline fn @"x86or.b"(p0: Register, p1: Register) Instruction {
9673 return encodeJK(0x003f8014, p0, p1);
9674 }
9675
9676 /// Encodes a `x86or.d` instruction (requires 64bit).
9677 pub inline fn @"x86or.d"(p0: Register, p1: Register) Instruction {
9678 return encodeJK(0x003f8017, p0, p1);
9679 }
9680
9681 /// Encodes a `x86or.h` instruction (requires 64bit).
9682 pub inline fn @"x86or.h"(p0: Register, p1: Register) Instruction {
9683 return encodeJK(0x003f8015, p0, p1);
9684 }
9685
9686 /// Encodes a `x86or.w` instruction (requires 64bit).
9687 pub inline fn @"x86or.w"(p0: Register, p1: Register) Instruction {
9688 return encodeJK(0x003f8016, p0, p1);
9689 }
9690
9691 /// Encodes a `x86rcl.b` instruction (requires 64bit).
9692 pub inline fn @"x86rcl.b"(p0: Register, p1: Register) Instruction {
9693 return encodeJK(0x003f800c, p0, p1);
9694 }
9695
9696 /// Encodes a `x86rcl.d` instruction (requires 64bit).
9697 pub inline fn @"x86rcl.d"(p0: Register, p1: Register) Instruction {
9698 return encodeJK(0x003f800f, p0, p1);
9699 }
9700
9701 /// Encodes a `x86rcl.h` instruction (requires 64bit).
9702 pub inline fn @"x86rcl.h"(p0: Register, p1: Register) Instruction {
9703 return encodeJK(0x003f800d, p0, p1);
9704 }
9705
9706 /// Encodes a `x86rcl.w` instruction (requires 64bit).
9707 pub inline fn @"x86rcl.w"(p0: Register, p1: Register) Instruction {
9708 return encodeJK(0x003f800e, p0, p1);
9709 }
9710
9711 /// Encodes a `x86rcli.b` instruction (requires 64bit).
9712 pub inline fn @"x86rcli.b"(p0: Register, p1: u3) Instruction {
9713 return encodeJUk3(0x00542018, p0, p1);
9714 }
9715
9716 /// Encodes a `x86rcli.d` instruction (requires 64bit).
9717 pub inline fn @"x86rcli.d"(p0: Register, p1: u6) Instruction {
9718 return encodeJUk6(0x0055001b, p0, p1);
9719 }
9720
9721 /// Encodes a `x86rcli.h` instruction (requires 64bit).
9722 pub inline fn @"x86rcli.h"(p0: Register, p1: u4) Instruction {
9723 return encodeJUk4(0x00544019, p0, p1);
9724 }
9725
9726 /// Encodes a `x86rcli.w` instruction (requires 64bit).
9727 pub inline fn @"x86rcli.w"(p0: Register, p1: u5) Instruction {
9728 return encodeJUk5(0x0054801a, p0, p1);
9729 }
9730
9731 /// Encodes a `x86rcr.b` instruction (requires 64bit).
9732 pub inline fn @"x86rcr.b"(p0: Register, p1: Register) Instruction {
9733 return encodeJK(0x003f8008, p0, p1);
9734 }
9735
9736 /// Encodes a `x86rcr.d` instruction (requires 64bit).
9737 pub inline fn @"x86rcr.d"(p0: Register, p1: Register) Instruction {
9738 return encodeJK(0x003f800b, p0, p1);
9739 }
9740
9741 /// Encodes a `x86rcr.h` instruction (requires 64bit).
9742 pub inline fn @"x86rcr.h"(p0: Register, p1: Register) Instruction {
9743 return encodeJK(0x003f8009, p0, p1);
9744 }
9745
9746 /// Encodes a `x86rcr.w` instruction (requires 64bit).
9747 pub inline fn @"x86rcr.w"(p0: Register, p1: Register) Instruction {
9748 return encodeJK(0x003f800a, p0, p1);
9749 }
9750
9751 /// Encodes a `x86rcri.b` instruction (requires 64bit).
9752 pub inline fn @"x86rcri.b"(p0: Register, p1: u3) Instruction {
9753 return encodeJUk3(0x00542010, p0, p1);
9754 }
9755
9756 /// Encodes a `x86rcri.d` instruction (requires 64bit).
9757 pub inline fn @"x86rcri.d"(p0: Register, p1: u6) Instruction {
9758 return encodeJUk6(0x00550013, p0, p1);
9759 }
9760
9761 /// Encodes a `x86rcri.h` instruction (requires 64bit).
9762 pub inline fn @"x86rcri.h"(p0: Register, p1: u4) Instruction {
9763 return encodeJUk4(0x00544011, p0, p1);
9764 }
9765
9766 /// Encodes a `x86rcri.w` instruction (requires 64bit).
9767 pub inline fn @"x86rcri.w"(p0: Register, p1: u5) Instruction {
9768 return encodeJUk5(0x00548012, p0, p1);
9769 }
9770
9771 /// Encodes a `x86rotl.b` instruction (requires 64bit).
9772 pub inline fn @"x86rotl.b"(p0: Register, p1: Register) Instruction {
9773 return encodeJK(0x003f8004, p0, p1);
9774 }
9775
9776 /// Encodes a `x86rotl.d` instruction (requires 64bit).
9777 pub inline fn @"x86rotl.d"(p0: Register, p1: Register) Instruction {
9778 return encodeJK(0x003f8007, p0, p1);
9779 }
9780
9781 /// Encodes a `x86rotl.h` instruction (requires 64bit).
9782 pub inline fn @"x86rotl.h"(p0: Register, p1: Register) Instruction {
9783 return encodeJK(0x003f8005, p0, p1);
9784 }
9785
9786 /// Encodes a `x86rotl.w` instruction (requires 64bit).
9787 pub inline fn @"x86rotl.w"(p0: Register, p1: Register) Instruction {
9788 return encodeJK(0x003f8006, p0, p1);
9789 }
9790
9791 /// Encodes a `x86rotli.b` instruction (requires 64bit).
9792 pub inline fn @"x86rotli.b"(p0: Register, p1: u3) Instruction {
9793 return encodeJUk3(0x00542014, p0, p1);
9794 }
9795
9796 /// Encodes a `x86rotli.d` instruction (requires 64bit).
9797 pub inline fn @"x86rotli.d"(p0: Register, p1: u6) Instruction {
9798 return encodeJUk6(0x00550017, p0, p1);
9799 }
9800
9801 /// Encodes a `x86rotli.h` instruction (requires 64bit).
9802 pub inline fn @"x86rotli.h"(p0: Register, p1: u4) Instruction {
9803 return encodeJUk4(0x00544015, p0, p1);
9804 }
9805
9806 /// Encodes a `x86rotli.w` instruction (requires 64bit).
9807 pub inline fn @"x86rotli.w"(p0: Register, p1: u5) Instruction {
9808 return encodeJUk5(0x00548016, p0, p1);
9809 }
9810
9811 /// Encodes a `x86rotr.b` instruction (requires 64bit).
9812 pub inline fn @"x86rotr.b"(p0: Register, p1: Register) Instruction {
9813 return encodeJK(0x003f8000, p0, p1);
9814 }
9815
9816 /// Encodes a `x86rotr.d` instruction (requires 64bit).
9817 pub inline fn @"x86rotr.d"(p0: Register, p1: Register) Instruction {
9818 return encodeJK(0x003f8002, p0, p1);
9819 }
9820
9821 /// Encodes a `x86rotr.h` instruction (requires 64bit).
9822 pub inline fn @"x86rotr.h"(p0: Register, p1: Register) Instruction {
9823 return encodeJK(0x003f8001, p0, p1);
9824 }
9825
9826 /// Encodes a `x86rotr.w` instruction (requires 64bit).
9827 pub inline fn @"x86rotr.w"(p0: Register, p1: Register) Instruction {
9828 return encodeJK(0x003f8003, p0, p1);
9829 }
9830
9831 /// Encodes a `x86rotri.b` instruction (requires 64bit).
9832 pub inline fn @"x86rotri.b"(p0: Register, p1: u3) Instruction {
9833 return encodeJUk3(0x0054200c, p0, p1);
9834 }
9835
9836 /// Encodes a `x86rotri.d` instruction (requires 64bit).
9837 pub inline fn @"x86rotri.d"(p0: Register, p1: u6) Instruction {
9838 return encodeJUk6(0x0055000f, p0, p1);
9839 }
9840
9841 /// Encodes a `x86rotri.h` instruction (requires 64bit).
9842 pub inline fn @"x86rotri.h"(p0: Register, p1: u4) Instruction {
9843 return encodeJUk4(0x0054400d, p0, p1);
9844 }
9845
9846 /// Encodes a `x86rotri.w` instruction (requires 64bit).
9847 pub inline fn @"x86rotri.w"(p0: Register, p1: u5) Instruction {
9848 return encodeJUk5(0x0054800e, p0, p1);
9849 }
9850
9851 /// Encodes a `x86sbc.b` instruction (requires 64bit).
9852 pub inline fn @"x86sbc.b"(p0: Register, p1: Register) Instruction {
9853 return encodeJK(0x003f0010, p0, p1);
9854 }
9855
9856 /// Encodes a `x86sbc.d` instruction (requires 64bit).
9857 pub inline fn @"x86sbc.d"(p0: Register, p1: Register) Instruction {
9858 return encodeJK(0x003f0013, p0, p1);
9859 }
9860
9861 /// Encodes a `x86sbc.h` instruction (requires 64bit).
9862 pub inline fn @"x86sbc.h"(p0: Register, p1: Register) Instruction {
9863 return encodeJK(0x003f0011, p0, p1);
9864 }
9865
9866 /// Encodes a `x86sbc.w` instruction (requires 64bit).
9867 pub inline fn @"x86sbc.w"(p0: Register, p1: Register) Instruction {
9868 return encodeJK(0x003f0012, p0, p1);
9869 }
9870
9871 /// Encodes a `x86setj` instruction (requires 64bit).
9872 pub inline fn x86setj(p0: Register, p1: u4) Instruction {
9873 return encodeDUk4(0x00368000, p0, p1);
9874 }
9875
9876 /// Encodes a `x86setloope` instruction (requires 64bit).
9877 pub inline fn x86setloope(p0: Register, p1: Register) Instruction {
9878 return encodeDJ(0x00007800, p0, p1);
9879 }
9880
9881 /// Encodes a `x86setloopne` instruction (requires 64bit).
9882 pub inline fn x86setloopne(p0: Register, p1: Register) Instruction {
9883 return encodeDJ(0x00007c00, p0, p1);
9884 }
9885
9886 /// Encodes a `x86settag` instruction (requires 64bit).
9887 pub inline fn x86settag(p0: Register, p1: u5, p2: u8) Instruction {
9888 return encodeDUj5Uk8(0x00580000, p0, p1, p2);
9889 }
9890
9891 /// Encodes a `x86settm` instruction (requires 64bit).
9892 pub inline fn x86settm() Instruction {
9893 return encodeEMPTY(0x00008008);
9894 }
9895
9896 /// Encodes a `x86sll.b` instruction (requires 64bit).
9897 pub inline fn @"x86sll.b"(p0: Register, p1: Register) Instruction {
9898 return encodeJK(0x003f0014, p0, p1);
9899 }
9900
9901 /// Encodes a `x86sll.d` instruction (requires 64bit).
9902 pub inline fn @"x86sll.d"(p0: Register, p1: Register) Instruction {
9903 return encodeJK(0x003f0017, p0, p1);
9904 }
9905
9906 /// Encodes a `x86sll.h` instruction (requires 64bit).
9907 pub inline fn @"x86sll.h"(p0: Register, p1: Register) Instruction {
9908 return encodeJK(0x003f0015, p0, p1);
9909 }
9910
9911 /// Encodes a `x86sll.w` instruction (requires 64bit).
9912 pub inline fn @"x86sll.w"(p0: Register, p1: Register) Instruction {
9913 return encodeJK(0x003f0016, p0, p1);
9914 }
9915
9916 /// Encodes a `x86slli.b` instruction (requires 64bit).
9917 pub inline fn @"x86slli.b"(p0: Register, p1: u3) Instruction {
9918 return encodeJUk3(0x00542000, p0, p1);
9919 }
9920
9921 /// Encodes a `x86slli.d` instruction (requires 64bit).
9922 pub inline fn @"x86slli.d"(p0: Register, p1: u6) Instruction {
9923 return encodeJUk6(0x00550003, p0, p1);
9924 }
9925
9926 /// Encodes a `x86slli.h` instruction (requires 64bit).
9927 pub inline fn @"x86slli.h"(p0: Register, p1: u4) Instruction {
9928 return encodeJUk4(0x00544001, p0, p1);
9929 }
9930
9931 /// Encodes a `x86slli.w` instruction (requires 64bit).
9932 pub inline fn @"x86slli.w"(p0: Register, p1: u5) Instruction {
9933 return encodeJUk5(0x00548002, p0, p1);
9934 }
9935
9936 /// Encodes a `x86sra.b` instruction (requires 64bit).
9937 pub inline fn @"x86sra.b"(p0: Register, p1: Register) Instruction {
9938 return encodeJK(0x003f001c, p0, p1);
9939 }
9940
9941 /// Encodes a `x86sra.d` instruction (requires 64bit).
9942 pub inline fn @"x86sra.d"(p0: Register, p1: Register) Instruction {
9943 return encodeJK(0x003f001f, p0, p1);
9944 }
9945
9946 /// Encodes a `x86sra.h` instruction (requires 64bit).
9947 pub inline fn @"x86sra.h"(p0: Register, p1: Register) Instruction {
9948 return encodeJK(0x003f001d, p0, p1);
9949 }
9950
9951 /// Encodes a `x86sra.w` instruction (requires 64bit).
9952 pub inline fn @"x86sra.w"(p0: Register, p1: Register) Instruction {
9953 return encodeJK(0x003f001e, p0, p1);
9954 }
9955
9956 /// Encodes a `x86srai.b` instruction (requires 64bit).
9957 pub inline fn @"x86srai.b"(p0: Register, p1: u3) Instruction {
9958 return encodeJUk3(0x00542008, p0, p1);
9959 }
9960
9961 /// Encodes a `x86srai.d` instruction (requires 64bit).
9962 pub inline fn @"x86srai.d"(p0: Register, p1: u6) Instruction {
9963 return encodeJUk6(0x0055000b, p0, p1);
9964 }
9965
9966 /// Encodes a `x86srai.h` instruction (requires 64bit).
9967 pub inline fn @"x86srai.h"(p0: Register, p1: u4) Instruction {
9968 return encodeJUk4(0x00544009, p0, p1);
9969 }
9970
9971 /// Encodes a `x86srai.w` instruction (requires 64bit).
9972 pub inline fn @"x86srai.w"(p0: Register, p1: u5) Instruction {
9973 return encodeJUk5(0x0054800a, p0, p1);
9974 }
9975
9976 /// Encodes a `x86srl.b` instruction (requires 64bit).
9977 pub inline fn @"x86srl.b"(p0: Register, p1: Register) Instruction {
9978 return encodeJK(0x003f0018, p0, p1);
9979 }
9980
9981 /// Encodes a `x86srl.d` instruction (requires 64bit).
9982 pub inline fn @"x86srl.d"(p0: Register, p1: Register) Instruction {
9983 return encodeJK(0x003f001b, p0, p1);
9984 }
9985
9986 /// Encodes a `x86srl.h` instruction (requires 64bit).
9987 pub inline fn @"x86srl.h"(p0: Register, p1: Register) Instruction {
9988 return encodeJK(0x003f0019, p0, p1);
9989 }
9990
9991 /// Encodes a `x86srl.w` instruction (requires 64bit).
9992 pub inline fn @"x86srl.w"(p0: Register, p1: Register) Instruction {
9993 return encodeJK(0x003f001a, p0, p1);
9994 }
9995
9996 /// Encodes a `x86srli.b` instruction (requires 64bit).
9997 pub inline fn @"x86srli.b"(p0: Register, p1: u3) Instruction {
9998 return encodeJUk3(0x00542004, p0, p1);
9999 }
10000
10001 /// Encodes a `x86srli.d` instruction (requires 64bit).
10002 pub inline fn @"x86srli.d"(p0: Register, p1: u6) Instruction {
10003 return encodeJUk6(0x00550007, p0, p1);
10004 }
10005
10006 /// Encodes a `x86srli.h` instruction (requires 64bit).
10007 pub inline fn @"x86srli.h"(p0: Register, p1: u4) Instruction {
10008 return encodeJUk4(0x00544005, p0, p1);
10009 }
10010
10011 /// Encodes a `x86srli.w` instruction (requires 64bit).
10012 pub inline fn @"x86srli.w"(p0: Register, p1: u5) Instruction {
10013 return encodeJUk5(0x00548006, p0, p1);
10014 }
10015
10016 /// Encodes a `x86sub.b` instruction (requires 64bit).
10017 pub inline fn @"x86sub.b"(p0: Register, p1: Register) Instruction {
10018 return encodeJK(0x003f0008, p0, p1);
10019 }
10020
10021 /// Encodes a `x86sub.d` instruction (requires 64bit).
10022 pub inline fn @"x86sub.d"(p0: Register, p1: Register) Instruction {
10023 return encodeJK(0x003f000b, p0, p1);
10024 }
10025
10026 /// Encodes a `x86sub.du` instruction (requires 64bit).
10027 pub inline fn @"x86sub.du"(p0: Register, p1: Register) Instruction {
10028 return encodeJK(0x003f0003, p0, p1);
10029 }
10030
10031 /// Encodes a `x86sub.h` instruction (requires 64bit).
10032 pub inline fn @"x86sub.h"(p0: Register, p1: Register) Instruction {
10033 return encodeJK(0x003f0009, p0, p1);
10034 }
10035
10036 /// Encodes a `x86sub.w` instruction (requires 64bit).
10037 pub inline fn @"x86sub.w"(p0: Register, p1: Register) Instruction {
10038 return encodeJK(0x003f000a, p0, p1);
10039 }
10040
10041 /// Encodes a `x86sub.wu` instruction (requires 64bit).
10042 pub inline fn @"x86sub.wu"(p0: Register, p1: Register) Instruction {
10043 return encodeJK(0x003f0002, p0, p1);
10044 }
10045
10046 /// Encodes a `x86xor.b` instruction (requires 64bit).
10047 pub inline fn @"x86xor.b"(p0: Register, p1: Register) Instruction {
10048 return encodeJK(0x003f8018, p0, p1);
10049 }
10050
10051 /// Encodes a `x86xor.d` instruction (requires 64bit).
10052 pub inline fn @"x86xor.d"(p0: Register, p1: Register) Instruction {
10053 return encodeJK(0x003f801b, p0, p1);
10054 }
10055
10056 /// Encodes a `x86xor.h` instruction (requires 64bit).
10057 pub inline fn @"x86xor.h"(p0: Register, p1: Register) Instruction {
10058 return encodeJK(0x003f8019, p0, p1);
10059 }
10060
10061 /// Encodes a `x86xor.w` instruction (requires 64bit).
10062 pub inline fn @"x86xor.w"(p0: Register, p1: Register) Instruction {
10063 return encodeJK(0x003f801a, p0, p1);
10064 }
10065
10066 /// Encodes a `xor` instruction (requires 32bit).
10067 pub inline fn xor(p0: Register, p1: Register, p2: Register) Instruction {
10068 return encodeDJK(0x00158000, p0, p1, p2);
10069 }
10070
10071 /// Encodes a `xori` instruction (requires 32bit).
10072 pub inline fn xori(p0: Register, p1: Register, p2: u12) Instruction {
10073 return encodeDJUk12(0x03c00000, p0, p1, p2);
10074 }
10075
10076 /// Encodes a `xvabsd.b` instruction (requires lasx).
10077 pub inline fn @"xvabsd.b"(p0: Register, p1: Register, p2: Register) Instruction {
10078 return encodeXdXjXk(0x74600000, p0, p1, p2);
10079 }
10080
10081 /// Encodes a `xvabsd.bu` instruction (requires lasx).
10082 pub inline fn @"xvabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10083 return encodeXdXjXk(0x74620000, p0, p1, p2);
10084 }
10085
10086 /// Encodes a `xvabsd.d` instruction (requires lasx).
10087 pub inline fn @"xvabsd.d"(p0: Register, p1: Register, p2: Register) Instruction {
10088 return encodeXdXjXk(0x74618000, p0, p1, p2);
10089 }
10090
10091 /// Encodes a `xvabsd.du` instruction (requires lasx).
10092 pub inline fn @"xvabsd.du"(p0: Register, p1: Register, p2: Register) Instruction {
10093 return encodeXdXjXk(0x74638000, p0, p1, p2);
10094 }
10095
10096 /// Encodes a `xvabsd.h` instruction (requires lasx).
10097 pub inline fn @"xvabsd.h"(p0: Register, p1: Register, p2: Register) Instruction {
10098 return encodeXdXjXk(0x74608000, p0, p1, p2);
10099 }
10100
10101 /// Encodes a `xvabsd.hu` instruction (requires lasx).
10102 pub inline fn @"xvabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10103 return encodeXdXjXk(0x74628000, p0, p1, p2);
10104 }
10105
10106 /// Encodes a `xvabsd.w` instruction (requires lasx).
10107 pub inline fn @"xvabsd.w"(p0: Register, p1: Register, p2: Register) Instruction {
10108 return encodeXdXjXk(0x74610000, p0, p1, p2);
10109 }
10110
10111 /// Encodes a `xvabsd.wu` instruction (requires lasx).
10112 pub inline fn @"xvabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10113 return encodeXdXjXk(0x74630000, p0, p1, p2);
10114 }
10115
10116 /// Encodes a `xvadd.b` instruction (requires lasx).
10117 pub inline fn @"xvadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
10118 return encodeXdXjXk(0x740a0000, p0, p1, p2);
10119 }
10120
10121 /// Encodes a `xvadd.d` instruction (requires lasx).
10122 pub inline fn @"xvadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
10123 return encodeXdXjXk(0x740b8000, p0, p1, p2);
10124 }
10125
10126 /// Encodes a `xvadd.h` instruction (requires lasx).
10127 pub inline fn @"xvadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
10128 return encodeXdXjXk(0x740a8000, p0, p1, p2);
10129 }
10130
10131 /// Encodes a `xvadd.q` instruction (requires lasx).
10132 pub inline fn @"xvadd.q"(p0: Register, p1: Register, p2: Register) Instruction {
10133 return encodeXdXjXk(0x752d0000, p0, p1, p2);
10134 }
10135
10136 /// Encodes a `xvadd.w` instruction (requires lasx).
10137 pub inline fn @"xvadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
10138 return encodeXdXjXk(0x740b0000, p0, p1, p2);
10139 }
10140
10141 /// Encodes a `xvadda.b` instruction (requires lasx).
10142 pub inline fn @"xvadda.b"(p0: Register, p1: Register, p2: Register) Instruction {
10143 return encodeXdXjXk(0x745c0000, p0, p1, p2);
10144 }
10145
10146 /// Encodes a `xvadda.d` instruction (requires lasx).
10147 pub inline fn @"xvadda.d"(p0: Register, p1: Register, p2: Register) Instruction {
10148 return encodeXdXjXk(0x745d8000, p0, p1, p2);
10149 }
10150
10151 /// Encodes a `xvadda.h` instruction (requires lasx).
10152 pub inline fn @"xvadda.h"(p0: Register, p1: Register, p2: Register) Instruction {
10153 return encodeXdXjXk(0x745c8000, p0, p1, p2);
10154 }
10155
10156 /// Encodes a `xvadda.w` instruction (requires lasx).
10157 pub inline fn @"xvadda.w"(p0: Register, p1: Register, p2: Register) Instruction {
10158 return encodeXdXjXk(0x745d0000, p0, p1, p2);
10159 }
10160
10161 /// Encodes a `xvaddi.bu` instruction (requires lasx).
10162 pub inline fn @"xvaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
10163 return encodeXdXjUk5(0x768a0000, p0, p1, p2);
10164 }
10165
10166 /// Encodes a `xvaddi.du` instruction (requires lasx).
10167 pub inline fn @"xvaddi.du"(p0: Register, p1: Register, p2: u5) Instruction {
10168 return encodeXdXjUk5(0x768b8000, p0, p1, p2);
10169 }
10170
10171 /// Encodes a `xvaddi.hu` instruction (requires lasx).
10172 pub inline fn @"xvaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
10173 return encodeXdXjUk5(0x768a8000, p0, p1, p2);
10174 }
10175
10176 /// Encodes a `xvaddi.wu` instruction (requires lasx).
10177 pub inline fn @"xvaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
10178 return encodeXdXjUk5(0x768b0000, p0, p1, p2);
10179 }
10180
10181 /// Encodes a `xvaddwev.d.w` instruction (requires lasx).
10182 pub inline fn @"xvaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
10183 return encodeXdXjXk(0x741f0000, p0, p1, p2);
10184 }
10185
10186 /// Encodes a `xvaddwev.d.wu` instruction (requires lasx).
10187 pub inline fn @"xvaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10188 return encodeXdXjXk(0x742f0000, p0, p1, p2);
10189 }
10190
10191 /// Encodes a `xvaddwev.d.wu.w` instruction (requires lasx).
10192 pub inline fn @"xvaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
10193 return encodeXdXjXk(0x743f0000, p0, p1, p2);
10194 }
10195
10196 /// Encodes a `xvaddwev.h.b` instruction (requires lasx).
10197 pub inline fn @"xvaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
10198 return encodeXdXjXk(0x741e0000, p0, p1, p2);
10199 }
10200
10201 /// Encodes a `xvaddwev.h.bu` instruction (requires lasx).
10202 pub inline fn @"xvaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10203 return encodeXdXjXk(0x742e0000, p0, p1, p2);
10204 }
10205
10206 /// Encodes a `xvaddwev.h.bu.b` instruction (requires lasx).
10207 pub inline fn @"xvaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
10208 return encodeXdXjXk(0x743e0000, p0, p1, p2);
10209 }
10210
10211 /// Encodes a `xvaddwev.q.d` instruction (requires lasx).
10212 pub inline fn @"xvaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
10213 return encodeXdXjXk(0x741f8000, p0, p1, p2);
10214 }
10215
10216 /// Encodes a `xvaddwev.q.du` instruction (requires lasx).
10217 pub inline fn @"xvaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
10218 return encodeXdXjXk(0x742f8000, p0, p1, p2);
10219 }
10220
10221 /// Encodes a `xvaddwev.q.du.d` instruction (requires lasx).
10222 pub inline fn @"xvaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
10223 return encodeXdXjXk(0x743f8000, p0, p1, p2);
10224 }
10225
10226 /// Encodes a `xvaddwev.w.h` instruction (requires lasx).
10227 pub inline fn @"xvaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
10228 return encodeXdXjXk(0x741e8000, p0, p1, p2);
10229 }
10230
10231 /// Encodes a `xvaddwev.w.hu` instruction (requires lasx).
10232 pub inline fn @"xvaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10233 return encodeXdXjXk(0x742e8000, p0, p1, p2);
10234 }
10235
10236 /// Encodes a `xvaddwev.w.hu.h` instruction (requires lasx).
10237 pub inline fn @"xvaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
10238 return encodeXdXjXk(0x743e8000, p0, p1, p2);
10239 }
10240
10241 /// Encodes a `xvaddwod.d.w` instruction (requires lasx).
10242 pub inline fn @"xvaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
10243 return encodeXdXjXk(0x74230000, p0, p1, p2);
10244 }
10245
10246 /// Encodes a `xvaddwod.d.wu` instruction (requires lasx).
10247 pub inline fn @"xvaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10248 return encodeXdXjXk(0x74330000, p0, p1, p2);
10249 }
10250
10251 /// Encodes a `xvaddwod.d.wu.w` instruction (requires lasx).
10252 pub inline fn @"xvaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
10253 return encodeXdXjXk(0x74410000, p0, p1, p2);
10254 }
10255
10256 /// Encodes a `xvaddwod.h.b` instruction (requires lasx).
10257 pub inline fn @"xvaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
10258 return encodeXdXjXk(0x74220000, p0, p1, p2);
10259 }
10260
10261 /// Encodes a `xvaddwod.h.bu` instruction (requires lasx).
10262 pub inline fn @"xvaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10263 return encodeXdXjXk(0x74320000, p0, p1, p2);
10264 }
10265
10266 /// Encodes a `xvaddwod.h.bu.b` instruction (requires lasx).
10267 pub inline fn @"xvaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
10268 return encodeXdXjXk(0x74400000, p0, p1, p2);
10269 }
10270
10271 /// Encodes a `xvaddwod.q.d` instruction (requires lasx).
10272 pub inline fn @"xvaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
10273 return encodeXdXjXk(0x74238000, p0, p1, p2);
10274 }
10275
10276 /// Encodes a `xvaddwod.q.du` instruction (requires lasx).
10277 pub inline fn @"xvaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
10278 return encodeXdXjXk(0x74338000, p0, p1, p2);
10279 }
10280
10281 /// Encodes a `xvaddwod.q.du.d` instruction (requires lasx).
10282 pub inline fn @"xvaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
10283 return encodeXdXjXk(0x74418000, p0, p1, p2);
10284 }
10285
10286 /// Encodes a `xvaddwod.w.h` instruction (requires lasx).
10287 pub inline fn @"xvaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
10288 return encodeXdXjXk(0x74228000, p0, p1, p2);
10289 }
10290
10291 /// Encodes a `xvaddwod.w.hu` instruction (requires lasx).
10292 pub inline fn @"xvaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10293 return encodeXdXjXk(0x74328000, p0, p1, p2);
10294 }
10295
10296 /// Encodes a `xvaddwod.w.hu.h` instruction (requires lasx).
10297 pub inline fn @"xvaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
10298 return encodeXdXjXk(0x74408000, p0, p1, p2);
10299 }
10300
10301 /// Encodes a `xvand.v` instruction (requires lasx).
10302 pub inline fn @"xvand.v"(p0: Register, p1: Register, p2: Register) Instruction {
10303 return encodeXdXjXk(0x75260000, p0, p1, p2);
10304 }
10305
10306 /// Encodes a `xvandi.b` instruction (requires lasx).
10307 pub inline fn @"xvandi.b"(p0: Register, p1: Register, p2: u8) Instruction {
10308 return encodeXdXjUk8(0x77d00000, p0, p1, p2);
10309 }
10310
10311 /// Encodes a `xvandn.v` instruction (requires lasx).
10312 pub inline fn @"xvandn.v"(p0: Register, p1: Register, p2: Register) Instruction {
10313 return encodeXdXjXk(0x75280000, p0, p1, p2);
10314 }
10315
10316 /// Encodes a `xvavg.b` instruction (requires lasx).
10317 pub inline fn @"xvavg.b"(p0: Register, p1: Register, p2: Register) Instruction {
10318 return encodeXdXjXk(0x74640000, p0, p1, p2);
10319 }
10320
10321 /// Encodes a `xvavg.bu` instruction (requires lasx).
10322 pub inline fn @"xvavg.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10323 return encodeXdXjXk(0x74660000, p0, p1, p2);
10324 }
10325
10326 /// Encodes a `xvavg.d` instruction (requires lasx).
10327 pub inline fn @"xvavg.d"(p0: Register, p1: Register, p2: Register) Instruction {
10328 return encodeXdXjXk(0x74658000, p0, p1, p2);
10329 }
10330
10331 /// Encodes a `xvavg.du` instruction (requires lasx).
10332 pub inline fn @"xvavg.du"(p0: Register, p1: Register, p2: Register) Instruction {
10333 return encodeXdXjXk(0x74678000, p0, p1, p2);
10334 }
10335
10336 /// Encodes a `xvavg.h` instruction (requires lasx).
10337 pub inline fn @"xvavg.h"(p0: Register, p1: Register, p2: Register) Instruction {
10338 return encodeXdXjXk(0x74648000, p0, p1, p2);
10339 }
10340
10341 /// Encodes a `xvavg.hu` instruction (requires lasx).
10342 pub inline fn @"xvavg.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10343 return encodeXdXjXk(0x74668000, p0, p1, p2);
10344 }
10345
10346 /// Encodes a `xvavg.w` instruction (requires lasx).
10347 pub inline fn @"xvavg.w"(p0: Register, p1: Register, p2: Register) Instruction {
10348 return encodeXdXjXk(0x74650000, p0, p1, p2);
10349 }
10350
10351 /// Encodes a `xvavg.wu` instruction (requires lasx).
10352 pub inline fn @"xvavg.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10353 return encodeXdXjXk(0x74670000, p0, p1, p2);
10354 }
10355
10356 /// Encodes a `xvavgr.b` instruction (requires lasx).
10357 pub inline fn @"xvavgr.b"(p0: Register, p1: Register, p2: Register) Instruction {
10358 return encodeXdXjXk(0x74680000, p0, p1, p2);
10359 }
10360
10361 /// Encodes a `xvavgr.bu` instruction (requires lasx).
10362 pub inline fn @"xvavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10363 return encodeXdXjXk(0x746a0000, p0, p1, p2);
10364 }
10365
10366 /// Encodes a `xvavgr.d` instruction (requires lasx).
10367 pub inline fn @"xvavgr.d"(p0: Register, p1: Register, p2: Register) Instruction {
10368 return encodeXdXjXk(0x74698000, p0, p1, p2);
10369 }
10370
10371 /// Encodes a `xvavgr.du` instruction (requires lasx).
10372 pub inline fn @"xvavgr.du"(p0: Register, p1: Register, p2: Register) Instruction {
10373 return encodeXdXjXk(0x746b8000, p0, p1, p2);
10374 }
10375
10376 /// Encodes a `xvavgr.h` instruction (requires lasx).
10377 pub inline fn @"xvavgr.h"(p0: Register, p1: Register, p2: Register) Instruction {
10378 return encodeXdXjXk(0x74688000, p0, p1, p2);
10379 }
10380
10381 /// Encodes a `xvavgr.hu` instruction (requires lasx).
10382 pub inline fn @"xvavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10383 return encodeXdXjXk(0x746a8000, p0, p1, p2);
10384 }
10385
10386 /// Encodes a `xvavgr.w` instruction (requires lasx).
10387 pub inline fn @"xvavgr.w"(p0: Register, p1: Register, p2: Register) Instruction {
10388 return encodeXdXjXk(0x74690000, p0, p1, p2);
10389 }
10390
10391 /// Encodes a `xvavgr.wu` instruction (requires lasx).
10392 pub inline fn @"xvavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10393 return encodeXdXjXk(0x746b0000, p0, p1, p2);
10394 }
10395
10396 /// Encodes a `xvbitclr.b` instruction (requires lasx).
10397 pub inline fn @"xvbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction {
10398 return encodeXdXjXk(0x750c0000, p0, p1, p2);
10399 }
10400
10401 /// Encodes a `xvbitclr.d` instruction (requires lasx).
10402 pub inline fn @"xvbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction {
10403 return encodeXdXjXk(0x750d8000, p0, p1, p2);
10404 }
10405
10406 /// Encodes a `xvbitclr.h` instruction (requires lasx).
10407 pub inline fn @"xvbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction {
10408 return encodeXdXjXk(0x750c8000, p0, p1, p2);
10409 }
10410
10411 /// Encodes a `xvbitclr.w` instruction (requires lasx).
10412 pub inline fn @"xvbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction {
10413 return encodeXdXjXk(0x750d0000, p0, p1, p2);
10414 }
10415
10416 /// Encodes a `xvbitclri.b` instruction (requires lasx).
10417 pub inline fn @"xvbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction {
10418 return encodeXdXjUk3(0x77102000, p0, p1, p2);
10419 }
10420
10421 /// Encodes a `xvbitclri.d` instruction (requires lasx).
10422 pub inline fn @"xvbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction {
10423 return encodeXdXjUk6(0x77110000, p0, p1, p2);
10424 }
10425
10426 /// Encodes a `xvbitclri.h` instruction (requires lasx).
10427 pub inline fn @"xvbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction {
10428 return encodeXdXjUk4(0x77104000, p0, p1, p2);
10429 }
10430
10431 /// Encodes a `xvbitclri.w` instruction (requires lasx).
10432 pub inline fn @"xvbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction {
10433 return encodeXdXjUk5(0x77108000, p0, p1, p2);
10434 }
10435
10436 /// Encodes a `xvbitrev.b` instruction (requires lasx).
10437 pub inline fn @"xvbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction {
10438 return encodeXdXjXk(0x75100000, p0, p1, p2);
10439 }
10440
10441 /// Encodes a `xvbitrev.d` instruction (requires lasx).
10442 pub inline fn @"xvbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction {
10443 return encodeXdXjXk(0x75118000, p0, p1, p2);
10444 }
10445
10446 /// Encodes a `xvbitrev.h` instruction (requires lasx).
10447 pub inline fn @"xvbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction {
10448 return encodeXdXjXk(0x75108000, p0, p1, p2);
10449 }
10450
10451 /// Encodes a `xvbitrev.w` instruction (requires lasx).
10452 pub inline fn @"xvbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction {
10453 return encodeXdXjXk(0x75110000, p0, p1, p2);
10454 }
10455
10456 /// Encodes a `xvbitrevi.b` instruction (requires lasx).
10457 pub inline fn @"xvbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction {
10458 return encodeXdXjUk3(0x77182000, p0, p1, p2);
10459 }
10460
10461 /// Encodes a `xvbitrevi.d` instruction (requires lasx).
10462 pub inline fn @"xvbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction {
10463 return encodeXdXjUk6(0x77190000, p0, p1, p2);
10464 }
10465
10466 /// Encodes a `xvbitrevi.h` instruction (requires lasx).
10467 pub inline fn @"xvbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction {
10468 return encodeXdXjUk4(0x77184000, p0, p1, p2);
10469 }
10470
10471 /// Encodes a `xvbitrevi.w` instruction (requires lasx).
10472 pub inline fn @"xvbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction {
10473 return encodeXdXjUk5(0x77188000, p0, p1, p2);
10474 }
10475
10476 /// Encodes a `xvbitsel.v` instruction (requires lasx).
10477 pub inline fn @"xvbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
10478 return encodeXdXjXkXa(0x0d200000, p0, p1, p2, p3);
10479 }
10480
10481 /// Encodes a `xvbitseli.b` instruction (requires lasx).
10482 pub inline fn @"xvbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction {
10483 return encodeXdXjUk8(0x77c40000, p0, p1, p2);
10484 }
10485
10486 /// Encodes a `xvbitset.b` instruction (requires lasx).
10487 pub inline fn @"xvbitset.b"(p0: Register, p1: Register, p2: Register) Instruction {
10488 return encodeXdXjXk(0x750e0000, p0, p1, p2);
10489 }
10490
10491 /// Encodes a `xvbitset.d` instruction (requires lasx).
10492 pub inline fn @"xvbitset.d"(p0: Register, p1: Register, p2: Register) Instruction {
10493 return encodeXdXjXk(0x750f8000, p0, p1, p2);
10494 }
10495
10496 /// Encodes a `xvbitset.h` instruction (requires lasx).
10497 pub inline fn @"xvbitset.h"(p0: Register, p1: Register, p2: Register) Instruction {
10498 return encodeXdXjXk(0x750e8000, p0, p1, p2);
10499 }
10500
10501 /// Encodes a `xvbitset.w` instruction (requires lasx).
10502 pub inline fn @"xvbitset.w"(p0: Register, p1: Register, p2: Register) Instruction {
10503 return encodeXdXjXk(0x750f0000, p0, p1, p2);
10504 }
10505
10506 /// Encodes a `xvbitseti.b` instruction (requires lasx).
10507 pub inline fn @"xvbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction {
10508 return encodeXdXjUk3(0x77142000, p0, p1, p2);
10509 }
10510
10511 /// Encodes a `xvbitseti.d` instruction (requires lasx).
10512 pub inline fn @"xvbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction {
10513 return encodeXdXjUk6(0x77150000, p0, p1, p2);
10514 }
10515
10516 /// Encodes a `xvbitseti.h` instruction (requires lasx).
10517 pub inline fn @"xvbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction {
10518 return encodeXdXjUk4(0x77144000, p0, p1, p2);
10519 }
10520
10521 /// Encodes a `xvbitseti.w` instruction (requires lasx).
10522 pub inline fn @"xvbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction {
10523 return encodeXdXjUk5(0x77148000, p0, p1, p2);
10524 }
10525
10526 /// Encodes a `xvbsll.v` instruction (requires lasx).
10527 pub inline fn @"xvbsll.v"(p0: Register, p1: Register, p2: u5) Instruction {
10528 return encodeXdXjUk5(0x768e0000, p0, p1, p2);
10529 }
10530
10531 /// Encodes a `xvbsrl.v` instruction (requires lasx).
10532 pub inline fn @"xvbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction {
10533 return encodeXdXjUk5(0x768e8000, p0, p1, p2);
10534 }
10535
10536 /// Encodes a `xvclo.b` instruction (requires lasx).
10537 pub inline fn @"xvclo.b"(p0: Register, p1: Register) Instruction {
10538 return encodeXdXj(0x769c0000, p0, p1);
10539 }
10540
10541 /// Encodes a `xvclo.d` instruction (requires lasx).
10542 pub inline fn @"xvclo.d"(p0: Register, p1: Register) Instruction {
10543 return encodeXdXj(0x769c0c00, p0, p1);
10544 }
10545
10546 /// Encodes a `xvclo.h` instruction (requires lasx).
10547 pub inline fn @"xvclo.h"(p0: Register, p1: Register) Instruction {
10548 return encodeXdXj(0x769c0400, p0, p1);
10549 }
10550
10551 /// Encodes a `xvclo.w` instruction (requires lasx).
10552 pub inline fn @"xvclo.w"(p0: Register, p1: Register) Instruction {
10553 return encodeXdXj(0x769c0800, p0, p1);
10554 }
10555
10556 /// Encodes a `xvclz.b` instruction (requires lasx).
10557 pub inline fn @"xvclz.b"(p0: Register, p1: Register) Instruction {
10558 return encodeXdXj(0x769c1000, p0, p1);
10559 }
10560
10561 /// Encodes a `xvclz.d` instruction (requires lasx).
10562 pub inline fn @"xvclz.d"(p0: Register, p1: Register) Instruction {
10563 return encodeXdXj(0x769c1c00, p0, p1);
10564 }
10565
10566 /// Encodes a `xvclz.h` instruction (requires lasx).
10567 pub inline fn @"xvclz.h"(p0: Register, p1: Register) Instruction {
10568 return encodeXdXj(0x769c1400, p0, p1);
10569 }
10570
10571 /// Encodes a `xvclz.w` instruction (requires lasx).
10572 pub inline fn @"xvclz.w"(p0: Register, p1: Register) Instruction {
10573 return encodeXdXj(0x769c1800, p0, p1);
10574 }
10575
10576 /// Encodes a `xvdiv.b` instruction (requires lasx).
10577 pub inline fn @"xvdiv.b"(p0: Register, p1: Register, p2: Register) Instruction {
10578 return encodeXdXjXk(0x74e00000, p0, p1, p2);
10579 }
10580
10581 /// Encodes a `xvdiv.bu` instruction (requires lasx).
10582 pub inline fn @"xvdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction {
10583 return encodeXdXjXk(0x74e40000, p0, p1, p2);
10584 }
10585
10586 /// Encodes a `xvdiv.d` instruction (requires lasx).
10587 pub inline fn @"xvdiv.d"(p0: Register, p1: Register, p2: Register) Instruction {
10588 return encodeXdXjXk(0x74e18000, p0, p1, p2);
10589 }
10590
10591 /// Encodes a `xvdiv.du` instruction (requires lasx).
10592 pub inline fn @"xvdiv.du"(p0: Register, p1: Register, p2: Register) Instruction {
10593 return encodeXdXjXk(0x74e58000, p0, p1, p2);
10594 }
10595
10596 /// Encodes a `xvdiv.h` instruction (requires lasx).
10597 pub inline fn @"xvdiv.h"(p0: Register, p1: Register, p2: Register) Instruction {
10598 return encodeXdXjXk(0x74e08000, p0, p1, p2);
10599 }
10600
10601 /// Encodes a `xvdiv.hu` instruction (requires lasx).
10602 pub inline fn @"xvdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction {
10603 return encodeXdXjXk(0x74e48000, p0, p1, p2);
10604 }
10605
10606 /// Encodes a `xvdiv.w` instruction (requires lasx).
10607 pub inline fn @"xvdiv.w"(p0: Register, p1: Register, p2: Register) Instruction {
10608 return encodeXdXjXk(0x74e10000, p0, p1, p2);
10609 }
10610
10611 /// Encodes a `xvdiv.wu` instruction (requires lasx).
10612 pub inline fn @"xvdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction {
10613 return encodeXdXjXk(0x74e50000, p0, p1, p2);
10614 }
10615
10616 /// Encodes a `xvexth.d.w` instruction (requires lasx).
10617 pub inline fn @"xvexth.d.w"(p0: Register, p1: Register) Instruction {
10618 return encodeXdXj(0x769ee800, p0, p1);
10619 }
10620
10621 /// Encodes a `xvexth.du.wu` instruction (requires lasx).
10622 pub inline fn @"xvexth.du.wu"(p0: Register, p1: Register) Instruction {
10623 return encodeXdXj(0x769ef800, p0, p1);
10624 }
10625
10626 /// Encodes a `xvexth.h.b` instruction (requires lasx).
10627 pub inline fn @"xvexth.h.b"(p0: Register, p1: Register) Instruction {
10628 return encodeXdXj(0x769ee000, p0, p1);
10629 }
10630
10631 /// Encodes a `xvexth.hu.bu` instruction (requires lasx).
10632 pub inline fn @"xvexth.hu.bu"(p0: Register, p1: Register) Instruction {
10633 return encodeXdXj(0x769ef000, p0, p1);
10634 }
10635
10636 /// Encodes a `xvexth.q.d` instruction (requires lasx).
10637 pub inline fn @"xvexth.q.d"(p0: Register, p1: Register) Instruction {
10638 return encodeXdXj(0x769eec00, p0, p1);
10639 }
10640
10641 /// Encodes a `xvexth.qu.du` instruction (requires lasx).
10642 pub inline fn @"xvexth.qu.du"(p0: Register, p1: Register) Instruction {
10643 return encodeXdXj(0x769efc00, p0, p1);
10644 }
10645
10646 /// Encodes a `xvexth.w.h` instruction (requires lasx).
10647 pub inline fn @"xvexth.w.h"(p0: Register, p1: Register) Instruction {
10648 return encodeXdXj(0x769ee400, p0, p1);
10649 }
10650
10651 /// Encodes a `xvexth.wu.hu` instruction (requires lasx).
10652 pub inline fn @"xvexth.wu.hu"(p0: Register, p1: Register) Instruction {
10653 return encodeXdXj(0x769ef400, p0, p1);
10654 }
10655
10656 /// Encodes a `xvextl.q.d` instruction (requires lasx).
10657 pub inline fn @"xvextl.q.d"(p0: Register, p1: Register) Instruction {
10658 return encodeXdXj(0x77090000, p0, p1);
10659 }
10660
10661 /// Encodes a `xvextl.qu.du` instruction (requires lasx).
10662 pub inline fn @"xvextl.qu.du"(p0: Register, p1: Register) Instruction {
10663 return encodeXdXj(0x770d0000, p0, p1);
10664 }
10665
10666 /// Encodes a `xvextrins.b` instruction (requires lasx).
10667 pub inline fn @"xvextrins.b"(p0: Register, p1: Register, p2: u8) Instruction {
10668 return encodeXdXjUk8(0x778c0000, p0, p1, p2);
10669 }
10670
10671 /// Encodes a `xvextrins.d` instruction (requires lasx).
10672 pub inline fn @"xvextrins.d"(p0: Register, p1: Register, p2: u8) Instruction {
10673 return encodeXdXjUk8(0x77800000, p0, p1, p2);
10674 }
10675
10676 /// Encodes a `xvextrins.h` instruction (requires lasx).
10677 pub inline fn @"xvextrins.h"(p0: Register, p1: Register, p2: u8) Instruction {
10678 return encodeXdXjUk8(0x77880000, p0, p1, p2);
10679 }
10680
10681 /// Encodes a `xvextrins.w` instruction (requires lasx).
10682 pub inline fn @"xvextrins.w"(p0: Register, p1: Register, p2: u8) Instruction {
10683 return encodeXdXjUk8(0x77840000, p0, p1, p2);
10684 }
10685
10686 /// Encodes a `xvfadd.d` instruction (requires lasx).
10687 pub inline fn @"xvfadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
10688 return encodeXdXjXk(0x75310000, p0, p1, p2);
10689 }
10690
10691 /// Encodes a `xvfadd.s` instruction (requires lasx).
10692 pub inline fn @"xvfadd.s"(p0: Register, p1: Register, p2: Register) Instruction {
10693 return encodeXdXjXk(0x75308000, p0, p1, p2);
10694 }
10695
10696 /// Encodes a `xvfclass.d` instruction (requires lasx).
10697 pub inline fn @"xvfclass.d"(p0: Register, p1: Register) Instruction {
10698 return encodeXdXj(0x769cd800, p0, p1);
10699 }
10700
10701 /// Encodes a `xvfclass.s` instruction (requires lasx).
10702 pub inline fn @"xvfclass.s"(p0: Register, p1: Register) Instruction {
10703 return encodeXdXj(0x769cd400, p0, p1);
10704 }
10705
10706 /// Encodes a `xvfcmp.caf.d` instruction (requires lasx).
10707 pub inline fn @"xvfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction {
10708 return encodeXdXjXk(0x0ca00000, p0, p1, p2);
10709 }
10710
10711 /// Encodes a `xvfcmp.caf.s` instruction (requires lasx).
10712 pub inline fn @"xvfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction {
10713 return encodeXdXjXk(0x0c900000, p0, p1, p2);
10714 }
10715
10716 /// Encodes a `xvfcmp.ceq.d` instruction (requires lasx).
10717 pub inline fn @"xvfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction {
10718 return encodeXdXjXk(0x0ca20000, p0, p1, p2);
10719 }
10720
10721 /// Encodes a `xvfcmp.ceq.s` instruction (requires lasx).
10722 pub inline fn @"xvfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction {
10723 return encodeXdXjXk(0x0c920000, p0, p1, p2);
10724 }
10725
10726 /// Encodes a `xvfcmp.cle.d` instruction (requires lasx).
10727 pub inline fn @"xvfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction {
10728 return encodeXdXjXk(0x0ca30000, p0, p1, p2);
10729 }
10730
10731 /// Encodes a `xvfcmp.cle.s` instruction (requires lasx).
10732 pub inline fn @"xvfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction {
10733 return encodeXdXjXk(0x0c930000, p0, p1, p2);
10734 }
10735
10736 /// Encodes a `xvfcmp.clt.d` instruction (requires lasx).
10737 pub inline fn @"xvfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction {
10738 return encodeXdXjXk(0x0ca10000, p0, p1, p2);
10739 }
10740
10741 /// Encodes a `xvfcmp.clt.s` instruction (requires lasx).
10742 pub inline fn @"xvfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction {
10743 return encodeXdXjXk(0x0c910000, p0, p1, p2);
10744 }
10745
10746 /// Encodes a `xvfcmp.cne.d` instruction (requires lasx).
10747 pub inline fn @"xvfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction {
10748 return encodeXdXjXk(0x0ca80000, p0, p1, p2);
10749 }
10750
10751 /// Encodes a `xvfcmp.cne.s` instruction (requires lasx).
10752 pub inline fn @"xvfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction {
10753 return encodeXdXjXk(0x0c980000, p0, p1, p2);
10754 }
10755
10756 /// Encodes a `xvfcmp.cor.d` instruction (requires lasx).
10757 pub inline fn @"xvfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction {
10758 return encodeXdXjXk(0x0caa0000, p0, p1, p2);
10759 }
10760
10761 /// Encodes a `xvfcmp.cor.s` instruction (requires lasx).
10762 pub inline fn @"xvfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction {
10763 return encodeXdXjXk(0x0c9a0000, p0, p1, p2);
10764 }
10765
10766 /// Encodes a `xvfcmp.cueq.d` instruction (requires lasx).
10767 pub inline fn @"xvfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
10768 return encodeXdXjXk(0x0ca60000, p0, p1, p2);
10769 }
10770
10771 /// Encodes a `xvfcmp.cueq.s` instruction (requires lasx).
10772 pub inline fn @"xvfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
10773 return encodeXdXjXk(0x0c960000, p0, p1, p2);
10774 }
10775
10776 /// Encodes a `xvfcmp.cule.d` instruction (requires lasx).
10777 pub inline fn @"xvfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction {
10778 return encodeXdXjXk(0x0ca70000, p0, p1, p2);
10779 }
10780
10781 /// Encodes a `xvfcmp.cule.s` instruction (requires lasx).
10782 pub inline fn @"xvfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction {
10783 return encodeXdXjXk(0x0c970000, p0, p1, p2);
10784 }
10785
10786 /// Encodes a `xvfcmp.cult.d` instruction (requires lasx).
10787 pub inline fn @"xvfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction {
10788 return encodeXdXjXk(0x0ca50000, p0, p1, p2);
10789 }
10790
10791 /// Encodes a `xvfcmp.cult.s` instruction (requires lasx).
10792 pub inline fn @"xvfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction {
10793 return encodeXdXjXk(0x0c950000, p0, p1, p2);
10794 }
10795
10796 /// Encodes a `xvfcmp.cun.d` instruction (requires lasx).
10797 pub inline fn @"xvfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction {
10798 return encodeXdXjXk(0x0ca40000, p0, p1, p2);
10799 }
10800
10801 /// Encodes a `xvfcmp.cun.s` instruction (requires lasx).
10802 pub inline fn @"xvfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction {
10803 return encodeXdXjXk(0x0c940000, p0, p1, p2);
10804 }
10805
10806 /// Encodes a `xvfcmp.cune.d` instruction (requires lasx).
10807 pub inline fn @"xvfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction {
10808 return encodeXdXjXk(0x0cac0000, p0, p1, p2);
10809 }
10810
10811 /// Encodes a `xvfcmp.cune.s` instruction (requires lasx).
10812 pub inline fn @"xvfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction {
10813 return encodeXdXjXk(0x0c9c0000, p0, p1, p2);
10814 }
10815
10816 /// Encodes a `xvfcmp.saf.d` instruction (requires lasx).
10817 pub inline fn @"xvfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction {
10818 return encodeXdXjXk(0x0ca08000, p0, p1, p2);
10819 }
10820
10821 /// Encodes a `xvfcmp.saf.s` instruction (requires lasx).
10822 pub inline fn @"xvfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction {
10823 return encodeXdXjXk(0x0c908000, p0, p1, p2);
10824 }
10825
10826 /// Encodes a `xvfcmp.seq.d` instruction (requires lasx).
10827 pub inline fn @"xvfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction {
10828 return encodeXdXjXk(0x0ca28000, p0, p1, p2);
10829 }
10830
10831 /// Encodes a `xvfcmp.seq.s` instruction (requires lasx).
10832 pub inline fn @"xvfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction {
10833 return encodeXdXjXk(0x0c928000, p0, p1, p2);
10834 }
10835
10836 /// Encodes a `xvfcmp.sle.d` instruction (requires lasx).
10837 pub inline fn @"xvfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction {
10838 return encodeXdXjXk(0x0ca38000, p0, p1, p2);
10839 }
10840
10841 /// Encodes a `xvfcmp.sle.s` instruction (requires lasx).
10842 pub inline fn @"xvfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction {
10843 return encodeXdXjXk(0x0c938000, p0, p1, p2);
10844 }
10845
10846 /// Encodes a `xvfcmp.slt.d` instruction (requires lasx).
10847 pub inline fn @"xvfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction {
10848 return encodeXdXjXk(0x0ca18000, p0, p1, p2);
10849 }
10850
10851 /// Encodes a `xvfcmp.slt.s` instruction (requires lasx).
10852 pub inline fn @"xvfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction {
10853 return encodeXdXjXk(0x0c918000, p0, p1, p2);
10854 }
10855
10856 /// Encodes a `xvfcmp.sne.d` instruction (requires lasx).
10857 pub inline fn @"xvfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction {
10858 return encodeXdXjXk(0x0ca88000, p0, p1, p2);
10859 }
10860
10861 /// Encodes a `xvfcmp.sne.s` instruction (requires lasx).
10862 pub inline fn @"xvfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction {
10863 return encodeXdXjXk(0x0c988000, p0, p1, p2);
10864 }
10865
10866 /// Encodes a `xvfcmp.sor.d` instruction (requires lasx).
10867 pub inline fn @"xvfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction {
10868 return encodeXdXjXk(0x0caa8000, p0, p1, p2);
10869 }
10870
10871 /// Encodes a `xvfcmp.sor.s` instruction (requires lasx).
10872 pub inline fn @"xvfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction {
10873 return encodeXdXjXk(0x0c9a8000, p0, p1, p2);
10874 }
10875
10876 /// Encodes a `xvfcmp.sueq.d` instruction (requires lasx).
10877 pub inline fn @"xvfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction {
10878 return encodeXdXjXk(0x0ca68000, p0, p1, p2);
10879 }
10880
10881 /// Encodes a `xvfcmp.sueq.s` instruction (requires lasx).
10882 pub inline fn @"xvfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction {
10883 return encodeXdXjXk(0x0c968000, p0, p1, p2);
10884 }
10885
10886 /// Encodes a `xvfcmp.sule.d` instruction (requires lasx).
10887 pub inline fn @"xvfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction {
10888 return encodeXdXjXk(0x0ca78000, p0, p1, p2);
10889 }
10890
10891 /// Encodes a `xvfcmp.sule.s` instruction (requires lasx).
10892 pub inline fn @"xvfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction {
10893 return encodeXdXjXk(0x0c978000, p0, p1, p2);
10894 }
10895
10896 /// Encodes a `xvfcmp.sult.d` instruction (requires lasx).
10897 pub inline fn @"xvfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction {
10898 return encodeXdXjXk(0x0ca58000, p0, p1, p2);
10899 }
10900
10901 /// Encodes a `xvfcmp.sult.s` instruction (requires lasx).
10902 pub inline fn @"xvfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction {
10903 return encodeXdXjXk(0x0c958000, p0, p1, p2);
10904 }
10905
10906 /// Encodes a `xvfcmp.sun.d` instruction (requires lasx).
10907 pub inline fn @"xvfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction {
10908 return encodeXdXjXk(0x0ca48000, p0, p1, p2);
10909 }
10910
10911 /// Encodes a `xvfcmp.sun.s` instruction (requires lasx).
10912 pub inline fn @"xvfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction {
10913 return encodeXdXjXk(0x0c948000, p0, p1, p2);
10914 }
10915
10916 /// Encodes a `xvfcmp.sune.d` instruction (requires lasx).
10917 pub inline fn @"xvfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction {
10918 return encodeXdXjXk(0x0cac8000, p0, p1, p2);
10919 }
10920
10921 /// Encodes a `xvfcmp.sune.s` instruction (requires lasx).
10922 pub inline fn @"xvfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction {
10923 return encodeXdXjXk(0x0c9c8000, p0, p1, p2);
10924 }
10925
10926 /// Encodes a `xvfcvt.h.s` instruction (requires lasx).
10927 pub inline fn @"xvfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction {
10928 return encodeXdXjXk(0x75460000, p0, p1, p2);
10929 }
10930
10931 /// Encodes a `xvfcvt.s.d` instruction (requires lasx).
10932 pub inline fn @"xvfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction {
10933 return encodeXdXjXk(0x75468000, p0, p1, p2);
10934 }
10935
10936 /// Encodes a `xvfcvth.d.s` instruction (requires lasx).
10937 pub inline fn @"xvfcvth.d.s"(p0: Register, p1: Register) Instruction {
10938 return encodeXdXj(0x769df400, p0, p1);
10939 }
10940
10941 /// Encodes a `xvfcvth.s.h` instruction (requires lasx).
10942 pub inline fn @"xvfcvth.s.h"(p0: Register, p1: Register) Instruction {
10943 return encodeXdXj(0x769dec00, p0, p1);
10944 }
10945
10946 /// Encodes a `xvfcvtl.d.s` instruction (requires lasx).
10947 pub inline fn @"xvfcvtl.d.s"(p0: Register, p1: Register) Instruction {
10948 return encodeXdXj(0x769df000, p0, p1);
10949 }
10950
10951 /// Encodes a `xvfcvtl.s.h` instruction (requires lasx).
10952 pub inline fn @"xvfcvtl.s.h"(p0: Register, p1: Register) Instruction {
10953 return encodeXdXj(0x769de800, p0, p1);
10954 }
10955
10956 /// Encodes a `xvfdiv.d` instruction (requires lasx).
10957 pub inline fn @"xvfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction {
10958 return encodeXdXjXk(0x753b0000, p0, p1, p2);
10959 }
10960
10961 /// Encodes a `xvfdiv.s` instruction (requires lasx).
10962 pub inline fn @"xvfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction {
10963 return encodeXdXjXk(0x753a8000, p0, p1, p2);
10964 }
10965
10966 /// Encodes a `xvffint.d.l` instruction (requires lasx).
10967 pub inline fn @"xvffint.d.l"(p0: Register, p1: Register) Instruction {
10968 return encodeXdXj(0x769e0800, p0, p1);
10969 }
10970
10971 /// Encodes a `xvffint.d.lu` instruction (requires lasx).
10972 pub inline fn @"xvffint.d.lu"(p0: Register, p1: Register) Instruction {
10973 return encodeXdXj(0x769e0c00, p0, p1);
10974 }
10975
10976 /// Encodes a `xvffint.s.l` instruction (requires lasx).
10977 pub inline fn @"xvffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction {
10978 return encodeXdXjXk(0x75480000, p0, p1, p2);
10979 }
10980
10981 /// Encodes a `xvffint.s.w` instruction (requires lasx).
10982 pub inline fn @"xvffint.s.w"(p0: Register, p1: Register) Instruction {
10983 return encodeXdXj(0x769e0000, p0, p1);
10984 }
10985
10986 /// Encodes a `xvffint.s.wu` instruction (requires lasx).
10987 pub inline fn @"xvffint.s.wu"(p0: Register, p1: Register) Instruction {
10988 return encodeXdXj(0x769e0400, p0, p1);
10989 }
10990
10991 /// Encodes a `xvffinth.d.w` instruction (requires lasx).
10992 pub inline fn @"xvffinth.d.w"(p0: Register, p1: Register) Instruction {
10993 return encodeXdXj(0x769e1400, p0, p1);
10994 }
10995
10996 /// Encodes a `xvffintl.d.w` instruction (requires lasx).
10997 pub inline fn @"xvffintl.d.w"(p0: Register, p1: Register) Instruction {
10998 return encodeXdXj(0x769e1000, p0, p1);
10999 }
11000
11001 /// Encodes a `xvflogb.d` instruction (requires lasx).
11002 pub inline fn @"xvflogb.d"(p0: Register, p1: Register) Instruction {
11003 return encodeXdXj(0x769cc800, p0, p1);
11004 }
11005
11006 /// Encodes a `xvflogb.s` instruction (requires lasx).
11007 pub inline fn @"xvflogb.s"(p0: Register, p1: Register) Instruction {
11008 return encodeXdXj(0x769cc400, p0, p1);
11009 }
11010
11011 /// Encodes a `xvfmadd.d` instruction (requires lasx).
11012 pub inline fn @"xvfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11013 return encodeXdXjXkXa(0x0a200000, p0, p1, p2, p3);
11014 }
11015
11016 /// Encodes a `xvfmadd.s` instruction (requires lasx).
11017 pub inline fn @"xvfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11018 return encodeXdXjXkXa(0x0a100000, p0, p1, p2, p3);
11019 }
11020
11021 /// Encodes a `xvfmax.d` instruction (requires lasx).
11022 pub inline fn @"xvfmax.d"(p0: Register, p1: Register, p2: Register) Instruction {
11023 return encodeXdXjXk(0x753d0000, p0, p1, p2);
11024 }
11025
11026 /// Encodes a `xvfmax.s` instruction (requires lasx).
11027 pub inline fn @"xvfmax.s"(p0: Register, p1: Register, p2: Register) Instruction {
11028 return encodeXdXjXk(0x753c8000, p0, p1, p2);
11029 }
11030
11031 /// Encodes a `xvfmaxa.d` instruction (requires lasx).
11032 pub inline fn @"xvfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction {
11033 return encodeXdXjXk(0x75410000, p0, p1, p2);
11034 }
11035
11036 /// Encodes a `xvfmaxa.s` instruction (requires lasx).
11037 pub inline fn @"xvfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction {
11038 return encodeXdXjXk(0x75408000, p0, p1, p2);
11039 }
11040
11041 /// Encodes a `xvfmin.d` instruction (requires lasx).
11042 pub inline fn @"xvfmin.d"(p0: Register, p1: Register, p2: Register) Instruction {
11043 return encodeXdXjXk(0x753f0000, p0, p1, p2);
11044 }
11045
11046 /// Encodes a `xvfmin.s` instruction (requires lasx).
11047 pub inline fn @"xvfmin.s"(p0: Register, p1: Register, p2: Register) Instruction {
11048 return encodeXdXjXk(0x753e8000, p0, p1, p2);
11049 }
11050
11051 /// Encodes a `xvfmina.d` instruction (requires lasx).
11052 pub inline fn @"xvfmina.d"(p0: Register, p1: Register, p2: Register) Instruction {
11053 return encodeXdXjXk(0x75430000, p0, p1, p2);
11054 }
11055
11056 /// Encodes a `xvfmina.s` instruction (requires lasx).
11057 pub inline fn @"xvfmina.s"(p0: Register, p1: Register, p2: Register) Instruction {
11058 return encodeXdXjXk(0x75428000, p0, p1, p2);
11059 }
11060
11061 /// Encodes a `xvfmsub.d` instruction (requires lasx).
11062 pub inline fn @"xvfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11063 return encodeXdXjXkXa(0x0a600000, p0, p1, p2, p3);
11064 }
11065
11066 /// Encodes a `xvfmsub.s` instruction (requires lasx).
11067 pub inline fn @"xvfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11068 return encodeXdXjXkXa(0x0a500000, p0, p1, p2, p3);
11069 }
11070
11071 /// Encodes a `xvfmul.d` instruction (requires lasx).
11072 pub inline fn @"xvfmul.d"(p0: Register, p1: Register, p2: Register) Instruction {
11073 return encodeXdXjXk(0x75390000, p0, p1, p2);
11074 }
11075
11076 /// Encodes a `xvfmul.s` instruction (requires lasx).
11077 pub inline fn @"xvfmul.s"(p0: Register, p1: Register, p2: Register) Instruction {
11078 return encodeXdXjXk(0x75388000, p0, p1, p2);
11079 }
11080
11081 /// Encodes a `xvfnmadd.d` instruction (requires lasx).
11082 pub inline fn @"xvfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11083 return encodeXdXjXkXa(0x0aa00000, p0, p1, p2, p3);
11084 }
11085
11086 /// Encodes a `xvfnmadd.s` instruction (requires lasx).
11087 pub inline fn @"xvfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11088 return encodeXdXjXkXa(0x0a900000, p0, p1, p2, p3);
11089 }
11090
11091 /// Encodes a `xvfnmsub.d` instruction (requires lasx).
11092 pub inline fn @"xvfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11093 return encodeXdXjXkXa(0x0ae00000, p0, p1, p2, p3);
11094 }
11095
11096 /// Encodes a `xvfnmsub.s` instruction (requires lasx).
11097 pub inline fn @"xvfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
11098 return encodeXdXjXkXa(0x0ad00000, p0, p1, p2, p3);
11099 }
11100
11101 /// Encodes a `xvfrecip.d` instruction (requires lasx).
11102 pub inline fn @"xvfrecip.d"(p0: Register, p1: Register) Instruction {
11103 return encodeXdXj(0x769cf800, p0, p1);
11104 }
11105
11106 /// Encodes a `xvfrecip.s` instruction (requires lasx).
11107 pub inline fn @"xvfrecip.s"(p0: Register, p1: Register) Instruction {
11108 return encodeXdXj(0x769cf400, p0, p1);
11109 }
11110
11111 /// Encodes a `xvfrecipe.d` instruction (requires lasx).
11112 pub inline fn @"xvfrecipe.d"(p0: Register, p1: Register) Instruction {
11113 return encodeXdXj(0x769d1800, p0, p1);
11114 }
11115
11116 /// Encodes a `xvfrecipe.s` instruction (requires lasx).
11117 pub inline fn @"xvfrecipe.s"(p0: Register, p1: Register) Instruction {
11118 return encodeXdXj(0x769d1400, p0, p1);
11119 }
11120
11121 /// Encodes a `xvfrint.d` instruction (requires lasx).
11122 pub inline fn @"xvfrint.d"(p0: Register, p1: Register) Instruction {
11123 return encodeXdXj(0x769d3800, p0, p1);
11124 }
11125
11126 /// Encodes a `xvfrint.s` instruction (requires lasx).
11127 pub inline fn @"xvfrint.s"(p0: Register, p1: Register) Instruction {
11128 return encodeXdXj(0x769d3400, p0, p1);
11129 }
11130
11131 /// Encodes a `xvfrintrm.d` instruction (requires lasx).
11132 pub inline fn @"xvfrintrm.d"(p0: Register, p1: Register) Instruction {
11133 return encodeXdXj(0x769d4800, p0, p1);
11134 }
11135
11136 /// Encodes a `xvfrintrm.s` instruction (requires lasx).
11137 pub inline fn @"xvfrintrm.s"(p0: Register, p1: Register) Instruction {
11138 return encodeXdXj(0x769d4400, p0, p1);
11139 }
11140
11141 /// Encodes a `xvfrintrne.d` instruction (requires lasx).
11142 pub inline fn @"xvfrintrne.d"(p0: Register, p1: Register) Instruction {
11143 return encodeXdXj(0x769d7800, p0, p1);
11144 }
11145
11146 /// Encodes a `xvfrintrne.s` instruction (requires lasx).
11147 pub inline fn @"xvfrintrne.s"(p0: Register, p1: Register) Instruction {
11148 return encodeXdXj(0x769d7400, p0, p1);
11149 }
11150
11151 /// Encodes a `xvfrintrp.d` instruction (requires lasx).
11152 pub inline fn @"xvfrintrp.d"(p0: Register, p1: Register) Instruction {
11153 return encodeXdXj(0x769d5800, p0, p1);
11154 }
11155
11156 /// Encodes a `xvfrintrp.s` instruction (requires lasx).
11157 pub inline fn @"xvfrintrp.s"(p0: Register, p1: Register) Instruction {
11158 return encodeXdXj(0x769d5400, p0, p1);
11159 }
11160
11161 /// Encodes a `xvfrintrz.d` instruction (requires lasx).
11162 pub inline fn @"xvfrintrz.d"(p0: Register, p1: Register) Instruction {
11163 return encodeXdXj(0x769d6800, p0, p1);
11164 }
11165
11166 /// Encodes a `xvfrintrz.s` instruction (requires lasx).
11167 pub inline fn @"xvfrintrz.s"(p0: Register, p1: Register) Instruction {
11168 return encodeXdXj(0x769d6400, p0, p1);
11169 }
11170
11171 /// Encodes a `xvfrsqrt.d` instruction (requires lasx).
11172 pub inline fn @"xvfrsqrt.d"(p0: Register, p1: Register) Instruction {
11173 return encodeXdXj(0x769d0800, p0, p1);
11174 }
11175
11176 /// Encodes a `xvfrsqrt.s` instruction (requires lasx).
11177 pub inline fn @"xvfrsqrt.s"(p0: Register, p1: Register) Instruction {
11178 return encodeXdXj(0x769d0400, p0, p1);
11179 }
11180
11181 /// Encodes a `xvfrsqrte.d` instruction (requires lasx).
11182 pub inline fn @"xvfrsqrte.d"(p0: Register, p1: Register) Instruction {
11183 return encodeXdXj(0x769d2800, p0, p1);
11184 }
11185
11186 /// Encodes a `xvfrsqrte.s` instruction (requires lasx).
11187 pub inline fn @"xvfrsqrte.s"(p0: Register, p1: Register) Instruction {
11188 return encodeXdXj(0x769d2400, p0, p1);
11189 }
11190
11191 /// Encodes a `xvfrstp.b` instruction (requires lasx).
11192 pub inline fn @"xvfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction {
11193 return encodeXdXjXk(0x752b0000, p0, p1, p2);
11194 }
11195
11196 /// Encodes a `xvfrstp.h` instruction (requires lasx).
11197 pub inline fn @"xvfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction {
11198 return encodeXdXjXk(0x752b8000, p0, p1, p2);
11199 }
11200
11201 /// Encodes a `xvfrstpi.b` instruction (requires lasx).
11202 pub inline fn @"xvfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction {
11203 return encodeXdXjUk5(0x769a0000, p0, p1, p2);
11204 }
11205
11206 /// Encodes a `xvfrstpi.h` instruction (requires lasx).
11207 pub inline fn @"xvfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction {
11208 return encodeXdXjUk5(0x769a8000, p0, p1, p2);
11209 }
11210
11211 /// Encodes a `xvfsqrt.d` instruction (requires lasx).
11212 pub inline fn @"xvfsqrt.d"(p0: Register, p1: Register) Instruction {
11213 return encodeXdXj(0x769ce800, p0, p1);
11214 }
11215
11216 /// Encodes a `xvfsqrt.s` instruction (requires lasx).
11217 pub inline fn @"xvfsqrt.s"(p0: Register, p1: Register) Instruction {
11218 return encodeXdXj(0x769ce400, p0, p1);
11219 }
11220
11221 /// Encodes a `xvfsub.d` instruction (requires lasx).
11222 pub inline fn @"xvfsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
11223 return encodeXdXjXk(0x75330000, p0, p1, p2);
11224 }
11225
11226 /// Encodes a `xvfsub.s` instruction (requires lasx).
11227 pub inline fn @"xvfsub.s"(p0: Register, p1: Register, p2: Register) Instruction {
11228 return encodeXdXjXk(0x75328000, p0, p1, p2);
11229 }
11230
11231 /// Encodes a `xvftint.l.d` instruction (requires lasx).
11232 pub inline fn @"xvftint.l.d"(p0: Register, p1: Register) Instruction {
11233 return encodeXdXj(0x769e3400, p0, p1);
11234 }
11235
11236 /// Encodes a `xvftint.lu.d` instruction (requires lasx).
11237 pub inline fn @"xvftint.lu.d"(p0: Register, p1: Register) Instruction {
11238 return encodeXdXj(0x769e5c00, p0, p1);
11239 }
11240
11241 /// Encodes a `xvftint.w.d` instruction (requires lasx).
11242 pub inline fn @"xvftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
11243 return encodeXdXjXk(0x75498000, p0, p1, p2);
11244 }
11245
11246 /// Encodes a `xvftint.w.s` instruction (requires lasx).
11247 pub inline fn @"xvftint.w.s"(p0: Register, p1: Register) Instruction {
11248 return encodeXdXj(0x769e3000, p0, p1);
11249 }
11250
11251 /// Encodes a `xvftint.wu.s` instruction (requires lasx).
11252 pub inline fn @"xvftint.wu.s"(p0: Register, p1: Register) Instruction {
11253 return encodeXdXj(0x769e5800, p0, p1);
11254 }
11255
11256 /// Encodes a `xvftinth.l.s` instruction (requires lasx).
11257 pub inline fn @"xvftinth.l.s"(p0: Register, p1: Register) Instruction {
11258 return encodeXdXj(0x769e8400, p0, p1);
11259 }
11260
11261 /// Encodes a `xvftintl.l.s` instruction (requires lasx).
11262 pub inline fn @"xvftintl.l.s"(p0: Register, p1: Register) Instruction {
11263 return encodeXdXj(0x769e8000, p0, p1);
11264 }
11265
11266 /// Encodes a `xvftintrm.l.d` instruction (requires lasx).
11267 pub inline fn @"xvftintrm.l.d"(p0: Register, p1: Register) Instruction {
11268 return encodeXdXj(0x769e3c00, p0, p1);
11269 }
11270
11271 /// Encodes a `xvftintrm.w.d` instruction (requires lasx).
11272 pub inline fn @"xvftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
11273 return encodeXdXjXk(0x754a0000, p0, p1, p2);
11274 }
11275
11276 /// Encodes a `xvftintrm.w.s` instruction (requires lasx).
11277 pub inline fn @"xvftintrm.w.s"(p0: Register, p1: Register) Instruction {
11278 return encodeXdXj(0x769e3800, p0, p1);
11279 }
11280
11281 /// Encodes a `xvftintrmh.l.s` instruction (requires lasx).
11282 pub inline fn @"xvftintrmh.l.s"(p0: Register, p1: Register) Instruction {
11283 return encodeXdXj(0x769e8c00, p0, p1);
11284 }
11285
11286 /// Encodes a `xvftintrml.l.s` instruction (requires lasx).
11287 pub inline fn @"xvftintrml.l.s"(p0: Register, p1: Register) Instruction {
11288 return encodeXdXj(0x769e8800, p0, p1);
11289 }
11290
11291 /// Encodes a `xvftintrne.l.d` instruction (requires lasx).
11292 pub inline fn @"xvftintrne.l.d"(p0: Register, p1: Register) Instruction {
11293 return encodeXdXj(0x769e5400, p0, p1);
11294 }
11295
11296 /// Encodes a `xvftintrne.w.d` instruction (requires lasx).
11297 pub inline fn @"xvftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
11298 return encodeXdXjXk(0x754b8000, p0, p1, p2);
11299 }
11300
11301 /// Encodes a `xvftintrne.w.s` instruction (requires lasx).
11302 pub inline fn @"xvftintrne.w.s"(p0: Register, p1: Register) Instruction {
11303 return encodeXdXj(0x769e5000, p0, p1);
11304 }
11305
11306 /// Encodes a `xvftintrneh.l.s` instruction (requires lasx).
11307 pub inline fn @"xvftintrneh.l.s"(p0: Register, p1: Register) Instruction {
11308 return encodeXdXj(0x769ea400, p0, p1);
11309 }
11310
11311 /// Encodes a `xvftintrnel.l.s` instruction (requires lasx).
11312 pub inline fn @"xvftintrnel.l.s"(p0: Register, p1: Register) Instruction {
11313 return encodeXdXj(0x769ea000, p0, p1);
11314 }
11315
11316 /// Encodes a `xvftintrp.l.d` instruction (requires lasx).
11317 pub inline fn @"xvftintrp.l.d"(p0: Register, p1: Register) Instruction {
11318 return encodeXdXj(0x769e4400, p0, p1);
11319 }
11320
11321 /// Encodes a `xvftintrp.w.d` instruction (requires lasx).
11322 pub inline fn @"xvftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
11323 return encodeXdXjXk(0x754a8000, p0, p1, p2);
11324 }
11325
11326 /// Encodes a `xvftintrp.w.s` instruction (requires lasx).
11327 pub inline fn @"xvftintrp.w.s"(p0: Register, p1: Register) Instruction {
11328 return encodeXdXj(0x769e4000, p0, p1);
11329 }
11330
11331 /// Encodes a `xvftintrph.l.s` instruction (requires lasx).
11332 pub inline fn @"xvftintrph.l.s"(p0: Register, p1: Register) Instruction {
11333 return encodeXdXj(0x769e9400, p0, p1);
11334 }
11335
11336 /// Encodes a `xvftintrpl.l.s` instruction (requires lasx).
11337 pub inline fn @"xvftintrpl.l.s"(p0: Register, p1: Register) Instruction {
11338 return encodeXdXj(0x769e9000, p0, p1);
11339 }
11340
11341 /// Encodes a `xvftintrz.l.d` instruction (requires lasx).
11342 pub inline fn @"xvftintrz.l.d"(p0: Register, p1: Register) Instruction {
11343 return encodeXdXj(0x769e4c00, p0, p1);
11344 }
11345
11346 /// Encodes a `xvftintrz.lu.d` instruction (requires lasx).
11347 pub inline fn @"xvftintrz.lu.d"(p0: Register, p1: Register) Instruction {
11348 return encodeXdXj(0x769e7400, p0, p1);
11349 }
11350
11351 /// Encodes a `xvftintrz.w.d` instruction (requires lasx).
11352 pub inline fn @"xvftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
11353 return encodeXdXjXk(0x754b0000, p0, p1, p2);
11354 }
11355
11356 /// Encodes a `xvftintrz.w.s` instruction (requires lasx).
11357 pub inline fn @"xvftintrz.w.s"(p0: Register, p1: Register) Instruction {
11358 return encodeXdXj(0x769e4800, p0, p1);
11359 }
11360
11361 /// Encodes a `xvftintrz.wu.s` instruction (requires lasx).
11362 pub inline fn @"xvftintrz.wu.s"(p0: Register, p1: Register) Instruction {
11363 return encodeXdXj(0x769e7000, p0, p1);
11364 }
11365
11366 /// Encodes a `xvftintrzh.l.s` instruction (requires lasx).
11367 pub inline fn @"xvftintrzh.l.s"(p0: Register, p1: Register) Instruction {
11368 return encodeXdXj(0x769e9c00, p0, p1);
11369 }
11370
11371 /// Encodes a `xvftintrzl.l.s` instruction (requires lasx).
11372 pub inline fn @"xvftintrzl.l.s"(p0: Register, p1: Register) Instruction {
11373 return encodeXdXj(0x769e9800, p0, p1);
11374 }
11375
11376 /// Encodes a `xvhaddw.d.w` instruction (requires lasx).
11377 pub inline fn @"xvhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
11378 return encodeXdXjXk(0x74550000, p0, p1, p2);
11379 }
11380
11381 /// Encodes a `xvhaddw.du.wu` instruction (requires lasx).
11382 pub inline fn @"xvhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11383 return encodeXdXjXk(0x74590000, p0, p1, p2);
11384 }
11385
11386 /// Encodes a `xvhaddw.h.b` instruction (requires lasx).
11387 pub inline fn @"xvhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
11388 return encodeXdXjXk(0x74540000, p0, p1, p2);
11389 }
11390
11391 /// Encodes a `xvhaddw.hu.bu` instruction (requires lasx).
11392 pub inline fn @"xvhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11393 return encodeXdXjXk(0x74580000, p0, p1, p2);
11394 }
11395
11396 /// Encodes a `xvhaddw.q.d` instruction (requires lasx).
11397 pub inline fn @"xvhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
11398 return encodeXdXjXk(0x74558000, p0, p1, p2);
11399 }
11400
11401 /// Encodes a `xvhaddw.qu.du` instruction (requires lasx).
11402 pub inline fn @"xvhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction {
11403 return encodeXdXjXk(0x74598000, p0, p1, p2);
11404 }
11405
11406 /// Encodes a `xvhaddw.w.h` instruction (requires lasx).
11407 pub inline fn @"xvhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
11408 return encodeXdXjXk(0x74548000, p0, p1, p2);
11409 }
11410
11411 /// Encodes a `xvhaddw.wu.hu` instruction (requires lasx).
11412 pub inline fn @"xvhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11413 return encodeXdXjXk(0x74588000, p0, p1, p2);
11414 }
11415
11416 /// Encodes a `xvhsubw.d.w` instruction (requires lasx).
11417 pub inline fn @"xvhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
11418 return encodeXdXjXk(0x74570000, p0, p1, p2);
11419 }
11420
11421 /// Encodes a `xvhsubw.du.wu` instruction (requires lasx).
11422 pub inline fn @"xvhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11423 return encodeXdXjXk(0x745b0000, p0, p1, p2);
11424 }
11425
11426 /// Encodes a `xvhsubw.h.b` instruction (requires lasx).
11427 pub inline fn @"xvhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
11428 return encodeXdXjXk(0x74560000, p0, p1, p2);
11429 }
11430
11431 /// Encodes a `xvhsubw.hu.bu` instruction (requires lasx).
11432 pub inline fn @"xvhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11433 return encodeXdXjXk(0x745a0000, p0, p1, p2);
11434 }
11435
11436 /// Encodes a `xvhsubw.q.d` instruction (requires lasx).
11437 pub inline fn @"xvhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
11438 return encodeXdXjXk(0x74578000, p0, p1, p2);
11439 }
11440
11441 /// Encodes a `xvhsubw.qu.du` instruction (requires lasx).
11442 pub inline fn @"xvhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction {
11443 return encodeXdXjXk(0x745b8000, p0, p1, p2);
11444 }
11445
11446 /// Encodes a `xvhsubw.w.h` instruction (requires lasx).
11447 pub inline fn @"xvhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
11448 return encodeXdXjXk(0x74568000, p0, p1, p2);
11449 }
11450
11451 /// Encodes a `xvhsubw.wu.hu` instruction (requires lasx).
11452 pub inline fn @"xvhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11453 return encodeXdXjXk(0x745a8000, p0, p1, p2);
11454 }
11455
11456 /// Encodes a `xvilvh.b` instruction (requires lasx).
11457 pub inline fn @"xvilvh.b"(p0: Register, p1: Register, p2: Register) Instruction {
11458 return encodeXdXjXk(0x751c0000, p0, p1, p2);
11459 }
11460
11461 /// Encodes a `xvilvh.d` instruction (requires lasx).
11462 pub inline fn @"xvilvh.d"(p0: Register, p1: Register, p2: Register) Instruction {
11463 return encodeXdXjXk(0x751d8000, p0, p1, p2);
11464 }
11465
11466 /// Encodes a `xvilvh.h` instruction (requires lasx).
11467 pub inline fn @"xvilvh.h"(p0: Register, p1: Register, p2: Register) Instruction {
11468 return encodeXdXjXk(0x751c8000, p0, p1, p2);
11469 }
11470
11471 /// Encodes a `xvilvh.w` instruction (requires lasx).
11472 pub inline fn @"xvilvh.w"(p0: Register, p1: Register, p2: Register) Instruction {
11473 return encodeXdXjXk(0x751d0000, p0, p1, p2);
11474 }
11475
11476 /// Encodes a `xvilvl.b` instruction (requires lasx).
11477 pub inline fn @"xvilvl.b"(p0: Register, p1: Register, p2: Register) Instruction {
11478 return encodeXdXjXk(0x751a0000, p0, p1, p2);
11479 }
11480
11481 /// Encodes a `xvilvl.d` instruction (requires lasx).
11482 pub inline fn @"xvilvl.d"(p0: Register, p1: Register, p2: Register) Instruction {
11483 return encodeXdXjXk(0x751b8000, p0, p1, p2);
11484 }
11485
11486 /// Encodes a `xvilvl.h` instruction (requires lasx).
11487 pub inline fn @"xvilvl.h"(p0: Register, p1: Register, p2: Register) Instruction {
11488 return encodeXdXjXk(0x751a8000, p0, p1, p2);
11489 }
11490
11491 /// Encodes a `xvilvl.w` instruction (requires lasx).
11492 pub inline fn @"xvilvl.w"(p0: Register, p1: Register, p2: Register) Instruction {
11493 return encodeXdXjXk(0x751b0000, p0, p1, p2);
11494 }
11495
11496 /// Encodes a `xvinsgr2vr.d` instruction (requires lasx).
11497 pub inline fn @"xvinsgr2vr.d"(p0: Register, p1: Register, p2: u2) Instruction {
11498 return encodeXdJUk2(0x76ebe000, p0, p1, p2);
11499 }
11500
11501 /// Encodes a `xvinsgr2vr.w` instruction (requires lasx).
11502 pub inline fn @"xvinsgr2vr.w"(p0: Register, p1: Register, p2: u3) Instruction {
11503 return encodeXdJUk3(0x76ebc000, p0, p1, p2);
11504 }
11505
11506 /// Encodes a `xvinsve0.d` instruction (requires lasx).
11507 pub inline fn @"xvinsve0.d"(p0: Register, p1: Register, p2: u2) Instruction {
11508 return encodeXdXjUk2(0x76ffe000, p0, p1, p2);
11509 }
11510
11511 /// Encodes a `xvinsve0.w` instruction (requires lasx).
11512 pub inline fn @"xvinsve0.w"(p0: Register, p1: Register, p2: u3) Instruction {
11513 return encodeXdXjUk3(0x76ffc000, p0, p1, p2);
11514 }
11515
11516 /// Encodes a `xvld` instruction (requires lasx).
11517 pub inline fn xvld(p0: Register, p1: Register, p2: i12) Instruction {
11518 return encodeXdJSk12(0x2c800000, p0, p1, p2);
11519 }
11520
11521 /// Encodes a `xvldi` instruction (requires lasx).
11522 pub inline fn xvldi(p0: Register, p1: i13) Instruction {
11523 return encodeXdSj13(0x77e00000, p0, p1);
11524 }
11525
11526 /// Encodes a `xvldrepl.b` instruction (requires lasx).
11527 pub inline fn @"xvldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction {
11528 return encodeXdJSk12(0x32800000, p0, p1, p2);
11529 }
11530
11531 /// Encodes a `xvldrepl.d` instruction (requires lasx).
11532 pub inline fn @"xvldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction {
11533 return encodeXdJSk9ps3(0x32100000, p0, p1, p2);
11534 }
11535
11536 /// Encodes a `xvldrepl.h` instruction (requires lasx).
11537 pub inline fn @"xvldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction {
11538 return encodeXdJSk11ps1(0x32400000, p0, p1, p2);
11539 }
11540
11541 /// Encodes a `xvldrepl.w` instruction (requires lasx).
11542 pub inline fn @"xvldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction {
11543 return encodeXdJSk10ps2(0x32200000, p0, p1, p2);
11544 }
11545
11546 /// Encodes a `xvldx` instruction (requires lasx).
11547 pub inline fn xvldx(p0: Register, p1: Register, p2: Register) Instruction {
11548 return encodeXdJK(0x38480000, p0, p1, p2);
11549 }
11550
11551 /// Encodes a `xvmadd.b` instruction (requires lasx).
11552 pub inline fn @"xvmadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
11553 return encodeXdXjXk(0x74a80000, p0, p1, p2);
11554 }
11555
11556 /// Encodes a `xvmadd.d` instruction (requires lasx).
11557 pub inline fn @"xvmadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
11558 return encodeXdXjXk(0x74a98000, p0, p1, p2);
11559 }
11560
11561 /// Encodes a `xvmadd.h` instruction (requires lasx).
11562 pub inline fn @"xvmadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
11563 return encodeXdXjXk(0x74a88000, p0, p1, p2);
11564 }
11565
11566 /// Encodes a `xvmadd.w` instruction (requires lasx).
11567 pub inline fn @"xvmadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
11568 return encodeXdXjXk(0x74a90000, p0, p1, p2);
11569 }
11570
11571 /// Encodes a `xvmaddwev.d.w` instruction (requires lasx).
11572 pub inline fn @"xvmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
11573 return encodeXdXjXk(0x74ad0000, p0, p1, p2);
11574 }
11575
11576 /// Encodes a `xvmaddwev.d.wu` instruction (requires lasx).
11577 pub inline fn @"xvmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11578 return encodeXdXjXk(0x74b50000, p0, p1, p2);
11579 }
11580
11581 /// Encodes a `xvmaddwev.d.wu.w` instruction (requires lasx).
11582 pub inline fn @"xvmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
11583 return encodeXdXjXk(0x74bd0000, p0, p1, p2);
11584 }
11585
11586 /// Encodes a `xvmaddwev.h.b` instruction (requires lasx).
11587 pub inline fn @"xvmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
11588 return encodeXdXjXk(0x74ac0000, p0, p1, p2);
11589 }
11590
11591 /// Encodes a `xvmaddwev.h.bu` instruction (requires lasx).
11592 pub inline fn @"xvmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11593 return encodeXdXjXk(0x74b40000, p0, p1, p2);
11594 }
11595
11596 /// Encodes a `xvmaddwev.h.bu.b` instruction (requires lasx).
11597 pub inline fn @"xvmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
11598 return encodeXdXjXk(0x74bc0000, p0, p1, p2);
11599 }
11600
11601 /// Encodes a `xvmaddwev.q.d` instruction (requires lasx).
11602 pub inline fn @"xvmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
11603 return encodeXdXjXk(0x74ad8000, p0, p1, p2);
11604 }
11605
11606 /// Encodes a `xvmaddwev.q.du` instruction (requires lasx).
11607 pub inline fn @"xvmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
11608 return encodeXdXjXk(0x74b58000, p0, p1, p2);
11609 }
11610
11611 /// Encodes a `xvmaddwev.q.du.d` instruction (requires lasx).
11612 pub inline fn @"xvmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
11613 return encodeXdXjXk(0x74bd8000, p0, p1, p2);
11614 }
11615
11616 /// Encodes a `xvmaddwev.w.h` instruction (requires lasx).
11617 pub inline fn @"xvmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
11618 return encodeXdXjXk(0x74ac8000, p0, p1, p2);
11619 }
11620
11621 /// Encodes a `xvmaddwev.w.hu` instruction (requires lasx).
11622 pub inline fn @"xvmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11623 return encodeXdXjXk(0x74b48000, p0, p1, p2);
11624 }
11625
11626 /// Encodes a `xvmaddwev.w.hu.h` instruction (requires lasx).
11627 pub inline fn @"xvmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
11628 return encodeXdXjXk(0x74bc8000, p0, p1, p2);
11629 }
11630
11631 /// Encodes a `xvmaddwod.d.w` instruction (requires lasx).
11632 pub inline fn @"xvmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
11633 return encodeXdXjXk(0x74af0000, p0, p1, p2);
11634 }
11635
11636 /// Encodes a `xvmaddwod.d.wu` instruction (requires lasx).
11637 pub inline fn @"xvmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11638 return encodeXdXjXk(0x74b70000, p0, p1, p2);
11639 }
11640
11641 /// Encodes a `xvmaddwod.d.wu.w` instruction (requires lasx).
11642 pub inline fn @"xvmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
11643 return encodeXdXjXk(0x74bf0000, p0, p1, p2);
11644 }
11645
11646 /// Encodes a `xvmaddwod.h.b` instruction (requires lasx).
11647 pub inline fn @"xvmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
11648 return encodeXdXjXk(0x74ae0000, p0, p1, p2);
11649 }
11650
11651 /// Encodes a `xvmaddwod.h.bu` instruction (requires lasx).
11652 pub inline fn @"xvmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11653 return encodeXdXjXk(0x74b60000, p0, p1, p2);
11654 }
11655
11656 /// Encodes a `xvmaddwod.h.bu.b` instruction (requires lasx).
11657 pub inline fn @"xvmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
11658 return encodeXdXjXk(0x74be0000, p0, p1, p2);
11659 }
11660
11661 /// Encodes a `xvmaddwod.q.d` instruction (requires lasx).
11662 pub inline fn @"xvmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
11663 return encodeXdXjXk(0x74af8000, p0, p1, p2);
11664 }
11665
11666 /// Encodes a `xvmaddwod.q.du` instruction (requires lasx).
11667 pub inline fn @"xvmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
11668 return encodeXdXjXk(0x74b78000, p0, p1, p2);
11669 }
11670
11671 /// Encodes a `xvmaddwod.q.du.d` instruction (requires lasx).
11672 pub inline fn @"xvmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
11673 return encodeXdXjXk(0x74bf8000, p0, p1, p2);
11674 }
11675
11676 /// Encodes a `xvmaddwod.w.h` instruction (requires lasx).
11677 pub inline fn @"xvmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
11678 return encodeXdXjXk(0x74ae8000, p0, p1, p2);
11679 }
11680
11681 /// Encodes a `xvmaddwod.w.hu` instruction (requires lasx).
11682 pub inline fn @"xvmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11683 return encodeXdXjXk(0x74b68000, p0, p1, p2);
11684 }
11685
11686 /// Encodes a `xvmaddwod.w.hu.h` instruction (requires lasx).
11687 pub inline fn @"xvmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
11688 return encodeXdXjXk(0x74be8000, p0, p1, p2);
11689 }
11690
11691 /// Encodes a `xvmax.b` instruction (requires lasx).
11692 pub inline fn @"xvmax.b"(p0: Register, p1: Register, p2: Register) Instruction {
11693 return encodeXdXjXk(0x74700000, p0, p1, p2);
11694 }
11695
11696 /// Encodes a `xvmax.bu` instruction (requires lasx).
11697 pub inline fn @"xvmax.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11698 return encodeXdXjXk(0x74740000, p0, p1, p2);
11699 }
11700
11701 /// Encodes a `xvmax.d` instruction (requires lasx).
11702 pub inline fn @"xvmax.d"(p0: Register, p1: Register, p2: Register) Instruction {
11703 return encodeXdXjXk(0x74718000, p0, p1, p2);
11704 }
11705
11706 /// Encodes a `xvmax.du` instruction (requires lasx).
11707 pub inline fn @"xvmax.du"(p0: Register, p1: Register, p2: Register) Instruction {
11708 return encodeXdXjXk(0x74758000, p0, p1, p2);
11709 }
11710
11711 /// Encodes a `xvmax.h` instruction (requires lasx).
11712 pub inline fn @"xvmax.h"(p0: Register, p1: Register, p2: Register) Instruction {
11713 return encodeXdXjXk(0x74708000, p0, p1, p2);
11714 }
11715
11716 /// Encodes a `xvmax.hu` instruction (requires lasx).
11717 pub inline fn @"xvmax.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11718 return encodeXdXjXk(0x74748000, p0, p1, p2);
11719 }
11720
11721 /// Encodes a `xvmax.w` instruction (requires lasx).
11722 pub inline fn @"xvmax.w"(p0: Register, p1: Register, p2: Register) Instruction {
11723 return encodeXdXjXk(0x74710000, p0, p1, p2);
11724 }
11725
11726 /// Encodes a `xvmax.wu` instruction (requires lasx).
11727 pub inline fn @"xvmax.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11728 return encodeXdXjXk(0x74750000, p0, p1, p2);
11729 }
11730
11731 /// Encodes a `xvmaxi.b` instruction (requires lasx).
11732 pub inline fn @"xvmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction {
11733 return encodeXdXjSk5(0x76900000, p0, p1, p2);
11734 }
11735
11736 /// Encodes a `xvmaxi.bu` instruction (requires lasx).
11737 pub inline fn @"xvmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
11738 return encodeXdXjUk5(0x76940000, p0, p1, p2);
11739 }
11740
11741 /// Encodes a `xvmaxi.d` instruction (requires lasx).
11742 pub inline fn @"xvmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction {
11743 return encodeXdXjSk5(0x76918000, p0, p1, p2);
11744 }
11745
11746 /// Encodes a `xvmaxi.du` instruction (requires lasx).
11747 pub inline fn @"xvmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction {
11748 return encodeXdXjUk5(0x76958000, p0, p1, p2);
11749 }
11750
11751 /// Encodes a `xvmaxi.h` instruction (requires lasx).
11752 pub inline fn @"xvmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction {
11753 return encodeXdXjSk5(0x76908000, p0, p1, p2);
11754 }
11755
11756 /// Encodes a `xvmaxi.hu` instruction (requires lasx).
11757 pub inline fn @"xvmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
11758 return encodeXdXjUk5(0x76948000, p0, p1, p2);
11759 }
11760
11761 /// Encodes a `xvmaxi.w` instruction (requires lasx).
11762 pub inline fn @"xvmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction {
11763 return encodeXdXjSk5(0x76910000, p0, p1, p2);
11764 }
11765
11766 /// Encodes a `xvmaxi.wu` instruction (requires lasx).
11767 pub inline fn @"xvmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
11768 return encodeXdXjUk5(0x76950000, p0, p1, p2);
11769 }
11770
11771 /// Encodes a `xvmepatmsk.v` instruction (requires lasx).
11772 pub inline fn @"xvmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction {
11773 return encodeXdUj5Uk5(0x769b8000, p0, p1, p2);
11774 }
11775
11776 /// Encodes a `xvmin.b` instruction (requires lasx).
11777 pub inline fn @"xvmin.b"(p0: Register, p1: Register, p2: Register) Instruction {
11778 return encodeXdXjXk(0x74720000, p0, p1, p2);
11779 }
11780
11781 /// Encodes a `xvmin.bu` instruction (requires lasx).
11782 pub inline fn @"xvmin.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11783 return encodeXdXjXk(0x74760000, p0, p1, p2);
11784 }
11785
11786 /// Encodes a `xvmin.d` instruction (requires lasx).
11787 pub inline fn @"xvmin.d"(p0: Register, p1: Register, p2: Register) Instruction {
11788 return encodeXdXjXk(0x74738000, p0, p1, p2);
11789 }
11790
11791 /// Encodes a `xvmin.du` instruction (requires lasx).
11792 pub inline fn @"xvmin.du"(p0: Register, p1: Register, p2: Register) Instruction {
11793 return encodeXdXjXk(0x74778000, p0, p1, p2);
11794 }
11795
11796 /// Encodes a `xvmin.h` instruction (requires lasx).
11797 pub inline fn @"xvmin.h"(p0: Register, p1: Register, p2: Register) Instruction {
11798 return encodeXdXjXk(0x74728000, p0, p1, p2);
11799 }
11800
11801 /// Encodes a `xvmin.hu` instruction (requires lasx).
11802 pub inline fn @"xvmin.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11803 return encodeXdXjXk(0x74768000, p0, p1, p2);
11804 }
11805
11806 /// Encodes a `xvmin.w` instruction (requires lasx).
11807 pub inline fn @"xvmin.w"(p0: Register, p1: Register, p2: Register) Instruction {
11808 return encodeXdXjXk(0x74730000, p0, p1, p2);
11809 }
11810
11811 /// Encodes a `xvmin.wu` instruction (requires lasx).
11812 pub inline fn @"xvmin.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11813 return encodeXdXjXk(0x74770000, p0, p1, p2);
11814 }
11815
11816 /// Encodes a `xvmini.b` instruction (requires lasx).
11817 pub inline fn @"xvmini.b"(p0: Register, p1: Register, p2: i5) Instruction {
11818 return encodeXdXjSk5(0x76920000, p0, p1, p2);
11819 }
11820
11821 /// Encodes a `xvmini.bu` instruction (requires lasx).
11822 pub inline fn @"xvmini.bu"(p0: Register, p1: Register, p2: u5) Instruction {
11823 return encodeXdXjUk5(0x76960000, p0, p1, p2);
11824 }
11825
11826 /// Encodes a `xvmini.d` instruction (requires lasx).
11827 pub inline fn @"xvmini.d"(p0: Register, p1: Register, p2: i5) Instruction {
11828 return encodeXdXjSk5(0x76938000, p0, p1, p2);
11829 }
11830
11831 /// Encodes a `xvmini.du` instruction (requires lasx).
11832 pub inline fn @"xvmini.du"(p0: Register, p1: Register, p2: u5) Instruction {
11833 return encodeXdXjUk5(0x76978000, p0, p1, p2);
11834 }
11835
11836 /// Encodes a `xvmini.h` instruction (requires lasx).
11837 pub inline fn @"xvmini.h"(p0: Register, p1: Register, p2: i5) Instruction {
11838 return encodeXdXjSk5(0x76928000, p0, p1, p2);
11839 }
11840
11841 /// Encodes a `xvmini.hu` instruction (requires lasx).
11842 pub inline fn @"xvmini.hu"(p0: Register, p1: Register, p2: u5) Instruction {
11843 return encodeXdXjUk5(0x76968000, p0, p1, p2);
11844 }
11845
11846 /// Encodes a `xvmini.w` instruction (requires lasx).
11847 pub inline fn @"xvmini.w"(p0: Register, p1: Register, p2: i5) Instruction {
11848 return encodeXdXjSk5(0x76930000, p0, p1, p2);
11849 }
11850
11851 /// Encodes a `xvmini.wu` instruction (requires lasx).
11852 pub inline fn @"xvmini.wu"(p0: Register, p1: Register, p2: u5) Instruction {
11853 return encodeXdXjUk5(0x76970000, p0, p1, p2);
11854 }
11855
11856 /// Encodes a `xvmod.b` instruction (requires lasx).
11857 pub inline fn @"xvmod.b"(p0: Register, p1: Register, p2: Register) Instruction {
11858 return encodeXdXjXk(0x74e20000, p0, p1, p2);
11859 }
11860
11861 /// Encodes a `xvmod.bu` instruction (requires lasx).
11862 pub inline fn @"xvmod.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11863 return encodeXdXjXk(0x74e60000, p0, p1, p2);
11864 }
11865
11866 /// Encodes a `xvmod.d` instruction (requires lasx).
11867 pub inline fn @"xvmod.d"(p0: Register, p1: Register, p2: Register) Instruction {
11868 return encodeXdXjXk(0x74e38000, p0, p1, p2);
11869 }
11870
11871 /// Encodes a `xvmod.du` instruction (requires lasx).
11872 pub inline fn @"xvmod.du"(p0: Register, p1: Register, p2: Register) Instruction {
11873 return encodeXdXjXk(0x74e78000, p0, p1, p2);
11874 }
11875
11876 /// Encodes a `xvmod.h` instruction (requires lasx).
11877 pub inline fn @"xvmod.h"(p0: Register, p1: Register, p2: Register) Instruction {
11878 return encodeXdXjXk(0x74e28000, p0, p1, p2);
11879 }
11880
11881 /// Encodes a `xvmod.hu` instruction (requires lasx).
11882 pub inline fn @"xvmod.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11883 return encodeXdXjXk(0x74e68000, p0, p1, p2);
11884 }
11885
11886 /// Encodes a `xvmod.w` instruction (requires lasx).
11887 pub inline fn @"xvmod.w"(p0: Register, p1: Register, p2: Register) Instruction {
11888 return encodeXdXjXk(0x74e30000, p0, p1, p2);
11889 }
11890
11891 /// Encodes a `xvmod.wu` instruction (requires lasx).
11892 pub inline fn @"xvmod.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11893 return encodeXdXjXk(0x74e70000, p0, p1, p2);
11894 }
11895
11896 /// Encodes a `xvmskgez.b` instruction (requires lasx).
11897 pub inline fn @"xvmskgez.b"(p0: Register, p1: Register) Instruction {
11898 return encodeXdXj(0x769c5000, p0, p1);
11899 }
11900
11901 /// Encodes a `xvmskltz.b` instruction (requires lasx).
11902 pub inline fn @"xvmskltz.b"(p0: Register, p1: Register) Instruction {
11903 return encodeXdXj(0x769c4000, p0, p1);
11904 }
11905
11906 /// Encodes a `xvmskltz.d` instruction (requires lasx).
11907 pub inline fn @"xvmskltz.d"(p0: Register, p1: Register) Instruction {
11908 return encodeXdXj(0x769c4c00, p0, p1);
11909 }
11910
11911 /// Encodes a `xvmskltz.h` instruction (requires lasx).
11912 pub inline fn @"xvmskltz.h"(p0: Register, p1: Register) Instruction {
11913 return encodeXdXj(0x769c4400, p0, p1);
11914 }
11915
11916 /// Encodes a `xvmskltz.w` instruction (requires lasx).
11917 pub inline fn @"xvmskltz.w"(p0: Register, p1: Register) Instruction {
11918 return encodeXdXj(0x769c4800, p0, p1);
11919 }
11920
11921 /// Encodes a `xvmsknz.b` instruction (requires lasx).
11922 pub inline fn @"xvmsknz.b"(p0: Register, p1: Register) Instruction {
11923 return encodeXdXj(0x769c6000, p0, p1);
11924 }
11925
11926 /// Encodes a `xvmsub.b` instruction (requires lasx).
11927 pub inline fn @"xvmsub.b"(p0: Register, p1: Register, p2: Register) Instruction {
11928 return encodeXdXjXk(0x74aa0000, p0, p1, p2);
11929 }
11930
11931 /// Encodes a `xvmsub.d` instruction (requires lasx).
11932 pub inline fn @"xvmsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
11933 return encodeXdXjXk(0x74ab8000, p0, p1, p2);
11934 }
11935
11936 /// Encodes a `xvmsub.h` instruction (requires lasx).
11937 pub inline fn @"xvmsub.h"(p0: Register, p1: Register, p2: Register) Instruction {
11938 return encodeXdXjXk(0x74aa8000, p0, p1, p2);
11939 }
11940
11941 /// Encodes a `xvmsub.w` instruction (requires lasx).
11942 pub inline fn @"xvmsub.w"(p0: Register, p1: Register, p2: Register) Instruction {
11943 return encodeXdXjXk(0x74ab0000, p0, p1, p2);
11944 }
11945
11946 /// Encodes a `xvmuh.b` instruction (requires lasx).
11947 pub inline fn @"xvmuh.b"(p0: Register, p1: Register, p2: Register) Instruction {
11948 return encodeXdXjXk(0x74860000, p0, p1, p2);
11949 }
11950
11951 /// Encodes a `xvmuh.bu` instruction (requires lasx).
11952 pub inline fn @"xvmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction {
11953 return encodeXdXjXk(0x74880000, p0, p1, p2);
11954 }
11955
11956 /// Encodes a `xvmuh.d` instruction (requires lasx).
11957 pub inline fn @"xvmuh.d"(p0: Register, p1: Register, p2: Register) Instruction {
11958 return encodeXdXjXk(0x74878000, p0, p1, p2);
11959 }
11960
11961 /// Encodes a `xvmuh.du` instruction (requires lasx).
11962 pub inline fn @"xvmuh.du"(p0: Register, p1: Register, p2: Register) Instruction {
11963 return encodeXdXjXk(0x74898000, p0, p1, p2);
11964 }
11965
11966 /// Encodes a `xvmuh.h` instruction (requires lasx).
11967 pub inline fn @"xvmuh.h"(p0: Register, p1: Register, p2: Register) Instruction {
11968 return encodeXdXjXk(0x74868000, p0, p1, p2);
11969 }
11970
11971 /// Encodes a `xvmuh.hu` instruction (requires lasx).
11972 pub inline fn @"xvmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction {
11973 return encodeXdXjXk(0x74888000, p0, p1, p2);
11974 }
11975
11976 /// Encodes a `xvmuh.w` instruction (requires lasx).
11977 pub inline fn @"xvmuh.w"(p0: Register, p1: Register, p2: Register) Instruction {
11978 return encodeXdXjXk(0x74870000, p0, p1, p2);
11979 }
11980
11981 /// Encodes a `xvmuh.wu` instruction (requires lasx).
11982 pub inline fn @"xvmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction {
11983 return encodeXdXjXk(0x74890000, p0, p1, p2);
11984 }
11985
11986 /// Encodes a `xvmul.b` instruction (requires lasx).
11987 pub inline fn @"xvmul.b"(p0: Register, p1: Register, p2: Register) Instruction {
11988 return encodeXdXjXk(0x74840000, p0, p1, p2);
11989 }
11990
11991 /// Encodes a `xvmul.d` instruction (requires lasx).
11992 pub inline fn @"xvmul.d"(p0: Register, p1: Register, p2: Register) Instruction {
11993 return encodeXdXjXk(0x74858000, p0, p1, p2);
11994 }
11995
11996 /// Encodes a `xvmul.h` instruction (requires lasx).
11997 pub inline fn @"xvmul.h"(p0: Register, p1: Register, p2: Register) Instruction {
11998 return encodeXdXjXk(0x74848000, p0, p1, p2);
11999 }
12000
12001 /// Encodes a `xvmul.w` instruction (requires lasx).
12002 pub inline fn @"xvmul.w"(p0: Register, p1: Register, p2: Register) Instruction {
12003 return encodeXdXjXk(0x74850000, p0, p1, p2);
12004 }
12005
12006 /// Encodes a `xvmulwev.d.w` instruction (requires lasx).
12007 pub inline fn @"xvmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
12008 return encodeXdXjXk(0x74910000, p0, p1, p2);
12009 }
12010
12011 /// Encodes a `xvmulwev.d.wu` instruction (requires lasx).
12012 pub inline fn @"xvmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
12013 return encodeXdXjXk(0x74990000, p0, p1, p2);
12014 }
12015
12016 /// Encodes a `xvmulwev.d.wu.w` instruction (requires lasx).
12017 pub inline fn @"xvmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
12018 return encodeXdXjXk(0x74a10000, p0, p1, p2);
12019 }
12020
12021 /// Encodes a `xvmulwev.h.b` instruction (requires lasx).
12022 pub inline fn @"xvmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
12023 return encodeXdXjXk(0x74900000, p0, p1, p2);
12024 }
12025
12026 /// Encodes a `xvmulwev.h.bu` instruction (requires lasx).
12027 pub inline fn @"xvmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
12028 return encodeXdXjXk(0x74980000, p0, p1, p2);
12029 }
12030
12031 /// Encodes a `xvmulwev.h.bu.b` instruction (requires lasx).
12032 pub inline fn @"xvmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
12033 return encodeXdXjXk(0x74a00000, p0, p1, p2);
12034 }
12035
12036 /// Encodes a `xvmulwev.q.d` instruction (requires lasx).
12037 pub inline fn @"xvmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
12038 return encodeXdXjXk(0x74918000, p0, p1, p2);
12039 }
12040
12041 /// Encodes a `xvmulwev.q.du` instruction (requires lasx).
12042 pub inline fn @"xvmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
12043 return encodeXdXjXk(0x74998000, p0, p1, p2);
12044 }
12045
12046 /// Encodes a `xvmulwev.q.du.d` instruction (requires lasx).
12047 pub inline fn @"xvmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
12048 return encodeXdXjXk(0x74a18000, p0, p1, p2);
12049 }
12050
12051 /// Encodes a `xvmulwev.w.h` instruction (requires lasx).
12052 pub inline fn @"xvmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
12053 return encodeXdXjXk(0x74908000, p0, p1, p2);
12054 }
12055
12056 /// Encodes a `xvmulwev.w.hu` instruction (requires lasx).
12057 pub inline fn @"xvmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
12058 return encodeXdXjXk(0x74988000, p0, p1, p2);
12059 }
12060
12061 /// Encodes a `xvmulwev.w.hu.h` instruction (requires lasx).
12062 pub inline fn @"xvmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
12063 return encodeXdXjXk(0x74a08000, p0, p1, p2);
12064 }
12065
12066 /// Encodes a `xvmulwod.d.w` instruction (requires lasx).
12067 pub inline fn @"xvmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
12068 return encodeXdXjXk(0x74930000, p0, p1, p2);
12069 }
12070
12071 /// Encodes a `xvmulwod.d.wu` instruction (requires lasx).
12072 pub inline fn @"xvmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
12073 return encodeXdXjXk(0x749b0000, p0, p1, p2);
12074 }
12075
12076 /// Encodes a `xvmulwod.d.wu.w` instruction (requires lasx).
12077 pub inline fn @"xvmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction {
12078 return encodeXdXjXk(0x74a30000, p0, p1, p2);
12079 }
12080
12081 /// Encodes a `xvmulwod.h.b` instruction (requires lasx).
12082 pub inline fn @"xvmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
12083 return encodeXdXjXk(0x74920000, p0, p1, p2);
12084 }
12085
12086 /// Encodes a `xvmulwod.h.bu` instruction (requires lasx).
12087 pub inline fn @"xvmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
12088 return encodeXdXjXk(0x749a0000, p0, p1, p2);
12089 }
12090
12091 /// Encodes a `xvmulwod.h.bu.b` instruction (requires lasx).
12092 pub inline fn @"xvmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction {
12093 return encodeXdXjXk(0x74a20000, p0, p1, p2);
12094 }
12095
12096 /// Encodes a `xvmulwod.q.d` instruction (requires lasx).
12097 pub inline fn @"xvmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
12098 return encodeXdXjXk(0x74938000, p0, p1, p2);
12099 }
12100
12101 /// Encodes a `xvmulwod.q.du` instruction (requires lasx).
12102 pub inline fn @"xvmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
12103 return encodeXdXjXk(0x749b8000, p0, p1, p2);
12104 }
12105
12106 /// Encodes a `xvmulwod.q.du.d` instruction (requires lasx).
12107 pub inline fn @"xvmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction {
12108 return encodeXdXjXk(0x74a38000, p0, p1, p2);
12109 }
12110
12111 /// Encodes a `xvmulwod.w.h` instruction (requires lasx).
12112 pub inline fn @"xvmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
12113 return encodeXdXjXk(0x74928000, p0, p1, p2);
12114 }
12115
12116 /// Encodes a `xvmulwod.w.hu` instruction (requires lasx).
12117 pub inline fn @"xvmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
12118 return encodeXdXjXk(0x749a8000, p0, p1, p2);
12119 }
12120
12121 /// Encodes a `xvmulwod.w.hu.h` instruction (requires lasx).
12122 pub inline fn @"xvmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction {
12123 return encodeXdXjXk(0x74a28000, p0, p1, p2);
12124 }
12125
12126 /// Encodes a `xvneg.b` instruction (requires lasx).
12127 pub inline fn @"xvneg.b"(p0: Register, p1: Register) Instruction {
12128 return encodeXdXj(0x769c3000, p0, p1);
12129 }
12130
12131 /// Encodes a `xvneg.d` instruction (requires lasx).
12132 pub inline fn @"xvneg.d"(p0: Register, p1: Register) Instruction {
12133 return encodeXdXj(0x769c3c00, p0, p1);
12134 }
12135
12136 /// Encodes a `xvneg.h` instruction (requires lasx).
12137 pub inline fn @"xvneg.h"(p0: Register, p1: Register) Instruction {
12138 return encodeXdXj(0x769c3400, p0, p1);
12139 }
12140
12141 /// Encodes a `xvneg.w` instruction (requires lasx).
12142 pub inline fn @"xvneg.w"(p0: Register, p1: Register) Instruction {
12143 return encodeXdXj(0x769c3800, p0, p1);
12144 }
12145
12146 /// Encodes a `xvnor.v` instruction (requires lasx).
12147 pub inline fn @"xvnor.v"(p0: Register, p1: Register, p2: Register) Instruction {
12148 return encodeXdXjXk(0x75278000, p0, p1, p2);
12149 }
12150
12151 /// Encodes a `xvnori.b` instruction (requires lasx).
12152 pub inline fn @"xvnori.b"(p0: Register, p1: Register, p2: u8) Instruction {
12153 return encodeXdXjUk8(0x77dc0000, p0, p1, p2);
12154 }
12155
12156 /// Encodes a `xvor.v` instruction (requires lasx).
12157 pub inline fn @"xvor.v"(p0: Register, p1: Register, p2: Register) Instruction {
12158 return encodeXdXjXk(0x75268000, p0, p1, p2);
12159 }
12160
12161 /// Encodes a `xvori.b` instruction (requires lasx).
12162 pub inline fn @"xvori.b"(p0: Register, p1: Register, p2: u8) Instruction {
12163 return encodeXdXjUk8(0x77d40000, p0, p1, p2);
12164 }
12165
12166 /// Encodes a `xvorn.v` instruction (requires lasx).
12167 pub inline fn @"xvorn.v"(p0: Register, p1: Register, p2: Register) Instruction {
12168 return encodeXdXjXk(0x75288000, p0, p1, p2);
12169 }
12170
12171 /// Encodes a `xvpackev.b` instruction (requires lasx).
12172 pub inline fn @"xvpackev.b"(p0: Register, p1: Register, p2: Register) Instruction {
12173 return encodeXdXjXk(0x75160000, p0, p1, p2);
12174 }
12175
12176 /// Encodes a `xvpackev.d` instruction (requires lasx).
12177 pub inline fn @"xvpackev.d"(p0: Register, p1: Register, p2: Register) Instruction {
12178 return encodeXdXjXk(0x75178000, p0, p1, p2);
12179 }
12180
12181 /// Encodes a `xvpackev.h` instruction (requires lasx).
12182 pub inline fn @"xvpackev.h"(p0: Register, p1: Register, p2: Register) Instruction {
12183 return encodeXdXjXk(0x75168000, p0, p1, p2);
12184 }
12185
12186 /// Encodes a `xvpackev.w` instruction (requires lasx).
12187 pub inline fn @"xvpackev.w"(p0: Register, p1: Register, p2: Register) Instruction {
12188 return encodeXdXjXk(0x75170000, p0, p1, p2);
12189 }
12190
12191 /// Encodes a `xvpackod.b` instruction (requires lasx).
12192 pub inline fn @"xvpackod.b"(p0: Register, p1: Register, p2: Register) Instruction {
12193 return encodeXdXjXk(0x75180000, p0, p1, p2);
12194 }
12195
12196 /// Encodes a `xvpackod.d` instruction (requires lasx).
12197 pub inline fn @"xvpackod.d"(p0: Register, p1: Register, p2: Register) Instruction {
12198 return encodeXdXjXk(0x75198000, p0, p1, p2);
12199 }
12200
12201 /// Encodes a `xvpackod.h` instruction (requires lasx).
12202 pub inline fn @"xvpackod.h"(p0: Register, p1: Register, p2: Register) Instruction {
12203 return encodeXdXjXk(0x75188000, p0, p1, p2);
12204 }
12205
12206 /// Encodes a `xvpackod.w` instruction (requires lasx).
12207 pub inline fn @"xvpackod.w"(p0: Register, p1: Register, p2: Register) Instruction {
12208 return encodeXdXjXk(0x75190000, p0, p1, p2);
12209 }
12210
12211 /// Encodes a `xvpcnt.b` instruction (requires lasx).
12212 pub inline fn @"xvpcnt.b"(p0: Register, p1: Register) Instruction {
12213 return encodeXdXj(0x769c2000, p0, p1);
12214 }
12215
12216 /// Encodes a `xvpcnt.d` instruction (requires lasx).
12217 pub inline fn @"xvpcnt.d"(p0: Register, p1: Register) Instruction {
12218 return encodeXdXj(0x769c2c00, p0, p1);
12219 }
12220
12221 /// Encodes a `xvpcnt.h` instruction (requires lasx).
12222 pub inline fn @"xvpcnt.h"(p0: Register, p1: Register) Instruction {
12223 return encodeXdXj(0x769c2400, p0, p1);
12224 }
12225
12226 /// Encodes a `xvpcnt.w` instruction (requires lasx).
12227 pub inline fn @"xvpcnt.w"(p0: Register, p1: Register) Instruction {
12228 return encodeXdXj(0x769c2800, p0, p1);
12229 }
12230
12231 /// Encodes a `xvperm.w` instruction (requires lasx).
12232 pub inline fn @"xvperm.w"(p0: Register, p1: Register, p2: Register) Instruction {
12233 return encodeXdXjXk(0x757d0000, p0, p1, p2);
12234 }
12235
12236 /// Encodes a `xvpermi.d` instruction (requires lasx).
12237 pub inline fn @"xvpermi.d"(p0: Register, p1: Register, p2: u8) Instruction {
12238 return encodeXdXjUk8(0x77e80000, p0, p1, p2);
12239 }
12240
12241 /// Encodes a `xvpermi.q` instruction (requires lasx).
12242 pub inline fn @"xvpermi.q"(p0: Register, p1: Register, p2: u8) Instruction {
12243 return encodeXdXjUk8(0x77ec0000, p0, p1, p2);
12244 }
12245
12246 /// Encodes a `xvpermi.w` instruction (requires lasx).
12247 pub inline fn @"xvpermi.w"(p0: Register, p1: Register, p2: u8) Instruction {
12248 return encodeXdXjUk8(0x77e40000, p0, p1, p2);
12249 }
12250
12251 /// Encodes a `xvpickev.b` instruction (requires lasx).
12252 pub inline fn @"xvpickev.b"(p0: Register, p1: Register, p2: Register) Instruction {
12253 return encodeXdXjXk(0x751e0000, p0, p1, p2);
12254 }
12255
12256 /// Encodes a `xvpickev.d` instruction (requires lasx).
12257 pub inline fn @"xvpickev.d"(p0: Register, p1: Register, p2: Register) Instruction {
12258 return encodeXdXjXk(0x751f8000, p0, p1, p2);
12259 }
12260
12261 /// Encodes a `xvpickev.h` instruction (requires lasx).
12262 pub inline fn @"xvpickev.h"(p0: Register, p1: Register, p2: Register) Instruction {
12263 return encodeXdXjXk(0x751e8000, p0, p1, p2);
12264 }
12265
12266 /// Encodes a `xvpickev.w` instruction (requires lasx).
12267 pub inline fn @"xvpickev.w"(p0: Register, p1: Register, p2: Register) Instruction {
12268 return encodeXdXjXk(0x751f0000, p0, p1, p2);
12269 }
12270
12271 /// Encodes a `xvpickod.b` instruction (requires lasx).
12272 pub inline fn @"xvpickod.b"(p0: Register, p1: Register, p2: Register) Instruction {
12273 return encodeXdXjXk(0x75200000, p0, p1, p2);
12274 }
12275
12276 /// Encodes a `xvpickod.d` instruction (requires lasx).
12277 pub inline fn @"xvpickod.d"(p0: Register, p1: Register, p2: Register) Instruction {
12278 return encodeXdXjXk(0x75218000, p0, p1, p2);
12279 }
12280
12281 /// Encodes a `xvpickod.h` instruction (requires lasx).
12282 pub inline fn @"xvpickod.h"(p0: Register, p1: Register, p2: Register) Instruction {
12283 return encodeXdXjXk(0x75208000, p0, p1, p2);
12284 }
12285
12286 /// Encodes a `xvpickod.w` instruction (requires lasx).
12287 pub inline fn @"xvpickod.w"(p0: Register, p1: Register, p2: Register) Instruction {
12288 return encodeXdXjXk(0x75210000, p0, p1, p2);
12289 }
12290
12291 /// Encodes a `xvpickve.d` instruction (requires lasx).
12292 pub inline fn @"xvpickve.d"(p0: Register, p1: Register, p2: u2) Instruction {
12293 return encodeXdXjUk2(0x7703e000, p0, p1, p2);
12294 }
12295
12296 /// Encodes a `xvpickve.w` instruction (requires lasx).
12297 pub inline fn @"xvpickve.w"(p0: Register, p1: Register, p2: u3) Instruction {
12298 return encodeXdXjUk3(0x7703c000, p0, p1, p2);
12299 }
12300
12301 /// Encodes a `xvpickve2gr.d` instruction (requires lasx).
12302 pub inline fn @"xvpickve2gr.d"(p0: Register, p1: Register, p2: u2) Instruction {
12303 return encodeDXjUk2(0x76efe000, p0, p1, p2);
12304 }
12305
12306 /// Encodes a `xvpickve2gr.du` instruction (requires lasx).
12307 pub inline fn @"xvpickve2gr.du"(p0: Register, p1: Register, p2: u2) Instruction {
12308 return encodeDXjUk2(0x76f3e000, p0, p1, p2);
12309 }
12310
12311 /// Encodes a `xvpickve2gr.w` instruction (requires lasx).
12312 pub inline fn @"xvpickve2gr.w"(p0: Register, p1: Register, p2: u3) Instruction {
12313 return encodeDXjUk3(0x76efc000, p0, p1, p2);
12314 }
12315
12316 /// Encodes a `xvpickve2gr.wu` instruction (requires lasx).
12317 pub inline fn @"xvpickve2gr.wu"(p0: Register, p1: Register, p2: u3) Instruction {
12318 return encodeDXjUk3(0x76f3c000, p0, p1, p2);
12319 }
12320
12321 /// Encodes a `xvrepl128vei.b` instruction (requires lasx).
12322 pub inline fn @"xvrepl128vei.b"(p0: Register, p1: Register, p2: u4) Instruction {
12323 return encodeXdXjUk4(0x76f78000, p0, p1, p2);
12324 }
12325
12326 /// Encodes a `xvrepl128vei.d` instruction (requires lasx).
12327 pub inline fn @"xvrepl128vei.d"(p0: Register, p1: Register, p2: u1) Instruction {
12328 return encodeXdXjUk1(0x76f7f000, p0, p1, p2);
12329 }
12330
12331 /// Encodes a `xvrepl128vei.h` instruction (requires lasx).
12332 pub inline fn @"xvrepl128vei.h"(p0: Register, p1: Register, p2: u3) Instruction {
12333 return encodeXdXjUk3(0x76f7c000, p0, p1, p2);
12334 }
12335
12336 /// Encodes a `xvrepl128vei.w` instruction (requires lasx).
12337 pub inline fn @"xvrepl128vei.w"(p0: Register, p1: Register, p2: u2) Instruction {
12338 return encodeXdXjUk2(0x76f7e000, p0, p1, p2);
12339 }
12340
12341 /// Encodes a `xvreplgr2vr.b` instruction (requires lasx).
12342 pub inline fn @"xvreplgr2vr.b"(p0: Register, p1: Register) Instruction {
12343 return encodeXdJ(0x769f0000, p0, p1);
12344 }
12345
12346 /// Encodes a `xvreplgr2vr.d` instruction (requires lasx).
12347 pub inline fn @"xvreplgr2vr.d"(p0: Register, p1: Register) Instruction {
12348 return encodeXdJ(0x769f0c00, p0, p1);
12349 }
12350
12351 /// Encodes a `xvreplgr2vr.h` instruction (requires lasx).
12352 pub inline fn @"xvreplgr2vr.h"(p0: Register, p1: Register) Instruction {
12353 return encodeXdJ(0x769f0400, p0, p1);
12354 }
12355
12356 /// Encodes a `xvreplgr2vr.w` instruction (requires lasx).
12357 pub inline fn @"xvreplgr2vr.w"(p0: Register, p1: Register) Instruction {
12358 return encodeXdJ(0x769f0800, p0, p1);
12359 }
12360
12361 /// Encodes a `xvreplve.b` instruction (requires lasx).
12362 pub inline fn @"xvreplve.b"(p0: Register, p1: Register, p2: Register) Instruction {
12363 return encodeXdXjK(0x75220000, p0, p1, p2);
12364 }
12365
12366 /// Encodes a `xvreplve.d` instruction (requires lasx).
12367 pub inline fn @"xvreplve.d"(p0: Register, p1: Register, p2: Register) Instruction {
12368 return encodeXdXjK(0x75238000, p0, p1, p2);
12369 }
12370
12371 /// Encodes a `xvreplve.h` instruction (requires lasx).
12372 pub inline fn @"xvreplve.h"(p0: Register, p1: Register, p2: Register) Instruction {
12373 return encodeXdXjK(0x75228000, p0, p1, p2);
12374 }
12375
12376 /// Encodes a `xvreplve.w` instruction (requires lasx).
12377 pub inline fn @"xvreplve.w"(p0: Register, p1: Register, p2: Register) Instruction {
12378 return encodeXdXjK(0x75230000, p0, p1, p2);
12379 }
12380
12381 /// Encodes a `xvreplve0.b` instruction (requires lasx).
12382 pub inline fn @"xvreplve0.b"(p0: Register, p1: Register) Instruction {
12383 return encodeXdXj(0x77070000, p0, p1);
12384 }
12385
12386 /// Encodes a `xvreplve0.d` instruction (requires lasx).
12387 pub inline fn @"xvreplve0.d"(p0: Register, p1: Register) Instruction {
12388 return encodeXdXj(0x7707e000, p0, p1);
12389 }
12390
12391 /// Encodes a `xvreplve0.h` instruction (requires lasx).
12392 pub inline fn @"xvreplve0.h"(p0: Register, p1: Register) Instruction {
12393 return encodeXdXj(0x77078000, p0, p1);
12394 }
12395
12396 /// Encodes a `xvreplve0.q` instruction (requires lasx).
12397 pub inline fn @"xvreplve0.q"(p0: Register, p1: Register) Instruction {
12398 return encodeXdXj(0x7707f000, p0, p1);
12399 }
12400
12401 /// Encodes a `xvreplve0.w` instruction (requires lasx).
12402 pub inline fn @"xvreplve0.w"(p0: Register, p1: Register) Instruction {
12403 return encodeXdXj(0x7707c000, p0, p1);
12404 }
12405
12406 /// Encodes a `xvrotr.b` instruction (requires lasx).
12407 pub inline fn @"xvrotr.b"(p0: Register, p1: Register, p2: Register) Instruction {
12408 return encodeXdXjXk(0x74ee0000, p0, p1, p2);
12409 }
12410
12411 /// Encodes a `xvrotr.d` instruction (requires lasx).
12412 pub inline fn @"xvrotr.d"(p0: Register, p1: Register, p2: Register) Instruction {
12413 return encodeXdXjXk(0x74ef8000, p0, p1, p2);
12414 }
12415
12416 /// Encodes a `xvrotr.h` instruction (requires lasx).
12417 pub inline fn @"xvrotr.h"(p0: Register, p1: Register, p2: Register) Instruction {
12418 return encodeXdXjXk(0x74ee8000, p0, p1, p2);
12419 }
12420
12421 /// Encodes a `xvrotr.w` instruction (requires lasx).
12422 pub inline fn @"xvrotr.w"(p0: Register, p1: Register, p2: Register) Instruction {
12423 return encodeXdXjXk(0x74ef0000, p0, p1, p2);
12424 }
12425
12426 /// Encodes a `xvrotri.b` instruction (requires lasx).
12427 pub inline fn @"xvrotri.b"(p0: Register, p1: Register, p2: u3) Instruction {
12428 return encodeXdXjUk3(0x76a02000, p0, p1, p2);
12429 }
12430
12431 /// Encodes a `xvrotri.d` instruction (requires lasx).
12432 pub inline fn @"xvrotri.d"(p0: Register, p1: Register, p2: u6) Instruction {
12433 return encodeXdXjUk6(0x76a10000, p0, p1, p2);
12434 }
12435
12436 /// Encodes a `xvrotri.h` instruction (requires lasx).
12437 pub inline fn @"xvrotri.h"(p0: Register, p1: Register, p2: u4) Instruction {
12438 return encodeXdXjUk4(0x76a04000, p0, p1, p2);
12439 }
12440
12441 /// Encodes a `xvrotri.w` instruction (requires lasx).
12442 pub inline fn @"xvrotri.w"(p0: Register, p1: Register, p2: u5) Instruction {
12443 return encodeXdXjUk5(0x76a08000, p0, p1, p2);
12444 }
12445
12446 /// Encodes a `xvsadd.b` instruction (requires lasx).
12447 pub inline fn @"xvsadd.b"(p0: Register, p1: Register, p2: Register) Instruction {
12448 return encodeXdXjXk(0x74460000, p0, p1, p2);
12449 }
12450
12451 /// Encodes a `xvsadd.bu` instruction (requires lasx).
12452 pub inline fn @"xvsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction {
12453 return encodeXdXjXk(0x744a0000, p0, p1, p2);
12454 }
12455
12456 /// Encodes a `xvsadd.d` instruction (requires lasx).
12457 pub inline fn @"xvsadd.d"(p0: Register, p1: Register, p2: Register) Instruction {
12458 return encodeXdXjXk(0x74478000, p0, p1, p2);
12459 }
12460
12461 /// Encodes a `xvsadd.du` instruction (requires lasx).
12462 pub inline fn @"xvsadd.du"(p0: Register, p1: Register, p2: Register) Instruction {
12463 return encodeXdXjXk(0x744b8000, p0, p1, p2);
12464 }
12465
12466 /// Encodes a `xvsadd.h` instruction (requires lasx).
12467 pub inline fn @"xvsadd.h"(p0: Register, p1: Register, p2: Register) Instruction {
12468 return encodeXdXjXk(0x74468000, p0, p1, p2);
12469 }
12470
12471 /// Encodes a `xvsadd.hu` instruction (requires lasx).
12472 pub inline fn @"xvsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction {
12473 return encodeXdXjXk(0x744a8000, p0, p1, p2);
12474 }
12475
12476 /// Encodes a `xvsadd.w` instruction (requires lasx).
12477 pub inline fn @"xvsadd.w"(p0: Register, p1: Register, p2: Register) Instruction {
12478 return encodeXdXjXk(0x74470000, p0, p1, p2);
12479 }
12480
12481 /// Encodes a `xvsadd.wu` instruction (requires lasx).
12482 pub inline fn @"xvsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction {
12483 return encodeXdXjXk(0x744b0000, p0, p1, p2);
12484 }
12485
12486 /// Encodes a `xvsat.b` instruction (requires lasx).
12487 pub inline fn @"xvsat.b"(p0: Register, p1: Register, p2: u3) Instruction {
12488 return encodeXdXjUk3(0x77242000, p0, p1, p2);
12489 }
12490
12491 /// Encodes a `xvsat.bu` instruction (requires lasx).
12492 pub inline fn @"xvsat.bu"(p0: Register, p1: Register, p2: u3) Instruction {
12493 return encodeXdXjUk3(0x77282000, p0, p1, p2);
12494 }
12495
12496 /// Encodes a `xvsat.d` instruction (requires lasx).
12497 pub inline fn @"xvsat.d"(p0: Register, p1: Register, p2: u6) Instruction {
12498 return encodeXdXjUk6(0x77250000, p0, p1, p2);
12499 }
12500
12501 /// Encodes a `xvsat.du` instruction (requires lasx).
12502 pub inline fn @"xvsat.du"(p0: Register, p1: Register, p2: u6) Instruction {
12503 return encodeXdXjUk6(0x77290000, p0, p1, p2);
12504 }
12505
12506 /// Encodes a `xvsat.h` instruction (requires lasx).
12507 pub inline fn @"xvsat.h"(p0: Register, p1: Register, p2: u4) Instruction {
12508 return encodeXdXjUk4(0x77244000, p0, p1, p2);
12509 }
12510
12511 /// Encodes a `xvsat.hu` instruction (requires lasx).
12512 pub inline fn @"xvsat.hu"(p0: Register, p1: Register, p2: u4) Instruction {
12513 return encodeXdXjUk4(0x77284000, p0, p1, p2);
12514 }
12515
12516 /// Encodes a `xvsat.w` instruction (requires lasx).
12517 pub inline fn @"xvsat.w"(p0: Register, p1: Register, p2: u5) Instruction {
12518 return encodeXdXjUk5(0x77248000, p0, p1, p2);
12519 }
12520
12521 /// Encodes a `xvsat.wu` instruction (requires lasx).
12522 pub inline fn @"xvsat.wu"(p0: Register, p1: Register, p2: u5) Instruction {
12523 return encodeXdXjUk5(0x77288000, p0, p1, p2);
12524 }
12525
12526 /// Encodes a `xvseq.b` instruction (requires lasx).
12527 pub inline fn @"xvseq.b"(p0: Register, p1: Register, p2: Register) Instruction {
12528 return encodeXdXjXk(0x74000000, p0, p1, p2);
12529 }
12530
12531 /// Encodes a `xvseq.d` instruction (requires lasx).
12532 pub inline fn @"xvseq.d"(p0: Register, p1: Register, p2: Register) Instruction {
12533 return encodeXdXjXk(0x74018000, p0, p1, p2);
12534 }
12535
12536 /// Encodes a `xvseq.h` instruction (requires lasx).
12537 pub inline fn @"xvseq.h"(p0: Register, p1: Register, p2: Register) Instruction {
12538 return encodeXdXjXk(0x74008000, p0, p1, p2);
12539 }
12540
12541 /// Encodes a `xvseq.w` instruction (requires lasx).
12542 pub inline fn @"xvseq.w"(p0: Register, p1: Register, p2: Register) Instruction {
12543 return encodeXdXjXk(0x74010000, p0, p1, p2);
12544 }
12545
12546 /// Encodes a `xvseqi.b` instruction (requires lasx).
12547 pub inline fn @"xvseqi.b"(p0: Register, p1: Register, p2: i5) Instruction {
12548 return encodeXdXjSk5(0x76800000, p0, p1, p2);
12549 }
12550
12551 /// Encodes a `xvseqi.d` instruction (requires lasx).
12552 pub inline fn @"xvseqi.d"(p0: Register, p1: Register, p2: i5) Instruction {
12553 return encodeXdXjSk5(0x76818000, p0, p1, p2);
12554 }
12555
12556 /// Encodes a `xvseqi.h` instruction (requires lasx).
12557 pub inline fn @"xvseqi.h"(p0: Register, p1: Register, p2: i5) Instruction {
12558 return encodeXdXjSk5(0x76808000, p0, p1, p2);
12559 }
12560
12561 /// Encodes a `xvseqi.w` instruction (requires lasx).
12562 pub inline fn @"xvseqi.w"(p0: Register, p1: Register, p2: i5) Instruction {
12563 return encodeXdXjSk5(0x76810000, p0, p1, p2);
12564 }
12565
12566 /// Encodes a `xvsetallnez.b` instruction (requires f & lasx).
12567 pub inline fn @"xvsetallnez.b"(p0: Register, p1: Register) Instruction {
12568 return encodeCdXj(0x769cb000, p0, p1);
12569 }
12570
12571 /// Encodes a `xvsetallnez.d` instruction (requires f & lasx).
12572 pub inline fn @"xvsetallnez.d"(p0: Register, p1: Register) Instruction {
12573 return encodeCdXj(0x769cbc00, p0, p1);
12574 }
12575
12576 /// Encodes a `xvsetallnez.h` instruction (requires f & lasx).
12577 pub inline fn @"xvsetallnez.h"(p0: Register, p1: Register) Instruction {
12578 return encodeCdXj(0x769cb400, p0, p1);
12579 }
12580
12581 /// Encodes a `xvsetallnez.w` instruction (requires f & lasx).
12582 pub inline fn @"xvsetallnez.w"(p0: Register, p1: Register) Instruction {
12583 return encodeCdXj(0x769cb800, p0, p1);
12584 }
12585
12586 /// Encodes a `xvsetanyeqz.b` instruction (requires f & lasx).
12587 pub inline fn @"xvsetanyeqz.b"(p0: Register, p1: Register) Instruction {
12588 return encodeCdXj(0x769ca000, p0, p1);
12589 }
12590
12591 /// Encodes a `xvsetanyeqz.d` instruction (requires f & lasx).
12592 pub inline fn @"xvsetanyeqz.d"(p0: Register, p1: Register) Instruction {
12593 return encodeCdXj(0x769cac00, p0, p1);
12594 }
12595
12596 /// Encodes a `xvsetanyeqz.h` instruction (requires f & lasx).
12597 pub inline fn @"xvsetanyeqz.h"(p0: Register, p1: Register) Instruction {
12598 return encodeCdXj(0x769ca400, p0, p1);
12599 }
12600
12601 /// Encodes a `xvsetanyeqz.w` instruction (requires f & lasx).
12602 pub inline fn @"xvsetanyeqz.w"(p0: Register, p1: Register) Instruction {
12603 return encodeCdXj(0x769ca800, p0, p1);
12604 }
12605
12606 /// Encodes a `xvseteqz.v` instruction (requires f & lasx).
12607 pub inline fn @"xvseteqz.v"(p0: Register, p1: Register) Instruction {
12608 return encodeCdXj(0x769c9800, p0, p1);
12609 }
12610
12611 /// Encodes a `xvsetnez.v` instruction (requires f & lasx).
12612 pub inline fn @"xvsetnez.v"(p0: Register, p1: Register) Instruction {
12613 return encodeCdXj(0x769c9c00, p0, p1);
12614 }
12615
12616 /// Encodes a `xvshuf.b` instruction (requires lasx).
12617 pub inline fn @"xvshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction {
12618 return encodeXdXjXkXa(0x0d600000, p0, p1, p2, p3);
12619 }
12620
12621 /// Encodes a `xvshuf.d` instruction (requires lasx).
12622 pub inline fn @"xvshuf.d"(p0: Register, p1: Register, p2: Register) Instruction {
12623 return encodeXdXjXk(0x757b8000, p0, p1, p2);
12624 }
12625
12626 /// Encodes a `xvshuf.h` instruction (requires lasx).
12627 pub inline fn @"xvshuf.h"(p0: Register, p1: Register, p2: Register) Instruction {
12628 return encodeXdXjXk(0x757a8000, p0, p1, p2);
12629 }
12630
12631 /// Encodes a `xvshuf.w` instruction (requires lasx).
12632 pub inline fn @"xvshuf.w"(p0: Register, p1: Register, p2: Register) Instruction {
12633 return encodeXdXjXk(0x757b0000, p0, p1, p2);
12634 }
12635
12636 /// Encodes a `xvshuf4i.b` instruction (requires lasx).
12637 pub inline fn @"xvshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction {
12638 return encodeXdXjUk8(0x77900000, p0, p1, p2);
12639 }
12640
12641 /// Encodes a `xvshuf4i.d` instruction (requires lasx).
12642 pub inline fn @"xvshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction {
12643 return encodeXdXjUk8(0x779c0000, p0, p1, p2);
12644 }
12645
12646 /// Encodes a `xvshuf4i.h` instruction (requires lasx).
12647 pub inline fn @"xvshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction {
12648 return encodeXdXjUk8(0x77940000, p0, p1, p2);
12649 }
12650
12651 /// Encodes a `xvshuf4i.w` instruction (requires lasx).
12652 pub inline fn @"xvshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction {
12653 return encodeXdXjUk8(0x77980000, p0, p1, p2);
12654 }
12655
12656 /// Encodes a `xvsigncov.b` instruction (requires lasx).
12657 pub inline fn @"xvsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction {
12658 return encodeXdXjXk(0x752e0000, p0, p1, p2);
12659 }
12660
12661 /// Encodes a `xvsigncov.d` instruction (requires lasx).
12662 pub inline fn @"xvsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction {
12663 return encodeXdXjXk(0x752f8000, p0, p1, p2);
12664 }
12665
12666 /// Encodes a `xvsigncov.h` instruction (requires lasx).
12667 pub inline fn @"xvsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction {
12668 return encodeXdXjXk(0x752e8000, p0, p1, p2);
12669 }
12670
12671 /// Encodes a `xvsigncov.w` instruction (requires lasx).
12672 pub inline fn @"xvsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction {
12673 return encodeXdXjXk(0x752f0000, p0, p1, p2);
12674 }
12675
12676 /// Encodes a `xvsle.b` instruction (requires lasx).
12677 pub inline fn @"xvsle.b"(p0: Register, p1: Register, p2: Register) Instruction {
12678 return encodeXdXjXk(0x74020000, p0, p1, p2);
12679 }
12680
12681 /// Encodes a `xvsle.bu` instruction (requires lasx).
12682 pub inline fn @"xvsle.bu"(p0: Register, p1: Register, p2: Register) Instruction {
12683 return encodeXdXjXk(0x74040000, p0, p1, p2);
12684 }
12685
12686 /// Encodes a `xvsle.d` instruction (requires lasx).
12687 pub inline fn @"xvsle.d"(p0: Register, p1: Register, p2: Register) Instruction {
12688 return encodeXdXjXk(0x74038000, p0, p1, p2);
12689 }
12690
12691 /// Encodes a `xvsle.du` instruction (requires lasx).
12692 pub inline fn @"xvsle.du"(p0: Register, p1: Register, p2: Register) Instruction {
12693 return encodeXdXjXk(0x74058000, p0, p1, p2);
12694 }
12695
12696 /// Encodes a `xvsle.h` instruction (requires lasx).
12697 pub inline fn @"xvsle.h"(p0: Register, p1: Register, p2: Register) Instruction {
12698 return encodeXdXjXk(0x74028000, p0, p1, p2);
12699 }
12700
12701 /// Encodes a `xvsle.hu` instruction (requires lasx).
12702 pub inline fn @"xvsle.hu"(p0: Register, p1: Register, p2: Register) Instruction {
12703 return encodeXdXjXk(0x74048000, p0, p1, p2);
12704 }
12705
12706 /// Encodes a `xvsle.w` instruction (requires lasx).
12707 pub inline fn @"xvsle.w"(p0: Register, p1: Register, p2: Register) Instruction {
12708 return encodeXdXjXk(0x74030000, p0, p1, p2);
12709 }
12710
12711 /// Encodes a `xvsle.wu` instruction (requires lasx).
12712 pub inline fn @"xvsle.wu"(p0: Register, p1: Register, p2: Register) Instruction {
12713 return encodeXdXjXk(0x74050000, p0, p1, p2);
12714 }
12715
12716 /// Encodes a `xvslei.b` instruction (requires lasx).
12717 pub inline fn @"xvslei.b"(p0: Register, p1: Register, p2: i5) Instruction {
12718 return encodeXdXjSk5(0x76820000, p0, p1, p2);
12719 }
12720
12721 /// Encodes a `xvslei.bu` instruction (requires lasx).
12722 pub inline fn @"xvslei.bu"(p0: Register, p1: Register, p2: u5) Instruction {
12723 return encodeXdXjUk5(0x76840000, p0, p1, p2);
12724 }
12725
12726 /// Encodes a `xvslei.d` instruction (requires lasx).
12727 pub inline fn @"xvslei.d"(p0: Register, p1: Register, p2: i5) Instruction {
12728 return encodeXdXjSk5(0x76838000, p0, p1, p2);
12729 }
12730
12731 /// Encodes a `xvslei.du` instruction (requires lasx).
12732 pub inline fn @"xvslei.du"(p0: Register, p1: Register, p2: u5) Instruction {
12733 return encodeXdXjUk5(0x76858000, p0, p1, p2);
12734 }
12735
12736 /// Encodes a `xvslei.h` instruction (requires lasx).
12737 pub inline fn @"xvslei.h"(p0: Register, p1: Register, p2: i5) Instruction {
12738 return encodeXdXjSk5(0x76828000, p0, p1, p2);
12739 }
12740
12741 /// Encodes a `xvslei.hu` instruction (requires lasx).
12742 pub inline fn @"xvslei.hu"(p0: Register, p1: Register, p2: u5) Instruction {
12743 return encodeXdXjUk5(0x76848000, p0, p1, p2);
12744 }
12745
12746 /// Encodes a `xvslei.w` instruction (requires lasx).
12747 pub inline fn @"xvslei.w"(p0: Register, p1: Register, p2: i5) Instruction {
12748 return encodeXdXjSk5(0x76830000, p0, p1, p2);
12749 }
12750
12751 /// Encodes a `xvslei.wu` instruction (requires lasx).
12752 pub inline fn @"xvslei.wu"(p0: Register, p1: Register, p2: u5) Instruction {
12753 return encodeXdXjUk5(0x76850000, p0, p1, p2);
12754 }
12755
12756 /// Encodes a `xvsll.b` instruction (requires lasx).
12757 pub inline fn @"xvsll.b"(p0: Register, p1: Register, p2: Register) Instruction {
12758 return encodeXdXjXk(0x74e80000, p0, p1, p2);
12759 }
12760
12761 /// Encodes a `xvsll.d` instruction (requires lasx).
12762 pub inline fn @"xvsll.d"(p0: Register, p1: Register, p2: Register) Instruction {
12763 return encodeXdXjXk(0x74e98000, p0, p1, p2);
12764 }
12765
12766 /// Encodes a `xvsll.h` instruction (requires lasx).
12767 pub inline fn @"xvsll.h"(p0: Register, p1: Register, p2: Register) Instruction {
12768 return encodeXdXjXk(0x74e88000, p0, p1, p2);
12769 }
12770
12771 /// Encodes a `xvsll.w` instruction (requires lasx).
12772 pub inline fn @"xvsll.w"(p0: Register, p1: Register, p2: Register) Instruction {
12773 return encodeXdXjXk(0x74e90000, p0, p1, p2);
12774 }
12775
12776 /// Encodes a `xvslli.b` instruction (requires lasx).
12777 pub inline fn @"xvslli.b"(p0: Register, p1: Register, p2: u3) Instruction {
12778 return encodeXdXjUk3(0x772c2000, p0, p1, p2);
12779 }
12780
12781 /// Encodes a `xvslli.d` instruction (requires lasx).
12782 pub inline fn @"xvslli.d"(p0: Register, p1: Register, p2: u6) Instruction {
12783 return encodeXdXjUk6(0x772d0000, p0, p1, p2);
12784 }
12785
12786 /// Encodes a `xvslli.h` instruction (requires lasx).
12787 pub inline fn @"xvslli.h"(p0: Register, p1: Register, p2: u4) Instruction {
12788 return encodeXdXjUk4(0x772c4000, p0, p1, p2);
12789 }
12790
12791 /// Encodes a `xvslli.w` instruction (requires lasx).
12792 pub inline fn @"xvslli.w"(p0: Register, p1: Register, p2: u5) Instruction {
12793 return encodeXdXjUk5(0x772c8000, p0, p1, p2);
12794 }
12795
12796 /// Encodes a `xvsllwil.d.w` instruction (requires lasx).
12797 pub inline fn @"xvsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction {
12798 return encodeXdXjUk5(0x77088000, p0, p1, p2);
12799 }
12800
12801 /// Encodes a `xvsllwil.du.wu` instruction (requires lasx).
12802 pub inline fn @"xvsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction {
12803 return encodeXdXjUk5(0x770c8000, p0, p1, p2);
12804 }
12805
12806 /// Encodes a `xvsllwil.h.b` instruction (requires lasx).
12807 pub inline fn @"xvsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction {
12808 return encodeXdXjUk3(0x77082000, p0, p1, p2);
12809 }
12810
12811 /// Encodes a `xvsllwil.hu.bu` instruction (requires lasx).
12812 pub inline fn @"xvsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction {
12813 return encodeXdXjUk3(0x770c2000, p0, p1, p2);
12814 }
12815
12816 /// Encodes a `xvsllwil.w.h` instruction (requires lasx).
12817 pub inline fn @"xvsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction {
12818 return encodeXdXjUk4(0x77084000, p0, p1, p2);
12819 }
12820
12821 /// Encodes a `xvsllwil.wu.hu` instruction (requires lasx).
12822 pub inline fn @"xvsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction {
12823 return encodeXdXjUk4(0x770c4000, p0, p1, p2);
12824 }
12825
12826 /// Encodes a `xvslt.b` instruction (requires lasx).
12827 pub inline fn @"xvslt.b"(p0: Register, p1: Register, p2: Register) Instruction {
12828 return encodeXdXjXk(0x74060000, p0, p1, p2);
12829 }
12830
12831 /// Encodes a `xvslt.bu` instruction (requires lasx).
12832 pub inline fn @"xvslt.bu"(p0: Register, p1: Register, p2: Register) Instruction {
12833 return encodeXdXjXk(0x74080000, p0, p1, p2);
12834 }
12835
12836 /// Encodes a `xvslt.d` instruction (requires lasx).
12837 pub inline fn @"xvslt.d"(p0: Register, p1: Register, p2: Register) Instruction {
12838 return encodeXdXjXk(0x74078000, p0, p1, p2);
12839 }
12840
12841 /// Encodes a `xvslt.du` instruction (requires lasx).
12842 pub inline fn @"xvslt.du"(p0: Register, p1: Register, p2: Register) Instruction {
12843 return encodeXdXjXk(0x74098000, p0, p1, p2);
12844 }
12845
12846 /// Encodes a `xvslt.h` instruction (requires lasx).
12847 pub inline fn @"xvslt.h"(p0: Register, p1: Register, p2: Register) Instruction {
12848 return encodeXdXjXk(0x74068000, p0, p1, p2);
12849 }
12850
12851 /// Encodes a `xvslt.hu` instruction (requires lasx).
12852 pub inline fn @"xvslt.hu"(p0: Register, p1: Register, p2: Register) Instruction {
12853 return encodeXdXjXk(0x74088000, p0, p1, p2);
12854 }
12855
12856 /// Encodes a `xvslt.w` instruction (requires lasx).
12857 pub inline fn @"xvslt.w"(p0: Register, p1: Register, p2: Register) Instruction {
12858 return encodeXdXjXk(0x74070000, p0, p1, p2);
12859 }
12860
12861 /// Encodes a `xvslt.wu` instruction (requires lasx).
12862 pub inline fn @"xvslt.wu"(p0: Register, p1: Register, p2: Register) Instruction {
12863 return encodeXdXjXk(0x74090000, p0, p1, p2);
12864 }
12865
12866 /// Encodes a `xvslti.b` instruction (requires lasx).
12867 pub inline fn @"xvslti.b"(p0: Register, p1: Register, p2: i5) Instruction {
12868 return encodeXdXjSk5(0x76860000, p0, p1, p2);
12869 }
12870
12871 /// Encodes a `xvslti.bu` instruction (requires lasx).
12872 pub inline fn @"xvslti.bu"(p0: Register, p1: Register, p2: u5) Instruction {
12873 return encodeXdXjUk5(0x76880000, p0, p1, p2);
12874 }
12875
12876 /// Encodes a `xvslti.d` instruction (requires lasx).
12877 pub inline fn @"xvslti.d"(p0: Register, p1: Register, p2: i5) Instruction {
12878 return encodeXdXjSk5(0x76878000, p0, p1, p2);
12879 }
12880
12881 /// Encodes a `xvslti.du` instruction (requires lasx).
12882 pub inline fn @"xvslti.du"(p0: Register, p1: Register, p2: u5) Instruction {
12883 return encodeXdXjUk5(0x76898000, p0, p1, p2);
12884 }
12885
12886 /// Encodes a `xvslti.h` instruction (requires lasx).
12887 pub inline fn @"xvslti.h"(p0: Register, p1: Register, p2: i5) Instruction {
12888 return encodeXdXjSk5(0x76868000, p0, p1, p2);
12889 }
12890
12891 /// Encodes a `xvslti.hu` instruction (requires lasx).
12892 pub inline fn @"xvslti.hu"(p0: Register, p1: Register, p2: u5) Instruction {
12893 return encodeXdXjUk5(0x76888000, p0, p1, p2);
12894 }
12895
12896 /// Encodes a `xvslti.w` instruction (requires lasx).
12897 pub inline fn @"xvslti.w"(p0: Register, p1: Register, p2: i5) Instruction {
12898 return encodeXdXjSk5(0x76870000, p0, p1, p2);
12899 }
12900
12901 /// Encodes a `xvslti.wu` instruction (requires lasx).
12902 pub inline fn @"xvslti.wu"(p0: Register, p1: Register, p2: u5) Instruction {
12903 return encodeXdXjUk5(0x76890000, p0, p1, p2);
12904 }
12905
12906 /// Encodes a `xvsra.b` instruction (requires lasx).
12907 pub inline fn @"xvsra.b"(p0: Register, p1: Register, p2: Register) Instruction {
12908 return encodeXdXjXk(0x74ec0000, p0, p1, p2);
12909 }
12910
12911 /// Encodes a `xvsra.d` instruction (requires lasx).
12912 pub inline fn @"xvsra.d"(p0: Register, p1: Register, p2: Register) Instruction {
12913 return encodeXdXjXk(0x74ed8000, p0, p1, p2);
12914 }
12915
12916 /// Encodes a `xvsra.h` instruction (requires lasx).
12917 pub inline fn @"xvsra.h"(p0: Register, p1: Register, p2: Register) Instruction {
12918 return encodeXdXjXk(0x74ec8000, p0, p1, p2);
12919 }
12920
12921 /// Encodes a `xvsra.w` instruction (requires lasx).
12922 pub inline fn @"xvsra.w"(p0: Register, p1: Register, p2: Register) Instruction {
12923 return encodeXdXjXk(0x74ed0000, p0, p1, p2);
12924 }
12925
12926 /// Encodes a `xvsrai.b` instruction (requires lasx).
12927 pub inline fn @"xvsrai.b"(p0: Register, p1: Register, p2: u3) Instruction {
12928 return encodeXdXjUk3(0x77342000, p0, p1, p2);
12929 }
12930
12931 /// Encodes a `xvsrai.d` instruction (requires lasx).
12932 pub inline fn @"xvsrai.d"(p0: Register, p1: Register, p2: u6) Instruction {
12933 return encodeXdXjUk6(0x77350000, p0, p1, p2);
12934 }
12935
12936 /// Encodes a `xvsrai.h` instruction (requires lasx).
12937 pub inline fn @"xvsrai.h"(p0: Register, p1: Register, p2: u4) Instruction {
12938 return encodeXdXjUk4(0x77344000, p0, p1, p2);
12939 }
12940
12941 /// Encodes a `xvsrai.w` instruction (requires lasx).
12942 pub inline fn @"xvsrai.w"(p0: Register, p1: Register, p2: u5) Instruction {
12943 return encodeXdXjUk5(0x77348000, p0, p1, p2);
12944 }
12945
12946 /// Encodes a `xvsran.b.h` instruction (requires lasx).
12947 pub inline fn @"xvsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
12948 return encodeXdXjXk(0x74f68000, p0, p1, p2);
12949 }
12950
12951 /// Encodes a `xvsran.h.w` instruction (requires lasx).
12952 pub inline fn @"xvsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
12953 return encodeXdXjXk(0x74f70000, p0, p1, p2);
12954 }
12955
12956 /// Encodes a `xvsran.w.d` instruction (requires lasx).
12957 pub inline fn @"xvsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
12958 return encodeXdXjXk(0x74f78000, p0, p1, p2);
12959 }
12960
12961 /// Encodes a `xvsrani.b.h` instruction (requires lasx).
12962 pub inline fn @"xvsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
12963 return encodeXdXjUk4(0x77584000, p0, p1, p2);
12964 }
12965
12966 /// Encodes a `xvsrani.d.q` instruction (requires lasx).
12967 pub inline fn @"xvsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
12968 return encodeXdXjUk7(0x775a0000, p0, p1, p2);
12969 }
12970
12971 /// Encodes a `xvsrani.h.w` instruction (requires lasx).
12972 pub inline fn @"xvsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
12973 return encodeXdXjUk5(0x77588000, p0, p1, p2);
12974 }
12975
12976 /// Encodes a `xvsrani.w.d` instruction (requires lasx).
12977 pub inline fn @"xvsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
12978 return encodeXdXjUk6(0x77590000, p0, p1, p2);
12979 }
12980
12981 /// Encodes a `xvsrar.b` instruction (requires lasx).
12982 pub inline fn @"xvsrar.b"(p0: Register, p1: Register, p2: Register) Instruction {
12983 return encodeXdXjXk(0x74f20000, p0, p1, p2);
12984 }
12985
12986 /// Encodes a `xvsrar.d` instruction (requires lasx).
12987 pub inline fn @"xvsrar.d"(p0: Register, p1: Register, p2: Register) Instruction {
12988 return encodeXdXjXk(0x74f38000, p0, p1, p2);
12989 }
12990
12991 /// Encodes a `xvsrar.h` instruction (requires lasx).
12992 pub inline fn @"xvsrar.h"(p0: Register, p1: Register, p2: Register) Instruction {
12993 return encodeXdXjXk(0x74f28000, p0, p1, p2);
12994 }
12995
12996 /// Encodes a `xvsrar.w` instruction (requires lasx).
12997 pub inline fn @"xvsrar.w"(p0: Register, p1: Register, p2: Register) Instruction {
12998 return encodeXdXjXk(0x74f30000, p0, p1, p2);
12999 }
13000
13001 /// Encodes a `xvsrari.b` instruction (requires lasx).
13002 pub inline fn @"xvsrari.b"(p0: Register, p1: Register, p2: u3) Instruction {
13003 return encodeXdXjUk3(0x76a82000, p0, p1, p2);
13004 }
13005
13006 /// Encodes a `xvsrari.d` instruction (requires lasx).
13007 pub inline fn @"xvsrari.d"(p0: Register, p1: Register, p2: u6) Instruction {
13008 return encodeXdXjUk6(0x76a90000, p0, p1, p2);
13009 }
13010
13011 /// Encodes a `xvsrari.h` instruction (requires lasx).
13012 pub inline fn @"xvsrari.h"(p0: Register, p1: Register, p2: u4) Instruction {
13013 return encodeXdXjUk4(0x76a84000, p0, p1, p2);
13014 }
13015
13016 /// Encodes a `xvsrari.w` instruction (requires lasx).
13017 pub inline fn @"xvsrari.w"(p0: Register, p1: Register, p2: u5) Instruction {
13018 return encodeXdXjUk5(0x76a88000, p0, p1, p2);
13019 }
13020
13021 /// Encodes a `xvsrarn.b.h` instruction (requires lasx).
13022 pub inline fn @"xvsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13023 return encodeXdXjXk(0x74fa8000, p0, p1, p2);
13024 }
13025
13026 /// Encodes a `xvsrarn.h.w` instruction (requires lasx).
13027 pub inline fn @"xvsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13028 return encodeXdXjXk(0x74fb0000, p0, p1, p2);
13029 }
13030
13031 /// Encodes a `xvsrarn.w.d` instruction (requires lasx).
13032 pub inline fn @"xvsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13033 return encodeXdXjXk(0x74fb8000, p0, p1, p2);
13034 }
13035
13036 /// Encodes a `xvsrarni.b.h` instruction (requires lasx).
13037 pub inline fn @"xvsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13038 return encodeXdXjUk4(0x775c4000, p0, p1, p2);
13039 }
13040
13041 /// Encodes a `xvsrarni.d.q` instruction (requires lasx).
13042 pub inline fn @"xvsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13043 return encodeXdXjUk7(0x775e0000, p0, p1, p2);
13044 }
13045
13046 /// Encodes a `xvsrarni.h.w` instruction (requires lasx).
13047 pub inline fn @"xvsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13048 return encodeXdXjUk5(0x775c8000, p0, p1, p2);
13049 }
13050
13051 /// Encodes a `xvsrarni.w.d` instruction (requires lasx).
13052 pub inline fn @"xvsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13053 return encodeXdXjUk6(0x775d0000, p0, p1, p2);
13054 }
13055
13056 /// Encodes a `xvsrl.b` instruction (requires lasx).
13057 pub inline fn @"xvsrl.b"(p0: Register, p1: Register, p2: Register) Instruction {
13058 return encodeXdXjXk(0x74ea0000, p0, p1, p2);
13059 }
13060
13061 /// Encodes a `xvsrl.d` instruction (requires lasx).
13062 pub inline fn @"xvsrl.d"(p0: Register, p1: Register, p2: Register) Instruction {
13063 return encodeXdXjXk(0x74eb8000, p0, p1, p2);
13064 }
13065
13066 /// Encodes a `xvsrl.h` instruction (requires lasx).
13067 pub inline fn @"xvsrl.h"(p0: Register, p1: Register, p2: Register) Instruction {
13068 return encodeXdXjXk(0x74ea8000, p0, p1, p2);
13069 }
13070
13071 /// Encodes a `xvsrl.w` instruction (requires lasx).
13072 pub inline fn @"xvsrl.w"(p0: Register, p1: Register, p2: Register) Instruction {
13073 return encodeXdXjXk(0x74eb0000, p0, p1, p2);
13074 }
13075
13076 /// Encodes a `xvsrli.b` instruction (requires lasx).
13077 pub inline fn @"xvsrli.b"(p0: Register, p1: Register, p2: u3) Instruction {
13078 return encodeXdXjUk3(0x77302000, p0, p1, p2);
13079 }
13080
13081 /// Encodes a `xvsrli.d` instruction (requires lasx).
13082 pub inline fn @"xvsrli.d"(p0: Register, p1: Register, p2: u6) Instruction {
13083 return encodeXdXjUk6(0x77310000, p0, p1, p2);
13084 }
13085
13086 /// Encodes a `xvsrli.h` instruction (requires lasx).
13087 pub inline fn @"xvsrli.h"(p0: Register, p1: Register, p2: u4) Instruction {
13088 return encodeXdXjUk4(0x77304000, p0, p1, p2);
13089 }
13090
13091 /// Encodes a `xvsrli.w` instruction (requires lasx).
13092 pub inline fn @"xvsrli.w"(p0: Register, p1: Register, p2: u5) Instruction {
13093 return encodeXdXjUk5(0x77308000, p0, p1, p2);
13094 }
13095
13096 /// Encodes a `xvsrln.b.h` instruction (requires lasx).
13097 pub inline fn @"xvsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13098 return encodeXdXjXk(0x74f48000, p0, p1, p2);
13099 }
13100
13101 /// Encodes a `xvsrln.h.w` instruction (requires lasx).
13102 pub inline fn @"xvsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13103 return encodeXdXjXk(0x74f50000, p0, p1, p2);
13104 }
13105
13106 /// Encodes a `xvsrln.w.d` instruction (requires lasx).
13107 pub inline fn @"xvsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13108 return encodeXdXjXk(0x74f58000, p0, p1, p2);
13109 }
13110
13111 /// Encodes a `xvsrlni.b.h` instruction (requires lasx).
13112 pub inline fn @"xvsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13113 return encodeXdXjUk4(0x77404000, p0, p1, p2);
13114 }
13115
13116 /// Encodes a `xvsrlni.d.q` instruction (requires lasx).
13117 pub inline fn @"xvsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13118 return encodeXdXjUk7(0x77420000, p0, p1, p2);
13119 }
13120
13121 /// Encodes a `xvsrlni.h.w` instruction (requires lasx).
13122 pub inline fn @"xvsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13123 return encodeXdXjUk5(0x77408000, p0, p1, p2);
13124 }
13125
13126 /// Encodes a `xvsrlni.w.d` instruction (requires lasx).
13127 pub inline fn @"xvsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13128 return encodeXdXjUk6(0x77410000, p0, p1, p2);
13129 }
13130
13131 /// Encodes a `xvsrlr.b` instruction (requires lasx).
13132 pub inline fn @"xvsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction {
13133 return encodeXdXjXk(0x74f00000, p0, p1, p2);
13134 }
13135
13136 /// Encodes a `xvsrlr.d` instruction (requires lasx).
13137 pub inline fn @"xvsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction {
13138 return encodeXdXjXk(0x74f18000, p0, p1, p2);
13139 }
13140
13141 /// Encodes a `xvsrlr.h` instruction (requires lasx).
13142 pub inline fn @"xvsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction {
13143 return encodeXdXjXk(0x74f08000, p0, p1, p2);
13144 }
13145
13146 /// Encodes a `xvsrlr.w` instruction (requires lasx).
13147 pub inline fn @"xvsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction {
13148 return encodeXdXjXk(0x74f10000, p0, p1, p2);
13149 }
13150
13151 /// Encodes a `xvsrlri.b` instruction (requires lasx).
13152 pub inline fn @"xvsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction {
13153 return encodeXdXjUk3(0x76a42000, p0, p1, p2);
13154 }
13155
13156 /// Encodes a `xvsrlri.d` instruction (requires lasx).
13157 pub inline fn @"xvsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction {
13158 return encodeXdXjUk6(0x76a50000, p0, p1, p2);
13159 }
13160
13161 /// Encodes a `xvsrlri.h` instruction (requires lasx).
13162 pub inline fn @"xvsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction {
13163 return encodeXdXjUk4(0x76a44000, p0, p1, p2);
13164 }
13165
13166 /// Encodes a `xvsrlri.w` instruction (requires lasx).
13167 pub inline fn @"xvsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction {
13168 return encodeXdXjUk5(0x76a48000, p0, p1, p2);
13169 }
13170
13171 /// Encodes a `xvsrlrn.b.h` instruction (requires lasx).
13172 pub inline fn @"xvsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13173 return encodeXdXjXk(0x74f88000, p0, p1, p2);
13174 }
13175
13176 /// Encodes a `xvsrlrn.h.w` instruction (requires lasx).
13177 pub inline fn @"xvsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13178 return encodeXdXjXk(0x74f90000, p0, p1, p2);
13179 }
13180
13181 /// Encodes a `xvsrlrn.w.d` instruction (requires lasx).
13182 pub inline fn @"xvsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13183 return encodeXdXjXk(0x74f98000, p0, p1, p2);
13184 }
13185
13186 /// Encodes a `xvsrlrni.b.h` instruction (requires lasx).
13187 pub inline fn @"xvsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13188 return encodeXdXjUk4(0x77444000, p0, p1, p2);
13189 }
13190
13191 /// Encodes a `xvsrlrni.d.q` instruction (requires lasx).
13192 pub inline fn @"xvsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13193 return encodeXdXjUk7(0x77460000, p0, p1, p2);
13194 }
13195
13196 /// Encodes a `xvsrlrni.h.w` instruction (requires lasx).
13197 pub inline fn @"xvsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13198 return encodeXdXjUk5(0x77448000, p0, p1, p2);
13199 }
13200
13201 /// Encodes a `xvsrlrni.w.d` instruction (requires lasx).
13202 pub inline fn @"xvsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13203 return encodeXdXjUk6(0x77450000, p0, p1, p2);
13204 }
13205
13206 /// Encodes a `xvssran.b.h` instruction (requires lasx).
13207 pub inline fn @"xvssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13208 return encodeXdXjXk(0x74fe8000, p0, p1, p2);
13209 }
13210
13211 /// Encodes a `xvssran.bu.h` instruction (requires lasx).
13212 pub inline fn @"xvssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
13213 return encodeXdXjXk(0x75068000, p0, p1, p2);
13214 }
13215
13216 /// Encodes a `xvssran.h.w` instruction (requires lasx).
13217 pub inline fn @"xvssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13218 return encodeXdXjXk(0x74ff0000, p0, p1, p2);
13219 }
13220
13221 /// Encodes a `xvssran.hu.w` instruction (requires lasx).
13222 pub inline fn @"xvssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
13223 return encodeXdXjXk(0x75070000, p0, p1, p2);
13224 }
13225
13226 /// Encodes a `xvssran.w.d` instruction (requires lasx).
13227 pub inline fn @"xvssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13228 return encodeXdXjXk(0x74ff8000, p0, p1, p2);
13229 }
13230
13231 /// Encodes a `xvssran.wu.d` instruction (requires lasx).
13232 pub inline fn @"xvssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
13233 return encodeXdXjXk(0x75078000, p0, p1, p2);
13234 }
13235
13236 /// Encodes a `xvssrani.b.h` instruction (requires lasx).
13237 pub inline fn @"xvssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13238 return encodeXdXjUk4(0x77604000, p0, p1, p2);
13239 }
13240
13241 /// Encodes a `xvssrani.bu.h` instruction (requires lasx).
13242 pub inline fn @"xvssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
13243 return encodeXdXjUk4(0x77644000, p0, p1, p2);
13244 }
13245
13246 /// Encodes a `xvssrani.d.q` instruction (requires lasx).
13247 pub inline fn @"xvssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13248 return encodeXdXjUk7(0x77620000, p0, p1, p2);
13249 }
13250
13251 /// Encodes a `xvssrani.du.q` instruction (requires lasx).
13252 pub inline fn @"xvssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
13253 return encodeXdXjUk7(0x77660000, p0, p1, p2);
13254 }
13255
13256 /// Encodes a `xvssrani.h.w` instruction (requires lasx).
13257 pub inline fn @"xvssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13258 return encodeXdXjUk5(0x77608000, p0, p1, p2);
13259 }
13260
13261 /// Encodes a `xvssrani.hu.w` instruction (requires lasx).
13262 pub inline fn @"xvssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
13263 return encodeXdXjUk5(0x77648000, p0, p1, p2);
13264 }
13265
13266 /// Encodes a `xvssrani.w.d` instruction (requires lasx).
13267 pub inline fn @"xvssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13268 return encodeXdXjUk6(0x77610000, p0, p1, p2);
13269 }
13270
13271 /// Encodes a `xvssrani.wu.d` instruction (requires lasx).
13272 pub inline fn @"xvssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
13273 return encodeXdXjUk6(0x77650000, p0, p1, p2);
13274 }
13275
13276 /// Encodes a `xvssrarn.b.h` instruction (requires lasx).
13277 pub inline fn @"xvssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13278 return encodeXdXjXk(0x75028000, p0, p1, p2);
13279 }
13280
13281 /// Encodes a `xvssrarn.bu.h` instruction (requires lasx).
13282 pub inline fn @"xvssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
13283 return encodeXdXjXk(0x750a8000, p0, p1, p2);
13284 }
13285
13286 /// Encodes a `xvssrarn.h.w` instruction (requires lasx).
13287 pub inline fn @"xvssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13288 return encodeXdXjXk(0x75030000, p0, p1, p2);
13289 }
13290
13291 /// Encodes a `xvssrarn.hu.w` instruction (requires lasx).
13292 pub inline fn @"xvssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
13293 return encodeXdXjXk(0x750b0000, p0, p1, p2);
13294 }
13295
13296 /// Encodes a `xvssrarn.w.d` instruction (requires lasx).
13297 pub inline fn @"xvssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13298 return encodeXdXjXk(0x75038000, p0, p1, p2);
13299 }
13300
13301 /// Encodes a `xvssrarn.wu.d` instruction (requires lasx).
13302 pub inline fn @"xvssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
13303 return encodeXdXjXk(0x750b8000, p0, p1, p2);
13304 }
13305
13306 /// Encodes a `xvssrarni.b.h` instruction (requires lasx).
13307 pub inline fn @"xvssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13308 return encodeXdXjUk4(0x77684000, p0, p1, p2);
13309 }
13310
13311 /// Encodes a `xvssrarni.bu.h` instruction (requires lasx).
13312 pub inline fn @"xvssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
13313 return encodeXdXjUk4(0x776c4000, p0, p1, p2);
13314 }
13315
13316 /// Encodes a `xvssrarni.d.q` instruction (requires lasx).
13317 pub inline fn @"xvssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13318 return encodeXdXjUk7(0x776a0000, p0, p1, p2);
13319 }
13320
13321 /// Encodes a `xvssrarni.du.q` instruction (requires lasx).
13322 pub inline fn @"xvssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
13323 return encodeXdXjUk7(0x776e0000, p0, p1, p2);
13324 }
13325
13326 /// Encodes a `xvssrarni.h.w` instruction (requires lasx).
13327 pub inline fn @"xvssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13328 return encodeXdXjUk5(0x77688000, p0, p1, p2);
13329 }
13330
13331 /// Encodes a `xvssrarni.hu.w` instruction (requires lasx).
13332 pub inline fn @"xvssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
13333 return encodeXdXjUk5(0x776c8000, p0, p1, p2);
13334 }
13335
13336 /// Encodes a `xvssrarni.w.d` instruction (requires lasx).
13337 pub inline fn @"xvssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13338 return encodeXdXjUk6(0x77690000, p0, p1, p2);
13339 }
13340
13341 /// Encodes a `xvssrarni.wu.d` instruction (requires lasx).
13342 pub inline fn @"xvssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
13343 return encodeXdXjUk6(0x776d0000, p0, p1, p2);
13344 }
13345
13346 /// Encodes a `xvssrln.b.h` instruction (requires lasx).
13347 pub inline fn @"xvssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13348 return encodeXdXjXk(0x74fc8000, p0, p1, p2);
13349 }
13350
13351 /// Encodes a `xvssrln.bu.h` instruction (requires lasx).
13352 pub inline fn @"xvssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
13353 return encodeXdXjXk(0x75048000, p0, p1, p2);
13354 }
13355
13356 /// Encodes a `xvssrln.h.w` instruction (requires lasx).
13357 pub inline fn @"xvssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13358 return encodeXdXjXk(0x74fd0000, p0, p1, p2);
13359 }
13360
13361 /// Encodes a `xvssrln.hu.w` instruction (requires lasx).
13362 pub inline fn @"xvssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
13363 return encodeXdXjXk(0x75050000, p0, p1, p2);
13364 }
13365
13366 /// Encodes a `xvssrln.w.d` instruction (requires lasx).
13367 pub inline fn @"xvssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13368 return encodeXdXjXk(0x74fd8000, p0, p1, p2);
13369 }
13370
13371 /// Encodes a `xvssrln.wu.d` instruction (requires lasx).
13372 pub inline fn @"xvssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
13373 return encodeXdXjXk(0x75058000, p0, p1, p2);
13374 }
13375
13376 /// Encodes a `xvssrlni.b.h` instruction (requires lasx).
13377 pub inline fn @"xvssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13378 return encodeXdXjUk4(0x77484000, p0, p1, p2);
13379 }
13380
13381 /// Encodes a `xvssrlni.bu.h` instruction (requires lasx).
13382 pub inline fn @"xvssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
13383 return encodeXdXjUk4(0x774c4000, p0, p1, p2);
13384 }
13385
13386 /// Encodes a `xvssrlni.d.q` instruction (requires lasx).
13387 pub inline fn @"xvssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13388 return encodeXdXjUk7(0x774a0000, p0, p1, p2);
13389 }
13390
13391 /// Encodes a `xvssrlni.du.q` instruction (requires lasx).
13392 pub inline fn @"xvssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
13393 return encodeXdXjUk7(0x774e0000, p0, p1, p2);
13394 }
13395
13396 /// Encodes a `xvssrlni.h.w` instruction (requires lasx).
13397 pub inline fn @"xvssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13398 return encodeXdXjUk5(0x77488000, p0, p1, p2);
13399 }
13400
13401 /// Encodes a `xvssrlni.hu.w` instruction (requires lasx).
13402 pub inline fn @"xvssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
13403 return encodeXdXjUk5(0x774c8000, p0, p1, p2);
13404 }
13405
13406 /// Encodes a `xvssrlni.w.d` instruction (requires lasx).
13407 pub inline fn @"xvssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13408 return encodeXdXjUk6(0x77490000, p0, p1, p2);
13409 }
13410
13411 /// Encodes a `xvssrlni.wu.d` instruction (requires lasx).
13412 pub inline fn @"xvssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
13413 return encodeXdXjUk6(0x774d0000, p0, p1, p2);
13414 }
13415
13416 /// Encodes a `xvssrlrn.b.h` instruction (requires lasx).
13417 pub inline fn @"xvssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction {
13418 return encodeXdXjXk(0x75008000, p0, p1, p2);
13419 }
13420
13421 /// Encodes a `xvssrlrn.bu.h` instruction (requires lasx).
13422 pub inline fn @"xvssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction {
13423 return encodeXdXjXk(0x75088000, p0, p1, p2);
13424 }
13425
13426 /// Encodes a `xvssrlrn.h.w` instruction (requires lasx).
13427 pub inline fn @"xvssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction {
13428 return encodeXdXjXk(0x75010000, p0, p1, p2);
13429 }
13430
13431 /// Encodes a `xvssrlrn.hu.w` instruction (requires lasx).
13432 pub inline fn @"xvssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction {
13433 return encodeXdXjXk(0x75090000, p0, p1, p2);
13434 }
13435
13436 /// Encodes a `xvssrlrn.w.d` instruction (requires lasx).
13437 pub inline fn @"xvssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction {
13438 return encodeXdXjXk(0x75018000, p0, p1, p2);
13439 }
13440
13441 /// Encodes a `xvssrlrn.wu.d` instruction (requires lasx).
13442 pub inline fn @"xvssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction {
13443 return encodeXdXjXk(0x75098000, p0, p1, p2);
13444 }
13445
13446 /// Encodes a `xvssrlrni.b.h` instruction (requires lasx).
13447 pub inline fn @"xvssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction {
13448 return encodeXdXjUk4(0x77504000, p0, p1, p2);
13449 }
13450
13451 /// Encodes a `xvssrlrni.bu.h` instruction (requires lasx).
13452 pub inline fn @"xvssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction {
13453 return encodeXdXjUk4(0x77544000, p0, p1, p2);
13454 }
13455
13456 /// Encodes a `xvssrlrni.d.q` instruction (requires lasx).
13457 pub inline fn @"xvssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction {
13458 return encodeXdXjUk7(0x77520000, p0, p1, p2);
13459 }
13460
13461 /// Encodes a `xvssrlrni.du.q` instruction (requires lasx).
13462 pub inline fn @"xvssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction {
13463 return encodeXdXjUk7(0x77560000, p0, p1, p2);
13464 }
13465
13466 /// Encodes a `xvssrlrni.h.w` instruction (requires lasx).
13467 pub inline fn @"xvssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction {
13468 return encodeXdXjUk5(0x77508000, p0, p1, p2);
13469 }
13470
13471 /// Encodes a `xvssrlrni.hu.w` instruction (requires lasx).
13472 pub inline fn @"xvssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction {
13473 return encodeXdXjUk5(0x77548000, p0, p1, p2);
13474 }
13475
13476 /// Encodes a `xvssrlrni.w.d` instruction (requires lasx).
13477 pub inline fn @"xvssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction {
13478 return encodeXdXjUk6(0x77510000, p0, p1, p2);
13479 }
13480
13481 /// Encodes a `xvssrlrni.wu.d` instruction (requires lasx).
13482 pub inline fn @"xvssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction {
13483 return encodeXdXjUk6(0x77550000, p0, p1, p2);
13484 }
13485
13486 /// Encodes a `xvssub.b` instruction (requires lasx).
13487 pub inline fn @"xvssub.b"(p0: Register, p1: Register, p2: Register) Instruction {
13488 return encodeXdXjXk(0x74480000, p0, p1, p2);
13489 }
13490
13491 /// Encodes a `xvssub.bu` instruction (requires lasx).
13492 pub inline fn @"xvssub.bu"(p0: Register, p1: Register, p2: Register) Instruction {
13493 return encodeXdXjXk(0x744c0000, p0, p1, p2);
13494 }
13495
13496 /// Encodes a `xvssub.d` instruction (requires lasx).
13497 pub inline fn @"xvssub.d"(p0: Register, p1: Register, p2: Register) Instruction {
13498 return encodeXdXjXk(0x74498000, p0, p1, p2);
13499 }
13500
13501 /// Encodes a `xvssub.du` instruction (requires lasx).
13502 pub inline fn @"xvssub.du"(p0: Register, p1: Register, p2: Register) Instruction {
13503 return encodeXdXjXk(0x744d8000, p0, p1, p2);
13504 }
13505
13506 /// Encodes a `xvssub.h` instruction (requires lasx).
13507 pub inline fn @"xvssub.h"(p0: Register, p1: Register, p2: Register) Instruction {
13508 return encodeXdXjXk(0x74488000, p0, p1, p2);
13509 }
13510
13511 /// Encodes a `xvssub.hu` instruction (requires lasx).
13512 pub inline fn @"xvssub.hu"(p0: Register, p1: Register, p2: Register) Instruction {
13513 return encodeXdXjXk(0x744c8000, p0, p1, p2);
13514 }
13515
13516 /// Encodes a `xvssub.w` instruction (requires lasx).
13517 pub inline fn @"xvssub.w"(p0: Register, p1: Register, p2: Register) Instruction {
13518 return encodeXdXjXk(0x74490000, p0, p1, p2);
13519 }
13520
13521 /// Encodes a `xvssub.wu` instruction (requires lasx).
13522 pub inline fn @"xvssub.wu"(p0: Register, p1: Register, p2: Register) Instruction {
13523 return encodeXdXjXk(0x744d0000, p0, p1, p2);
13524 }
13525
13526 /// Encodes a `xvst` instruction (requires lasx).
13527 pub inline fn xvst(p0: Register, p1: Register, p2: i12) Instruction {
13528 return encodeXdJSk12(0x2cc00000, p0, p1, p2);
13529 }
13530
13531 /// Encodes a `xvstelm.b` instruction (requires lasx).
13532 pub inline fn @"xvstelm.b"(p0: Register, p1: Register, p2: i8, p3: u5) Instruction {
13533 return encodeXdJSk8Un5(0x33800000, p0, p1, p2, p3);
13534 }
13535
13536 /// Encodes a `xvstelm.d` instruction (requires lasx).
13537 pub inline fn @"xvstelm.d"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction {
13538 return encodeXdJSk8ps3Un2(0x33100000, p0, p1, p2, p3);
13539 }
13540
13541 /// Encodes a `xvstelm.h` instruction (requires lasx).
13542 pub inline fn @"xvstelm.h"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction {
13543 return encodeXdJSk8ps1Un4(0x33400000, p0, p1, p2, p3);
13544 }
13545
13546 /// Encodes a `xvstelm.w` instruction (requires lasx).
13547 pub inline fn @"xvstelm.w"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction {
13548 return encodeXdJSk8ps2Un3(0x33200000, p0, p1, p2, p3);
13549 }
13550
13551 /// Encodes a `xvstx` instruction (requires lasx).
13552 pub inline fn xvstx(p0: Register, p1: Register, p2: Register) Instruction {
13553 return encodeXdJK(0x384c0000, p0, p1, p2);
13554 }
13555
13556 /// Encodes a `xvsub.b` instruction (requires lasx).
13557 pub inline fn @"xvsub.b"(p0: Register, p1: Register, p2: Register) Instruction {
13558 return encodeXdXjXk(0x740c0000, p0, p1, p2);
13559 }
13560
13561 /// Encodes a `xvsub.d` instruction (requires lasx).
13562 pub inline fn @"xvsub.d"(p0: Register, p1: Register, p2: Register) Instruction {
13563 return encodeXdXjXk(0x740d8000, p0, p1, p2);
13564 }
13565
13566 /// Encodes a `xvsub.h` instruction (requires lasx).
13567 pub inline fn @"xvsub.h"(p0: Register, p1: Register, p2: Register) Instruction {
13568 return encodeXdXjXk(0x740c8000, p0, p1, p2);
13569 }
13570
13571 /// Encodes a `xvsub.q` instruction (requires lasx).
13572 pub inline fn @"xvsub.q"(p0: Register, p1: Register, p2: Register) Instruction {
13573 return encodeXdXjXk(0x752d8000, p0, p1, p2);
13574 }
13575
13576 /// Encodes a `xvsub.w` instruction (requires lasx).
13577 pub inline fn @"xvsub.w"(p0: Register, p1: Register, p2: Register) Instruction {
13578 return encodeXdXjXk(0x740d0000, p0, p1, p2);
13579 }
13580
13581 /// Encodes a `xvsubi.bu` instruction (requires lasx).
13582 pub inline fn @"xvsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction {
13583 return encodeXdXjUk5(0x768c0000, p0, p1, p2);
13584 }
13585
13586 /// Encodes a `xvsubi.du` instruction (requires lasx).
13587 pub inline fn @"xvsubi.du"(p0: Register, p1: Register, p2: u5) Instruction {
13588 return encodeXdXjUk5(0x768d8000, p0, p1, p2);
13589 }
13590
13591 /// Encodes a `xvsubi.hu` instruction (requires lasx).
13592 pub inline fn @"xvsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction {
13593 return encodeXdXjUk5(0x768c8000, p0, p1, p2);
13594 }
13595
13596 /// Encodes a `xvsubi.wu` instruction (requires lasx).
13597 pub inline fn @"xvsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction {
13598 return encodeXdXjUk5(0x768d0000, p0, p1, p2);
13599 }
13600
13601 /// Encodes a `xvsubwev.d.w` instruction (requires lasx).
13602 pub inline fn @"xvsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
13603 return encodeXdXjXk(0x74210000, p0, p1, p2);
13604 }
13605
13606 /// Encodes a `xvsubwev.d.wu` instruction (requires lasx).
13607 pub inline fn @"xvsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
13608 return encodeXdXjXk(0x74310000, p0, p1, p2);
13609 }
13610
13611 /// Encodes a `xvsubwev.h.b` instruction (requires lasx).
13612 pub inline fn @"xvsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
13613 return encodeXdXjXk(0x74200000, p0, p1, p2);
13614 }
13615
13616 /// Encodes a `xvsubwev.h.bu` instruction (requires lasx).
13617 pub inline fn @"xvsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
13618 return encodeXdXjXk(0x74300000, p0, p1, p2);
13619 }
13620
13621 /// Encodes a `xvsubwev.q.d` instruction (requires lasx).
13622 pub inline fn @"xvsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
13623 return encodeXdXjXk(0x74218000, p0, p1, p2);
13624 }
13625
13626 /// Encodes a `xvsubwev.q.du` instruction (requires lasx).
13627 pub inline fn @"xvsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
13628 return encodeXdXjXk(0x74318000, p0, p1, p2);
13629 }
13630
13631 /// Encodes a `xvsubwev.w.h` instruction (requires lasx).
13632 pub inline fn @"xvsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
13633 return encodeXdXjXk(0x74208000, p0, p1, p2);
13634 }
13635
13636 /// Encodes a `xvsubwev.w.hu` instruction (requires lasx).
13637 pub inline fn @"xvsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
13638 return encodeXdXjXk(0x74308000, p0, p1, p2);
13639 }
13640
13641 /// Encodes a `xvsubwod.d.w` instruction (requires lasx).
13642 pub inline fn @"xvsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction {
13643 return encodeXdXjXk(0x74250000, p0, p1, p2);
13644 }
13645
13646 /// Encodes a `xvsubwod.d.wu` instruction (requires lasx).
13647 pub inline fn @"xvsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction {
13648 return encodeXdXjXk(0x74350000, p0, p1, p2);
13649 }
13650
13651 /// Encodes a `xvsubwod.h.b` instruction (requires lasx).
13652 pub inline fn @"xvsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction {
13653 return encodeXdXjXk(0x74240000, p0, p1, p2);
13654 }
13655
13656 /// Encodes a `xvsubwod.h.bu` instruction (requires lasx).
13657 pub inline fn @"xvsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction {
13658 return encodeXdXjXk(0x74340000, p0, p1, p2);
13659 }
13660
13661 /// Encodes a `xvsubwod.q.d` instruction (requires lasx).
13662 pub inline fn @"xvsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction {
13663 return encodeXdXjXk(0x74258000, p0, p1, p2);
13664 }
13665
13666 /// Encodes a `xvsubwod.q.du` instruction (requires lasx).
13667 pub inline fn @"xvsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction {
13668 return encodeXdXjXk(0x74358000, p0, p1, p2);
13669 }
13670
13671 /// Encodes a `xvsubwod.w.h` instruction (requires lasx).
13672 pub inline fn @"xvsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction {
13673 return encodeXdXjXk(0x74248000, p0, p1, p2);
13674 }
13675
13676 /// Encodes a `xvsubwod.w.hu` instruction (requires lasx).
13677 pub inline fn @"xvsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction {
13678 return encodeXdXjXk(0x74348000, p0, p1, p2);
13679 }
13680
13681 /// Encodes a `xvxor.v` instruction (requires lasx).
13682 pub inline fn @"xvxor.v"(p0: Register, p1: Register, p2: Register) Instruction {
13683 return encodeXdXjXk(0x75270000, p0, p1, p2);
13684 }
13685
13686 /// Encodes a `xvxori.b` instruction (requires lasx).
13687 pub inline fn @"xvxori.b"(p0: Register, p1: Register, p2: u8) Instruction {
13688 return encodeXdXjUk8(0x77d80000, p0, p1, p2);
13689 }
13690
13691 /// Encodes a `xxx.unknown.1` instruction (requires 64bit).
13692 pub inline fn @"xxx.unknown.1"() Instruction {
13693 return encodeEMPTY(0x06493000);
13694 }
13695};
src/codegen/loongarch/inst_formats.zon created+11059
...@@ -0,0 +1,11059 @@
1// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig.
2.{
3 .instructions = .{
4 .@"adc.b" = .{
5 .word = 0x00300000,
6 .format = .DJK,
7 .features = .{.@"64bit"},
8 },
9 .@"adc.d" = .{
10 .word = 0x00318000,
11 .format = .DJK,
12 .features = .{.@"64bit"},
13 },
14 .@"adc.h" = .{
15 .word = 0x00308000,
16 .format = .DJK,
17 .features = .{.@"64bit"},
18 },
19 .@"adc.w" = .{
20 .word = 0x00310000,
21 .format = .DJK,
22 .features = .{.@"64bit"},
23 },
24 .@"add.d" = .{
25 .word = 0x00108000,
26 .format = .DJK,
27 .features = .{.@"64bit"},
28 },
29 .@"add.w" = .{
30 .word = 0x00100000,
31 .format = .DJK,
32 .features = .{.@"32bit"},
33 },
34 .@"addi.d" = .{
35 .word = 0x02c00000,
36 .format = .DJSk12,
37 .features = .{.@"64bit"},
38 },
39 .@"addi.w" = .{
40 .word = 0x02800000,
41 .format = .DJSk12,
42 .features = .{.@"32bit"},
43 },
44 .@"addu12i.d" = .{
45 .word = 0x00298000,
46 .format = .DJSk5,
47 .features = .{.@"64bit"},
48 },
49 .@"addu12i.w" = .{
50 .word = 0x00290000,
51 .format = .DJSk5,
52 .features = .{.@"64bit"},
53 },
54 .@"addu16i.d" = .{
55 .word = 0x10000000,
56 .format = .DJSk16,
57 .features = .{.@"64bit"},
58 },
59 .@"amadd.b" = .{
60 .word = 0x385d0000,
61 .format = .DJK,
62 .orig_format = .DKJ,
63 .features = .{.@"64bit"},
64 },
65 .@"amadd.d" = .{
66 .word = 0x38618000,
67 .format = .DJK,
68 .orig_format = .DKJ,
69 .features = .{.@"64bit"},
70 },
71 .@"amadd.h" = .{
72 .word = 0x385d8000,
73 .format = .DJK,
74 .orig_format = .DKJ,
75 .features = .{.@"64bit"},
76 },
77 .@"amadd.w" = .{
78 .word = 0x38610000,
79 .format = .DJK,
80 .orig_format = .DKJ,
81 .features = .{.@"64bit"},
82 },
83 .@"amadd_db.b" = .{
84 .word = 0x385f0000,
85 .format = .DJK,
86 .orig_format = .DKJ,
87 .features = .{.@"64bit"},
88 },
89 .@"amadd_db.d" = .{
90 .word = 0x386a8000,
91 .format = .DJK,
92 .orig_format = .DKJ,
93 .features = .{.@"64bit"},
94 },
95 .@"amadd_db.h" = .{
96 .word = 0x385f8000,
97 .format = .DJK,
98 .orig_format = .DKJ,
99 .features = .{.@"64bit"},
100 },
101 .@"amadd_db.w" = .{
102 .word = 0x386a0000,
103 .format = .DJK,
104 .orig_format = .DKJ,
105 .features = .{.@"64bit"},
106 },
107 .@"amand.d" = .{
108 .word = 0x38628000,
109 .format = .DJK,
110 .orig_format = .DKJ,
111 .features = .{.@"64bit"},
112 },
113 .@"amand.w" = .{
114 .word = 0x38620000,
115 .format = .DJK,
116 .orig_format = .DKJ,
117 .features = .{.@"64bit"},
118 },
119 .@"amand_db.d" = .{
120 .word = 0x386b8000,
121 .format = .DJK,
122 .orig_format = .DKJ,
123 .features = .{.@"64bit"},
124 },
125 .@"amand_db.w" = .{
126 .word = 0x386b0000,
127 .format = .DJK,
128 .orig_format = .DKJ,
129 .features = .{.@"64bit"},
130 },
131 .@"amcas.b" = .{
132 .word = 0x38580000,
133 .format = .DJK,
134 .orig_format = .DKJ,
135 .features = .{.@"64bit"},
136 },
137 .@"amcas.d" = .{
138 .word = 0x38598000,
139 .format = .DJK,
140 .orig_format = .DKJ,
141 .features = .{.@"64bit"},
142 },
143 .@"amcas.h" = .{
144 .word = 0x38588000,
145 .format = .DJK,
146 .orig_format = .DKJ,
147 .features = .{.@"64bit"},
148 },
149 .@"amcas.w" = .{
150 .word = 0x38590000,
151 .format = .DJK,
152 .orig_format = .DKJ,
153 .features = .{.@"64bit"},
154 },
155 .@"amcas_db.b" = .{
156 .word = 0x385a0000,
157 .format = .DJK,
158 .orig_format = .DKJ,
159 .features = .{.@"64bit"},
160 },
161 .@"amcas_db.d" = .{
162 .word = 0x385b8000,
163 .format = .DJK,
164 .orig_format = .DKJ,
165 .features = .{.@"64bit"},
166 },
167 .@"amcas_db.h" = .{
168 .word = 0x385a8000,
169 .format = .DJK,
170 .orig_format = .DKJ,
171 .features = .{.@"64bit"},
172 },
173 .@"amcas_db.w" = .{
174 .word = 0x385b0000,
175 .format = .DJK,
176 .orig_format = .DKJ,
177 .features = .{.@"64bit"},
178 },
179 .@"ammax.d" = .{
180 .word = 0x38658000,
181 .format = .DJK,
182 .orig_format = .DKJ,
183 .features = .{.@"64bit"},
184 },
185 .@"ammax.du" = .{
186 .word = 0x38678000,
187 .format = .DJK,
188 .orig_format = .DKJ,
189 .features = .{.@"64bit"},
190 },
191 .@"ammax.w" = .{
192 .word = 0x38650000,
193 .format = .DJK,
194 .orig_format = .DKJ,
195 .features = .{.@"64bit"},
196 },
197 .@"ammax.wu" = .{
198 .word = 0x38670000,
199 .format = .DJK,
200 .orig_format = .DKJ,
201 .features = .{.@"64bit"},
202 },
203 .@"ammax_db.d" = .{
204 .word = 0x386e8000,
205 .format = .DJK,
206 .orig_format = .DKJ,
207 .features = .{.@"64bit"},
208 },
209 .@"ammax_db.du" = .{
210 .word = 0x38708000,
211 .format = .DJK,
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1669 .word = 0x38798000,
1670 .format = .DJK,
1671 .features = .{.@"64bit"},
1672 },
1673 .@"ldgt.h" = .{
1674 .word = 0x38788000,
1675 .format = .DJK,
1676 .features = .{.@"64bit"},
1677 },
1678 .@"ldgt.w" = .{
1679 .word = 0x38790000,
1680 .format = .DJK,
1681 .features = .{.@"64bit"},
1682 },
1683 .@"ldl.d" = .{
1684 .word = 0x2e800000,
1685 .format = .DJSk12,
1686 .features = .{.@"64bit"},
1687 },
1688 .@"ldl.w" = .{
1689 .word = 0x2e000000,
1690 .format = .DJSk12,
1691 .features = .{.@"64bit"},
1692 },
1693 .@"ldle.b" = .{
1694 .word = 0x387a0000,
1695 .format = .DJK,
1696 .features = .{.@"64bit"},
1697 },
1698 .@"ldle.d" = .{
1699 .word = 0x387b8000,
1700 .format = .DJK,
1701 .features = .{.@"64bit"},
1702 },
1703 .@"ldle.h" = .{
1704 .word = 0x387a8000,
1705 .format = .DJK,
1706 .features = .{.@"64bit"},
1707 },
1708 .@"ldle.w" = .{
1709 .word = 0x387b0000,
1710 .format = .DJK,
1711 .features = .{.@"64bit"},
1712 },
1713 .@"ldox4.d" = .{
1714 .word = 0x26000000,
1715 .format = .DJSk14,
1716 .orig_format = .DJSk14ps2,
1717 .orig_name = "ldptr.d",
1718 .features = .{.@"64bit"},
1719 },
1720 .@"ldox4.w" = .{
1721 .word = 0x24000000,
1722 .format = .DJSk14,
1723 .orig_format = .DJSk14ps2,
1724 .orig_name = "ldptr.w",
1725 .features = .{.@"64bit"},
1726 },
1727 .ldpte = .{
1728 .word = 0x06440000,
1729 .format = .JUk8,
1730 .features = .{.@"64bit"},
1731 },
1732 .@"ldr.d" = .{
1733 .word = 0x2ec00000,
1734 .format = .DJSk12,
1735 .features = .{.@"64bit"},
1736 },
1737 .@"ldr.w" = .{
1738 .word = 0x2e400000,
1739 .format = .DJSk12,
1740 .features = .{.@"64bit"},
1741 },
1742 .@"ldx.b" = .{
1743 .word = 0x38000000,
1744 .format = .DJK,
1745 .features = .{.@"64bit"},
1746 },
1747 .@"ldx.bu" = .{
1748 .word = 0x38200000,
1749 .format = .DJK,
1750 .features = .{.@"64bit"},
1751 },
1752 .@"ldx.d" = .{
1753 .word = 0x380c0000,
1754 .format = .DJK,
1755 .features = .{.@"64bit"},
1756 },
1757 .@"ldx.h" = .{
1758 .word = 0x38040000,
1759 .format = .DJK,
1760 .features = .{.@"64bit"},
1761 },
1762 .@"ldx.hu" = .{
1763 .word = 0x38240000,
1764 .format = .DJK,
1765 .features = .{.@"64bit"},
1766 },
1767 .@"ldx.w" = .{
1768 .word = 0x38080000,
1769 .format = .DJK,
1770 .features = .{.@"64bit"},
1771 },
1772 .@"ldx.wu" = .{
1773 .word = 0x38280000,
1774 .format = .DJK,
1775 .features = .{.@"64bit"},
1776 },
1777 .@"ll.d" = .{
1778 .word = 0x22000000,
1779 .format = .DJSk14,
1780 .orig_format = .DJSk14ps2,
1781 .features = .{.@"64bit"},
1782 },
1783 .@"ll.w" = .{
1784 .word = 0x20000000,
1785 .format = .DJSk14,
1786 .orig_format = .DJSk14ps2,
1787 .features = .{.@"32bit"},
1788 },
1789 .@"llacq.d" = .{
1790 .word = 0x38578800,
1791 .format = .DJ,
1792 .features = .{.@"64bit"},
1793 },
1794 .@"llacq.w" = .{
1795 .word = 0x38578000,
1796 .format = .DJ,
1797 .features = .{.@"64bit"},
1798 },
1799 .@"lu12i.w" = .{
1800 .word = 0x14000000,
1801 .format = .DSj20,
1802 .features = .{.@"32bit"},
1803 },
1804 .maskeqz = .{
1805 .word = 0x00130000,
1806 .format = .DJK,
1807 .features = .{.@"32s"},
1808 },
1809 .masknez = .{
1810 .word = 0x00138000,
1811 .format = .DJK,
1812 .features = .{.@"32s"},
1813 },
1814 .@"mod.d" = .{
1815 .word = 0x00228000,
1816 .format = .DJK,
1817 .features = .{.@"64bit"},
1818 },
1819 .@"mod.du" = .{
1820 .word = 0x00238000,
1821 .format = .DJK,
1822 .features = .{.@"64bit"},
1823 },
1824 .@"mod.w" = .{
1825 .word = 0x00208000,
1826 .format = .DJK,
1827 .features = .{.@"32bit"},
1828 },
1829 .@"mod.wu" = .{
1830 .word = 0x00218000,
1831 .format = .DJK,
1832 .features = .{.@"32bit"},
1833 },
1834 .movfcc2fr = .{
1835 .word = 0x0114d400,
1836 .format = .FdCj,
1837 .orig_name = "movcf2fr",
1838 .features = .{.f},
1839 },
1840 .movfcc2gr = .{
1841 .word = 0x0114dc00,
1842 .format = .DCj,
1843 .orig_name = "movcf2gr",
1844 .features = .{.f},
1845 },
1846 .movfr2fcc = .{
1847 .word = 0x0114d000,
1848 .format = .CdFj,
1849 .orig_name = "movfr2cf",
1850 .features = .{.f},
1851 },
1852 .@"movfr2gr.d" = .{
1853 .word = 0x0114b800,
1854 .format = .DFj,
1855 .features = .{.f},
1856 },
1857 .@"movfr2gr.s" = .{
1858 .word = 0x0114b400,
1859 .format = .DFj,
1860 .features = .{.f},
1861 },
1862 .@"movfrh2gr.s" = .{
1863 .word = 0x0114bc00,
1864 .format = .DFj,
1865 .features = .{.f},
1866 },
1867 .movgr2fcc = .{
1868 .word = 0x0114d800,
1869 .format = .CdJ,
1870 .orig_name = "movgr2cf",
1871 .features = .{.f},
1872 },
1873 .@"movgr2fr.d" = .{
1874 .word = 0x0114a800,
1875 .format = .FdJ,
1876 .features = .{.f},
1877 },
1878 .@"movgr2fr.w" = .{
1879 .word = 0x0114a400,
1880 .format = .FdJ,
1881 .features = .{.f},
1882 },
1883 .@"movgr2frh.w" = .{
1884 .word = 0x0114ac00,
1885 .format = .FdJ,
1886 .features = .{.f},
1887 },
1888 .movgr2scr = .{
1889 .word = 0x00000800,
1890 .format = .TdJ,
1891 .features = .{.lbt},
1892 },
1893 .movscr2gr = .{
1894 .word = 0x00000c00,
1895 .format = .DTj,
1896 .features = .{.lbt},
1897 },
1898 .@"mul.d" = .{
1899 .word = 0x001d8000,
1900 .format = .DJK,
1901 .features = .{.@"64bit"},
1902 },
1903 .@"mul.w" = .{
1904 .word = 0x001c0000,
1905 .format = .DJK,
1906 .features = .{.@"32bit"},
1907 },
1908 .@"mulh.d" = .{
1909 .word = 0x001e0000,
1910 .format = .DJK,
1911 .features = .{.@"64bit"},
1912 },
1913 .@"mulh.du" = .{
1914 .word = 0x001e8000,
1915 .format = .DJK,
1916 .features = .{.@"64bit"},
1917 },
1918 .@"mulh.w" = .{
1919 .word = 0x001c8000,
1920 .format = .DJK,
1921 .features = .{.@"32bit"},
1922 },
1923 .@"mulh.wu" = .{
1924 .word = 0x001d0000,
1925 .format = .DJK,
1926 .features = .{.@"32bit"},
1927 },
1928 .@"mulw.d.w" = .{
1929 .word = 0x001f0000,
1930 .format = .DJK,
1931 .features = .{.@"64bit"},
1932 },
1933 .@"mulw.d.wu" = .{
1934 .word = 0x001f8000,
1935 .format = .DJK,
1936 .features = .{.@"64bit"},
1937 },
1938 .nor = .{
1939 .word = 0x00140000,
1940 .format = .DJK,
1941 .features = .{.@"32bit"},
1942 },
1943 .@"or" = .{
1944 .word = 0x00150000,
1945 .format = .DJK,
1946 .features = .{.@"32bit"},
1947 },
1948 .ori = .{
1949 .word = 0x03800000,
1950 .format = .DJUk12,
1951 .features = .{.@"32bit"},
1952 },
1953 .orn = .{
1954 .word = 0x00160000,
1955 .format = .DJK,
1956 .features = .{.@"32bit"},
1957 },
1958 .pcaddu12i = .{
1959 .word = 0x1c000000,
1960 .format = .DSj20,
1961 .features = .{.@"32bit"},
1962 },
1963 .pcaddu18i = .{
1964 .word = 0x1e000000,
1965 .format = .DSj20,
1966 .features = .{.@"64bit"},
1967 },
1968 .pcaddu2i = .{
1969 .word = 0x18000000,
1970 .format = .DSj20,
1971 .orig_name = "pcaddi",
1972 .features = .{.@"32bit"},
1973 },
1974 .pcalau12i = .{
1975 .word = 0x1a000000,
1976 .format = .DSj20,
1977 .features = .{.@"32s"},
1978 },
1979 .preld = .{
1980 .word = 0x2ac00000,
1981 .format = .JUd5Sk12,
1982 .orig_format = .Ud5JSk12,
1983 .features = .{.@"32bit"},
1984 },
1985 .preldx = .{
1986 .word = 0x382c0000,
1987 .format = .JKUd5,
1988 .orig_format = .Ud5JK,
1989 .features = .{.@"64bit"},
1990 },
1991 .@"rcr.b" = .{
1992 .word = 0x00340000,
1993 .format = .DJK,
1994 .features = .{.@"64bit"},
1995 },
1996 .@"rcr.d" = .{
1997 .word = 0x00358000,
1998 .format = .DJK,
1999 .features = .{.@"64bit"},
2000 },
2001 .@"rcr.h" = .{
2002 .word = 0x00348000,
2003 .format = .DJK,
2004 .features = .{.@"64bit"},
2005 },
2006 .@"rcr.w" = .{
2007 .word = 0x00350000,
2008 .format = .DJK,
2009 .features = .{.@"64bit"},
2010 },
2011 .@"rcri.b" = .{
2012 .word = 0x00502000,
2013 .format = .DJUk3,
2014 .features = .{.@"64bit"},
2015 },
2016 .@"rcri.d" = .{
2017 .word = 0x00510000,
2018 .format = .DJUk6,
2019 .features = .{.@"64bit"},
2020 },
2021 .@"rcri.h" = .{
2022 .word = 0x00504000,
2023 .format = .DJUk4,
2024 .features = .{.@"64bit"},
2025 },
2026 .@"rcri.w" = .{
2027 .word = 0x00508000,
2028 .format = .DJUk5,
2029 .features = .{.@"64bit"},
2030 },
2031 .@"rdtime.d" = .{
2032 .word = 0x00006800,
2033 .format = .DJ,
2034 .features = .{.@"64bit"},
2035 },
2036 .@"rdtimeh.w" = .{
2037 .word = 0x00006400,
2038 .format = .DJ,
2039 .features = .{.@"32bit"},
2040 },
2041 .@"rdtimel.w" = .{
2042 .word = 0x00006000,
2043 .format = .DJ,
2044 .features = .{.@"32bit"},
2045 },
2046 .@"revb.2h" = .{
2047 .word = 0x00003000,
2048 .format = .DJ,
2049 .features = .{.@"32s"},
2050 },
2051 .@"revb.2w" = .{
2052 .word = 0x00003800,
2053 .format = .DJ,
2054 .features = .{.@"64bit"},
2055 },
2056 .@"revb.4h" = .{
2057 .word = 0x00003400,
2058 .format = .DJ,
2059 .features = .{.@"64bit"},
2060 },
2061 .@"revb.d" = .{
2062 .word = 0x00003c00,
2063 .format = .DJ,
2064 .features = .{.@"64bit"},
2065 },
2066 .@"revbit.4b" = .{
2067 .word = 0x00004800,
2068 .format = .DJ,
2069 .orig_name = "bitrev.4b",
2070 .features = .{.@"32s"},
2071 },
2072 .@"revbit.8b" = .{
2073 .word = 0x00004c00,
2074 .format = .DJ,
2075 .orig_name = "bitrev.8b",
2076 .features = .{.@"64bit"},
2077 },
2078 .@"revbit.d" = .{
2079 .word = 0x00005400,
2080 .format = .DJ,
2081 .orig_name = "bitrev.d",
2082 .features = .{.@"64bit"},
2083 },
2084 .@"revbit.w" = .{
2085 .word = 0x00005000,
2086 .format = .DJ,
2087 .orig_name = "bitrev.w",
2088 .features = .{.@"32s"},
2089 },
2090 .@"revh.2w" = .{
2091 .word = 0x00004000,
2092 .format = .DJ,
2093 .features = .{.@"64bit"},
2094 },
2095 .@"revh.d" = .{
2096 .word = 0x00004400,
2097 .format = .DJ,
2098 .features = .{.@"64bit"},
2099 },
2100 .@"rotr.b" = .{
2101 .word = 0x001a0000,
2102 .format = .DJK,
2103 .features = .{.@"64bit"},
2104 },
2105 .@"rotr.d" = .{
2106 .word = 0x001b8000,
2107 .format = .DJK,
2108 .features = .{.@"64bit"},
2109 },
2110 .@"rotr.h" = .{
2111 .word = 0x001a8000,
2112 .format = .DJK,
2113 .features = .{.@"64bit"},
2114 },
2115 .@"rotr.w" = .{
2116 .word = 0x001b0000,
2117 .format = .DJK,
2118 .features = .{.@"32s"},
2119 },
2120 .@"rotri.b" = .{
2121 .word = 0x004c2000,
2122 .format = .DJUk3,
2123 .features = .{.@"64bit"},
2124 },
2125 .@"rotri.d" = .{
2126 .word = 0x004d0000,
2127 .format = .DJUk6,
2128 .features = .{.@"64bit"},
2129 },
2130 .@"rotri.h" = .{
2131 .word = 0x004c4000,
2132 .format = .DJUk4,
2133 .features = .{.@"64bit"},
2134 },
2135 .@"rotri.w" = .{
2136 .word = 0x004c8000,
2137 .format = .DJUk5,
2138 .features = .{.@"32s"},
2139 },
2140 .@"sbc.b" = .{
2141 .word = 0x00320000,
2142 .format = .DJK,
2143 .features = .{.@"64bit"},
2144 },
2145 .@"sbc.d" = .{
2146 .word = 0x00338000,
2147 .format = .DJK,
2148 .features = .{.@"64bit"},
2149 },
2150 .@"sbc.h" = .{
2151 .word = 0x00328000,
2152 .format = .DJK,
2153 .features = .{.@"64bit"},
2154 },
2155 .@"sbc.w" = .{
2156 .word = 0x00330000,
2157 .format = .DJK,
2158 .features = .{.@"64bit"},
2159 },
2160 .@"sc.d" = .{
2161 .word = 0x23000000,
2162 .format = .DJSk14,
2163 .orig_format = .DJSk14ps2,
2164 .features = .{.@"64bit"},
2165 },
2166 .@"sc.q" = .{
2167 .word = 0x38570000,
2168 .format = .DJK,
2169 .orig_format = .DKJ,
2170 .features = .{.@"64bit"},
2171 },
2172 .@"sc.w" = .{
2173 .word = 0x21000000,
2174 .format = .DJSk14,
2175 .orig_format = .DJSk14ps2,
2176 .features = .{.@"32bit"},
2177 },
2178 .@"screl.d" = .{
2179 .word = 0x38578c00,
2180 .format = .DJ,
2181 .features = .{.@"64bit"},
2182 },
2183 .@"screl.w" = .{
2184 .word = 0x38578400,
2185 .format = .DJ,
2186 .features = .{.@"64bit"},
2187 },
2188 .@"sext.b" = .{
2189 .word = 0x00005c00,
2190 .format = .DJ,
2191 .orig_name = "ext.w.b",
2192 .features = .{.@"32s"},
2193 },
2194 .@"sext.h" = .{
2195 .word = 0x00005800,
2196 .format = .DJ,
2197 .orig_name = "ext.w.h",
2198 .features = .{.@"32s"},
2199 },
2200 .@"sladd.d" = .{
2201 .word = 0x002c0000,
2202 .format = .DJKUa2,
2203 .orig_format = .DJKUa2pp1,
2204 .orig_name = "alsl.d",
2205 .features = .{.@"64bit"},
2206 },
2207 .@"sladd.w" = .{
2208 .word = 0x00040000,
2209 .format = .DJKUa2,
2210 .orig_format = .DJKUa2pp1,
2211 .orig_name = "alsl.w",
2212 .features = .{.@"32s"},
2213 },
2214 .@"sladd.wu" = .{
2215 .word = 0x00060000,
2216 .format = .DJKUa2,
2217 .orig_format = .DJKUa2pp1,
2218 .orig_name = "alsl.wu",
2219 .features = .{.@"64bit"},
2220 },
2221 .@"sll.d" = .{
2222 .word = 0x00188000,
2223 .format = .DJK,
2224 .features = .{.@"64bit"},
2225 },
2226 .@"sll.w" = .{
2227 .word = 0x00170000,
2228 .format = .DJK,
2229 .features = .{.@"32bit"},
2230 },
2231 .@"slli.d" = .{
2232 .word = 0x00410000,
2233 .format = .DJUk6,
2234 .features = .{.@"64bit"},
2235 },
2236 .@"slli.w" = .{
2237 .word = 0x00408000,
2238 .format = .DJUk5,
2239 .features = .{.@"32bit"},
2240 },
2241 .slt = .{
2242 .word = 0x00120000,
2243 .format = .DJK,
2244 .features = .{.@"32bit"},
2245 },
2246 .slti = .{
2247 .word = 0x02000000,
2248 .format = .DJSk12,
2249 .features = .{.@"32bit"},
2250 },
2251 .sltu = .{
2252 .word = 0x00128000,
2253 .format = .DJK,
2254 .features = .{.@"32bit"},
2255 },
2256 .sltui = .{
2257 .word = 0x02400000,
2258 .format = .DJSk12,
2259 .features = .{.@"32bit"},
2260 },
2261 .@"sra.d" = .{
2262 .word = 0x00198000,
2263 .format = .DJK,
2264 .features = .{.@"64bit"},
2265 },
2266 .@"sra.w" = .{
2267 .word = 0x00180000,
2268 .format = .DJK,
2269 .features = .{.@"32bit"},
2270 },
2271 .@"srai.d" = .{
2272 .word = 0x00490000,
2273 .format = .DJUk6,
2274 .features = .{.@"64bit"},
2275 },
2276 .@"srai.w" = .{
2277 .word = 0x00488000,
2278 .format = .DJUk5,
2279 .features = .{.@"32bit"},
2280 },
2281 .@"srl.d" = .{
2282 .word = 0x00190000,
2283 .format = .DJK,
2284 .features = .{.@"64bit"},
2285 },
2286 .@"srl.w" = .{
2287 .word = 0x00178000,
2288 .format = .DJK,
2289 .features = .{.@"32bit"},
2290 },
2291 .@"srli.d" = .{
2292 .word = 0x00450000,
2293 .format = .DJUk6,
2294 .features = .{.@"64bit"},
2295 },
2296 .@"srli.w" = .{
2297 .word = 0x00448000,
2298 .format = .DJUk5,
2299 .features = .{.@"32bit"},
2300 },
2301 .@"st.b" = .{
2302 .word = 0x29000000,
2303 .format = .DJSk12,
2304 .features = .{.@"32bit"},
2305 },
2306 .@"st.d" = .{
2307 .word = 0x29c00000,
2308 .format = .DJSk12,
2309 .features = .{.@"64bit"},
2310 },
2311 .@"st.h" = .{
2312 .word = 0x29400000,
2313 .format = .DJSk12,
2314 .features = .{.@"32bit"},
2315 },
2316 .@"st.w" = .{
2317 .word = 0x29800000,
2318 .format = .DJSk12,
2319 .features = .{.@"32bit"},
2320 },
2321 .@"stgt.b" = .{
2322 .word = 0x387c0000,
2323 .format = .DJK,
2324 .features = .{.@"64bit"},
2325 },
2326 .@"stgt.d" = .{
2327 .word = 0x387d8000,
2328 .format = .DJK,
2329 .features = .{.@"64bit"},
2330 },
2331 .@"stgt.h" = .{
2332 .word = 0x387c8000,
2333 .format = .DJK,
2334 .features = .{.@"64bit"},
2335 },
2336 .@"stgt.w" = .{
2337 .word = 0x387d0000,
2338 .format = .DJK,
2339 .features = .{.@"64bit"},
2340 },
2341 .@"stl.d" = .{
2342 .word = 0x2f800000,
2343 .format = .DJSk12,
2344 .features = .{.@"64bit"},
2345 },
2346 .@"stl.w" = .{
2347 .word = 0x2f000000,
2348 .format = .DJSk12,
2349 .features = .{.@"64bit"},
2350 },
2351 .@"stle.b" = .{
2352 .word = 0x387e0000,
2353 .format = .DJK,
2354 .features = .{.@"64bit"},
2355 },
2356 .@"stle.d" = .{
2357 .word = 0x387f8000,
2358 .format = .DJK,
2359 .features = .{.@"64bit"},
2360 },
2361 .@"stle.h" = .{
2362 .word = 0x387e8000,
2363 .format = .DJK,
2364 .features = .{.@"64bit"},
2365 },
2366 .@"stle.w" = .{
2367 .word = 0x387f0000,
2368 .format = .DJK,
2369 .features = .{.@"64bit"},
2370 },
2371 .@"stox4.d" = .{
2372 .word = 0x27000000,
2373 .format = .DJSk14,
2374 .orig_format = .DJSk14ps2,
2375 .orig_name = "stptr.d",
2376 .features = .{.@"64bit"},
2377 },
2378 .@"stox4.w" = .{
2379 .word = 0x25000000,
2380 .format = .DJSk14,
2381 .orig_format = .DJSk14ps2,
2382 .orig_name = "stptr.w",
2383 .features = .{.@"64bit"},
2384 },
2385 .@"str.d" = .{
2386 .word = 0x2fc00000,
2387 .format = .DJSk12,
2388 .features = .{.@"64bit"},
2389 },
2390 .@"str.w" = .{
2391 .word = 0x2f400000,
2392 .format = .DJSk12,
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10362 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10363 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } },
10364 } },
10365 .CjSd5k16ps2 = .{ .slots = .{
10366 .{ .reg = .{ .location = 5, .class = .fcc } },
10367 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10368 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10369 } },
10370 .D = .{ .slots = .{
10371 .{ .reg = .{ .location = 0, .class = .int } },
10372 } },
10373 .DCj = .{ .slots = .{
10374 .{ .reg = .{ .location = 0, .class = .int } },
10375 .{ .reg = .{ .location = 5, .class = .fcc } },
10376 } },
10377 .DFj = .{ .slots = .{
10378 .{ .reg = .{ .location = 0, .class = .int } },
10379 .{ .reg = .{ .location = 5, .class = .fp } },
10380 } },
10381 .DJ = .{ .slots = .{
10382 .{ .reg = .{ .location = 0, .class = .int } },
10383 .{ .reg = .{ .location = 5, .class = .int } },
10384 } },
10385 .DJK = .{ .slots = .{
10386 .{ .reg = .{ .location = 0, .class = .int } },
10387 .{ .reg = .{ .location = 5, .class = .int } },
10388 .{ .reg = .{ .location = 10, .class = .int } },
10389 } },
10390 .DJKUa2 = .{ .slots = .{
10391 .{ .reg = .{ .location = 0, .class = .int } },
10392 .{ .reg = .{ .location = 5, .class = .int } },
10393 .{ .reg = .{ .location = 10, .class = .int } },
10394 .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned } },
10395 } },
10396 .DJKUa2pp1 = .{ .slots = .{
10397 .{ .reg = .{ .location = 0, .class = .int } },
10398 .{ .reg = .{ .location = 5, .class = .int } },
10399 .{ .reg = .{ .location = 10, .class = .int } },
10400 .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned, .post_proc = .{ .add = 1 } } },
10401 } },
10402 .DJKUa3 = .{ .slots = .{
10403 .{ .reg = .{ .location = 0, .class = .int } },
10404 .{ .reg = .{ .location = 5, .class = .int } },
10405 .{ .reg = .{ .location = 10, .class = .int } },
10406 .{ .imm = .{ .location = 15, .length = 3, .signedness = .unsigned } },
10407 } },
10408 .DJSk12 = .{ .slots = .{
10409 .{ .reg = .{ .location = 0, .class = .int } },
10410 .{ .reg = .{ .location = 5, .class = .int } },
10411 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10412 } },
10413 .DJSk14 = .{ .slots = .{
10414 .{ .reg = .{ .location = 0, .class = .int } },
10415 .{ .reg = .{ .location = 5, .class = .int } },
10416 .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed } },
10417 } },
10418 .DJSk14ps2 = .{ .slots = .{
10419 .{ .reg = .{ .location = 0, .class = .int } },
10420 .{ .reg = .{ .location = 5, .class = .int } },
10421 .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10422 } },
10423 .DJSk16 = .{ .slots = .{
10424 .{ .reg = .{ .location = 0, .class = .int } },
10425 .{ .reg = .{ .location = 5, .class = .int } },
10426 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } },
10427 } },
10428 .DJSk16ps2 = .{ .slots = .{
10429 .{ .reg = .{ .location = 0, .class = .int } },
10430 .{ .reg = .{ .location = 5, .class = .int } },
10431 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10432 } },
10433 .DJSk5 = .{ .slots = .{
10434 .{ .reg = .{ .location = 0, .class = .int } },
10435 .{ .reg = .{ .location = 5, .class = .int } },
10436 .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } },
10437 } },
10438 .DJUk12 = .{ .slots = .{
10439 .{ .reg = .{ .location = 0, .class = .int } },
10440 .{ .reg = .{ .location = 5, .class = .int } },
10441 .{ .imm = .{ .location = 10, .length = 12, .signedness = .unsigned } },
10442 } },
10443 .DJUk14 = .{ .slots = .{
10444 .{ .reg = .{ .location = 0, .class = .int } },
10445 .{ .reg = .{ .location = 5, .class = .int } },
10446 .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } },
10447 } },
10448 .DJUk3 = .{ .slots = .{
10449 .{ .reg = .{ .location = 0, .class = .int } },
10450 .{ .reg = .{ .location = 5, .class = .int } },
10451 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10452 } },
10453 .DJUk4 = .{ .slots = .{
10454 .{ .reg = .{ .location = 0, .class = .int } },
10455 .{ .reg = .{ .location = 5, .class = .int } },
10456 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10457 } },
10458 .DJUk5 = .{ .slots = .{
10459 .{ .reg = .{ .location = 0, .class = .int } },
10460 .{ .reg = .{ .location = 5, .class = .int } },
10461 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10462 } },
10463 .DJUk5Um5 = .{ .slots = .{
10464 .{ .reg = .{ .location = 0, .class = .int } },
10465 .{ .reg = .{ .location = 5, .class = .int } },
10466 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10467 .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } },
10468 } },
10469 .DJUk6 = .{ .slots = .{
10470 .{ .reg = .{ .location = 0, .class = .int } },
10471 .{ .reg = .{ .location = 5, .class = .int } },
10472 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
10473 } },
10474 .DJUk6Um6 = .{ .slots = .{
10475 .{ .reg = .{ .location = 0, .class = .int } },
10476 .{ .reg = .{ .location = 5, .class = .int } },
10477 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
10478 .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } },
10479 } },
10480 .DJUk8 = .{ .slots = .{
10481 .{ .reg = .{ .location = 0, .class = .int } },
10482 .{ .reg = .{ .location = 5, .class = .int } },
10483 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
10484 } },
10485 .DJUm5Uk5 = .{ .slots = .{
10486 .{ .reg = .{ .location = 0, .class = .int } },
10487 .{ .reg = .{ .location = 5, .class = .int } },
10488 .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } },
10489 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10490 } },
10491 .DJUm6Uk6 = .{ .slots = .{
10492 .{ .reg = .{ .location = 0, .class = .int } },
10493 .{ .reg = .{ .location = 5, .class = .int } },
10494 .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } },
10495 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
10496 } },
10497 .DKJ = .{ .slots = .{
10498 .{ .reg = .{ .location = 0, .class = .int } },
10499 .{ .reg = .{ .location = 10, .class = .int } },
10500 .{ .reg = .{ .location = 5, .class = .int } },
10501 } },
10502 .DSj20 = .{ .slots = .{
10503 .{ .reg = .{ .location = 0, .class = .int } },
10504 .{ .imm = .{ .location = 5, .length = 20, .signedness = .signed } },
10505 } },
10506 .DTj = .{ .slots = .{
10507 .{ .reg = .{ .location = 0, .class = .int } },
10508 .{ .reg = .{ .location = 5, .class = .lbt_scratch } },
10509 } },
10510 .DUj5 = .{ .slots = .{
10511 .{ .reg = .{ .location = 0, .class = .int } },
10512 .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } },
10513 } },
10514 .DUj5Uk8 = .{ .slots = .{
10515 .{ .reg = .{ .location = 0, .class = .int } },
10516 .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } },
10517 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
10518 } },
10519 .DUk14 = .{ .slots = .{
10520 .{ .reg = .{ .location = 0, .class = .int } },
10521 .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } },
10522 } },
10523 .DUk4 = .{ .slots = .{
10524 .{ .reg = .{ .location = 0, .class = .int } },
10525 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10526 } },
10527 .DUk8 = .{ .slots = .{
10528 .{ .reg = .{ .location = 0, .class = .int } },
10529 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
10530 } },
10531 .DVjUk1 = .{ .slots = .{
10532 .{ .reg = .{ .location = 0, .class = .int } },
10533 .{ .reg = .{ .location = 5, .class = .lsx } },
10534 .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } },
10535 } },
10536 .DVjUk2 = .{ .slots = .{
10537 .{ .reg = .{ .location = 0, .class = .int } },
10538 .{ .reg = .{ .location = 5, .class = .lsx } },
10539 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
10540 } },
10541 .DVjUk3 = .{ .slots = .{
10542 .{ .reg = .{ .location = 0, .class = .int } },
10543 .{ .reg = .{ .location = 5, .class = .lsx } },
10544 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10545 } },
10546 .DVjUk4 = .{ .slots = .{
10547 .{ .reg = .{ .location = 0, .class = .int } },
10548 .{ .reg = .{ .location = 5, .class = .lsx } },
10549 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10550 } },
10551 .DXjUk2 = .{ .slots = .{
10552 .{ .reg = .{ .location = 0, .class = .int } },
10553 .{ .reg = .{ .location = 5, .class = .lasx } },
10554 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
10555 } },
10556 .DXjUk3 = .{ .slots = .{
10557 .{ .reg = .{ .location = 0, .class = .int } },
10558 .{ .reg = .{ .location = 5, .class = .lasx } },
10559 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10560 } },
10561 .EMPTY = .{ .slots = .{} },
10562 .FdCj = .{ .slots = .{
10563 .{ .reg = .{ .location = 0, .class = .fp } },
10564 .{ .reg = .{ .location = 5, .class = .fcc } },
10565 } },
10566 .FdFj = .{ .slots = .{
10567 .{ .reg = .{ .location = 0, .class = .fp } },
10568 .{ .reg = .{ .location = 5, .class = .fp } },
10569 } },
10570 .FdFjFk = .{ .slots = .{
10571 .{ .reg = .{ .location = 0, .class = .fp } },
10572 .{ .reg = .{ .location = 5, .class = .fp } },
10573 .{ .reg = .{ .location = 10, .class = .fp } },
10574 } },
10575 .FdFjFkCa = .{ .slots = .{
10576 .{ .reg = .{ .location = 0, .class = .fp } },
10577 .{ .reg = .{ .location = 5, .class = .fp } },
10578 .{ .reg = .{ .location = 10, .class = .fp } },
10579 .{ .reg = .{ .location = 15, .class = .fcc } },
10580 } },
10581 .FdFjFkFa = .{ .slots = .{
10582 .{ .reg = .{ .location = 0, .class = .fp } },
10583 .{ .reg = .{ .location = 5, .class = .fp } },
10584 .{ .reg = .{ .location = 10, .class = .fp } },
10585 .{ .reg = .{ .location = 15, .class = .fp } },
10586 } },
10587 .FdJ = .{ .slots = .{
10588 .{ .reg = .{ .location = 0, .class = .fp } },
10589 .{ .reg = .{ .location = 5, .class = .int } },
10590 } },
10591 .FdJK = .{ .slots = .{
10592 .{ .reg = .{ .location = 0, .class = .fp } },
10593 .{ .reg = .{ .location = 5, .class = .int } },
10594 .{ .reg = .{ .location = 10, .class = .int } },
10595 } },
10596 .FdJSk12 = .{ .slots = .{
10597 .{ .reg = .{ .location = 0, .class = .fp } },
10598 .{ .reg = .{ .location = 5, .class = .int } },
10599 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10600 } },
10601 .J = .{ .slots = .{
10602 .{ .reg = .{ .location = 5, .class = .int } },
10603 } },
10604 .JDSk16ps2 = .{ .slots = .{
10605 .{ .reg = .{ .location = 5, .class = .int } },
10606 .{ .reg = .{ .location = 0, .class = .int } },
10607 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10608 } },
10609 .JK = .{ .slots = .{
10610 .{ .reg = .{ .location = 5, .class = .int } },
10611 .{ .reg = .{ .location = 10, .class = .int } },
10612 } },
10613 .JKUd4 = .{ .slots = .{
10614 .{ .reg = .{ .location = 5, .class = .int } },
10615 .{ .reg = .{ .location = 10, .class = .int } },
10616 .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } },
10617 } },
10618 .JKUd5 = .{ .slots = .{
10619 .{ .reg = .{ .location = 5, .class = .int } },
10620 .{ .reg = .{ .location = 10, .class = .int } },
10621 .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } },
10622 } },
10623 .JSd5k16 = .{ .slots = .{
10624 .{ .reg = .{ .location = 5, .class = .int } },
10625 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10626 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } },
10627 } },
10628 .JSd5k16ps2 = .{ .slots = .{
10629 .{ .reg = .{ .location = 5, .class = .int } },
10630 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10631 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10632 } },
10633 .JUd4Uk5 = .{ .slots = .{
10634 .{ .reg = .{ .location = 5, .class = .int } },
10635 .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } },
10636 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10637 } },
10638 .JUd5 = .{ .slots = .{
10639 .{ .reg = .{ .location = 5, .class = .int } },
10640 .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } },
10641 } },
10642 .JUd5Sk12 = .{ .slots = .{
10643 .{ .reg = .{ .location = 5, .class = .int } },
10644 .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } },
10645 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10646 } },
10647 .JUk3 = .{ .slots = .{
10648 .{ .reg = .{ .location = 5, .class = .int } },
10649 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10650 } },
10651 .JUk4 = .{ .slots = .{
10652 .{ .reg = .{ .location = 5, .class = .int } },
10653 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10654 } },
10655 .JUk5 = .{ .slots = .{
10656 .{ .reg = .{ .location = 5, .class = .int } },
10657 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10658 } },
10659 .JUk5Ud4 = .{ .slots = .{
10660 .{ .reg = .{ .location = 5, .class = .int } },
10661 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10662 .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } },
10663 } },
10664 .JUk6 = .{ .slots = .{
10665 .{ .reg = .{ .location = 5, .class = .int } },
10666 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
10667 } },
10668 .JUk8 = .{ .slots = .{
10669 .{ .reg = .{ .location = 5, .class = .int } },
10670 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
10671 } },
10672 .Sd10k16 = .{ .slots = .{
10673 .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } },
10674 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } },
10675 } },
10676 .Sd10k16ps2 = .{ .slots = .{
10677 .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } },
10678 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10679 } },
10680 .Sd5k16 = .{ .slots = .{
10681 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10682 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } },
10683 } },
10684 .Sd5k16ps2 = .{ .slots = .{
10685 .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } },
10686 .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10687 } },
10688 .TdJ = .{ .slots = .{
10689 .{ .reg = .{ .location = 0, .class = .lbt_scratch } },
10690 .{ .reg = .{ .location = 5, .class = .int } },
10691 } },
10692 .Ud15 = .{ .slots = .{
10693 .{ .imm = .{ .location = 0, .length = 15, .signedness = .unsigned } },
10694 } },
10695 .Ud5JK = .{ .slots = .{
10696 .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } },
10697 .{ .reg = .{ .location = 5, .class = .int } },
10698 .{ .reg = .{ .location = 10, .class = .int } },
10699 } },
10700 .Ud5JSk12 = .{ .slots = .{
10701 .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } },
10702 .{ .reg = .{ .location = 5, .class = .int } },
10703 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10704 } },
10705 .Uj3 = .{ .slots = .{
10706 .{ .imm = .{ .location = 5, .length = 3, .signedness = .unsigned } },
10707 } },
10708 .VdJ = .{ .slots = .{
10709 .{ .reg = .{ .location = 0, .class = .lsx } },
10710 .{ .reg = .{ .location = 5, .class = .int } },
10711 } },
10712 .VdJK = .{ .slots = .{
10713 .{ .reg = .{ .location = 0, .class = .lsx } },
10714 .{ .reg = .{ .location = 5, .class = .int } },
10715 .{ .reg = .{ .location = 10, .class = .int } },
10716 } },
10717 .VdJSk10 = .{ .slots = .{
10718 .{ .reg = .{ .location = 0, .class = .lsx } },
10719 .{ .reg = .{ .location = 5, .class = .int } },
10720 .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } },
10721 } },
10722 .VdJSk10ps2 = .{ .slots = .{
10723 .{ .reg = .{ .location = 0, .class = .lsx } },
10724 .{ .reg = .{ .location = 5, .class = .int } },
10725 .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10726 } },
10727 .VdJSk11 = .{ .slots = .{
10728 .{ .reg = .{ .location = 0, .class = .lsx } },
10729 .{ .reg = .{ .location = 5, .class = .int } },
10730 .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } },
10731 } },
10732 .VdJSk11ps1 = .{ .slots = .{
10733 .{ .reg = .{ .location = 0, .class = .lsx } },
10734 .{ .reg = .{ .location = 5, .class = .int } },
10735 .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } },
10736 } },
10737 .VdJSk12 = .{ .slots = .{
10738 .{ .reg = .{ .location = 0, .class = .lsx } },
10739 .{ .reg = .{ .location = 5, .class = .int } },
10740 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10741 } },
10742 .VdJSk8Un1 = .{ .slots = .{
10743 .{ .reg = .{ .location = 0, .class = .lsx } },
10744 .{ .reg = .{ .location = 5, .class = .int } },
10745 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10746 .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } },
10747 } },
10748 .VdJSk8Un2 = .{ .slots = .{
10749 .{ .reg = .{ .location = 0, .class = .lsx } },
10750 .{ .reg = .{ .location = 5, .class = .int } },
10751 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10752 .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } },
10753 } },
10754 .VdJSk8Un3 = .{ .slots = .{
10755 .{ .reg = .{ .location = 0, .class = .lsx } },
10756 .{ .reg = .{ .location = 5, .class = .int } },
10757 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10758 .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } },
10759 } },
10760 .VdJSk8Un4 = .{ .slots = .{
10761 .{ .reg = .{ .location = 0, .class = .lsx } },
10762 .{ .reg = .{ .location = 5, .class = .int } },
10763 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10764 .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } },
10765 } },
10766 .VdJSk8ps1Un3 = .{ .slots = .{
10767 .{ .reg = .{ .location = 0, .class = .lsx } },
10768 .{ .reg = .{ .location = 5, .class = .int } },
10769 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } },
10770 .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } },
10771 } },
10772 .VdJSk8ps2Un2 = .{ .slots = .{
10773 .{ .reg = .{ .location = 0, .class = .lsx } },
10774 .{ .reg = .{ .location = 5, .class = .int } },
10775 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10776 .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } },
10777 } },
10778 .VdJSk8ps3Un1 = .{ .slots = .{
10779 .{ .reg = .{ .location = 0, .class = .lsx } },
10780 .{ .reg = .{ .location = 5, .class = .int } },
10781 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } },
10782 .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } },
10783 } },
10784 .VdJSk9 = .{ .slots = .{
10785 .{ .reg = .{ .location = 0, .class = .lsx } },
10786 .{ .reg = .{ .location = 5, .class = .int } },
10787 .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } },
10788 } },
10789 .VdJSk9ps3 = .{ .slots = .{
10790 .{ .reg = .{ .location = 0, .class = .lsx } },
10791 .{ .reg = .{ .location = 5, .class = .int } },
10792 .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } },
10793 } },
10794 .VdJUk1 = .{ .slots = .{
10795 .{ .reg = .{ .location = 0, .class = .lsx } },
10796 .{ .reg = .{ .location = 5, .class = .int } },
10797 .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } },
10798 } },
10799 .VdJUk2 = .{ .slots = .{
10800 .{ .reg = .{ .location = 0, .class = .lsx } },
10801 .{ .reg = .{ .location = 5, .class = .int } },
10802 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
10803 } },
10804 .VdJUk3 = .{ .slots = .{
10805 .{ .reg = .{ .location = 0, .class = .lsx } },
10806 .{ .reg = .{ .location = 5, .class = .int } },
10807 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10808 } },
10809 .VdJUk4 = .{ .slots = .{
10810 .{ .reg = .{ .location = 0, .class = .lsx } },
10811 .{ .reg = .{ .location = 5, .class = .int } },
10812 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10813 } },
10814 .VdSj13 = .{ .slots = .{
10815 .{ .reg = .{ .location = 0, .class = .lsx } },
10816 .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } },
10817 } },
10818 .VdUj5Uk5 = .{ .slots = .{
10819 .{ .reg = .{ .location = 0, .class = .lsx } },
10820 .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } },
10821 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10822 } },
10823 .VdVj = .{ .slots = .{
10824 .{ .reg = .{ .location = 0, .class = .lsx } },
10825 .{ .reg = .{ .location = 5, .class = .lsx } },
10826 } },
10827 .VdVjK = .{ .slots = .{
10828 .{ .reg = .{ .location = 0, .class = .lsx } },
10829 .{ .reg = .{ .location = 5, .class = .lsx } },
10830 .{ .reg = .{ .location = 10, .class = .int } },
10831 } },
10832 .VdVjSk5 = .{ .slots = .{
10833 .{ .reg = .{ .location = 0, .class = .lsx } },
10834 .{ .reg = .{ .location = 5, .class = .lsx } },
10835 .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } },
10836 } },
10837 .VdVjUk1 = .{ .slots = .{
10838 .{ .reg = .{ .location = 0, .class = .lsx } },
10839 .{ .reg = .{ .location = 5, .class = .lsx } },
10840 .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } },
10841 } },
10842 .VdVjUk2 = .{ .slots = .{
10843 .{ .reg = .{ .location = 0, .class = .lsx } },
10844 .{ .reg = .{ .location = 5, .class = .lsx } },
10845 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
10846 } },
10847 .VdVjUk3 = .{ .slots = .{
10848 .{ .reg = .{ .location = 0, .class = .lsx } },
10849 .{ .reg = .{ .location = 5, .class = .lsx } },
10850 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10851 } },
10852 .VdVjUk4 = .{ .slots = .{
10853 .{ .reg = .{ .location = 0, .class = .lsx } },
10854 .{ .reg = .{ .location = 5, .class = .lsx } },
10855 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
10856 } },
10857 .VdVjUk5 = .{ .slots = .{
10858 .{ .reg = .{ .location = 0, .class = .lsx } },
10859 .{ .reg = .{ .location = 5, .class = .lsx } },
10860 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10861 } },
10862 .VdVjUk6 = .{ .slots = .{
10863 .{ .reg = .{ .location = 0, .class = .lsx } },
10864 .{ .reg = .{ .location = 5, .class = .lsx } },
10865 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
10866 } },
10867 .VdVjUk7 = .{ .slots = .{
10868 .{ .reg = .{ .location = 0, .class = .lsx } },
10869 .{ .reg = .{ .location = 5, .class = .lsx } },
10870 .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } },
10871 } },
10872 .VdVjUk8 = .{ .slots = .{
10873 .{ .reg = .{ .location = 0, .class = .lsx } },
10874 .{ .reg = .{ .location = 5, .class = .lsx } },
10875 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
10876 } },
10877 .VdVjVk = .{ .slots = .{
10878 .{ .reg = .{ .location = 0, .class = .lsx } },
10879 .{ .reg = .{ .location = 5, .class = .lsx } },
10880 .{ .reg = .{ .location = 10, .class = .lsx } },
10881 } },
10882 .VdVjVkVa = .{ .slots = .{
10883 .{ .reg = .{ .location = 0, .class = .lsx } },
10884 .{ .reg = .{ .location = 5, .class = .lsx } },
10885 .{ .reg = .{ .location = 10, .class = .lsx } },
10886 .{ .reg = .{ .location = 15, .class = .lsx } },
10887 } },
10888 .XdJ = .{ .slots = .{
10889 .{ .reg = .{ .location = 0, .class = .lasx } },
10890 .{ .reg = .{ .location = 5, .class = .int } },
10891 } },
10892 .XdJK = .{ .slots = .{
10893 .{ .reg = .{ .location = 0, .class = .lasx } },
10894 .{ .reg = .{ .location = 5, .class = .int } },
10895 .{ .reg = .{ .location = 10, .class = .int } },
10896 } },
10897 .XdJSk10 = .{ .slots = .{
10898 .{ .reg = .{ .location = 0, .class = .lasx } },
10899 .{ .reg = .{ .location = 5, .class = .int } },
10900 .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } },
10901 } },
10902 .XdJSk10ps2 = .{ .slots = .{
10903 .{ .reg = .{ .location = 0, .class = .lasx } },
10904 .{ .reg = .{ .location = 5, .class = .int } },
10905 .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10906 } },
10907 .XdJSk11 = .{ .slots = .{
10908 .{ .reg = .{ .location = 0, .class = .lasx } },
10909 .{ .reg = .{ .location = 5, .class = .int } },
10910 .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } },
10911 } },
10912 .XdJSk11ps1 = .{ .slots = .{
10913 .{ .reg = .{ .location = 0, .class = .lasx } },
10914 .{ .reg = .{ .location = 5, .class = .int } },
10915 .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } },
10916 } },
10917 .XdJSk12 = .{ .slots = .{
10918 .{ .reg = .{ .location = 0, .class = .lasx } },
10919 .{ .reg = .{ .location = 5, .class = .int } },
10920 .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } },
10921 } },
10922 .XdJSk8Un2 = .{ .slots = .{
10923 .{ .reg = .{ .location = 0, .class = .lasx } },
10924 .{ .reg = .{ .location = 5, .class = .int } },
10925 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10926 .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } },
10927 } },
10928 .XdJSk8Un3 = .{ .slots = .{
10929 .{ .reg = .{ .location = 0, .class = .lasx } },
10930 .{ .reg = .{ .location = 5, .class = .int } },
10931 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10932 .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } },
10933 } },
10934 .XdJSk8Un4 = .{ .slots = .{
10935 .{ .reg = .{ .location = 0, .class = .lasx } },
10936 .{ .reg = .{ .location = 5, .class = .int } },
10937 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10938 .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } },
10939 } },
10940 .XdJSk8Un5 = .{ .slots = .{
10941 .{ .reg = .{ .location = 0, .class = .lasx } },
10942 .{ .reg = .{ .location = 5, .class = .int } },
10943 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } },
10944 .{ .imm = .{ .location = 18, .length = 5, .signedness = .unsigned } },
10945 } },
10946 .XdJSk8ps1Un4 = .{ .slots = .{
10947 .{ .reg = .{ .location = 0, .class = .lasx } },
10948 .{ .reg = .{ .location = 5, .class = .int } },
10949 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } },
10950 .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } },
10951 } },
10952 .XdJSk8ps2Un3 = .{ .slots = .{
10953 .{ .reg = .{ .location = 0, .class = .lasx } },
10954 .{ .reg = .{ .location = 5, .class = .int } },
10955 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } },
10956 .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } },
10957 } },
10958 .XdJSk8ps3Un2 = .{ .slots = .{
10959 .{ .reg = .{ .location = 0, .class = .lasx } },
10960 .{ .reg = .{ .location = 5, .class = .int } },
10961 .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } },
10962 .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } },
10963 } },
10964 .XdJSk9 = .{ .slots = .{
10965 .{ .reg = .{ .location = 0, .class = .lasx } },
10966 .{ .reg = .{ .location = 5, .class = .int } },
10967 .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } },
10968 } },
10969 .XdJSk9ps3 = .{ .slots = .{
10970 .{ .reg = .{ .location = 0, .class = .lasx } },
10971 .{ .reg = .{ .location = 5, .class = .int } },
10972 .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } },
10973 } },
10974 .XdJUk2 = .{ .slots = .{
10975 .{ .reg = .{ .location = 0, .class = .lasx } },
10976 .{ .reg = .{ .location = 5, .class = .int } },
10977 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
10978 } },
10979 .XdJUk3 = .{ .slots = .{
10980 .{ .reg = .{ .location = 0, .class = .lasx } },
10981 .{ .reg = .{ .location = 5, .class = .int } },
10982 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
10983 } },
10984 .XdSj13 = .{ .slots = .{
10985 .{ .reg = .{ .location = 0, .class = .lasx } },
10986 .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } },
10987 } },
10988 .XdUj5Uk5 = .{ .slots = .{
10989 .{ .reg = .{ .location = 0, .class = .lasx } },
10990 .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } },
10991 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
10992 } },
10993 .XdXj = .{ .slots = .{
10994 .{ .reg = .{ .location = 0, .class = .lasx } },
10995 .{ .reg = .{ .location = 5, .class = .lasx } },
10996 } },
10997 .XdXjK = .{ .slots = .{
10998 .{ .reg = .{ .location = 0, .class = .lasx } },
10999 .{ .reg = .{ .location = 5, .class = .lasx } },
11000 .{ .reg = .{ .location = 10, .class = .int } },
11001 } },
11002 .XdXjSk5 = .{ .slots = .{
11003 .{ .reg = .{ .location = 0, .class = .lasx } },
11004 .{ .reg = .{ .location = 5, .class = .lasx } },
11005 .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } },
11006 } },
11007 .XdXjUk1 = .{ .slots = .{
11008 .{ .reg = .{ .location = 0, .class = .lasx } },
11009 .{ .reg = .{ .location = 5, .class = .lasx } },
11010 .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } },
11011 } },
11012 .XdXjUk2 = .{ .slots = .{
11013 .{ .reg = .{ .location = 0, .class = .lasx } },
11014 .{ .reg = .{ .location = 5, .class = .lasx } },
11015 .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } },
11016 } },
11017 .XdXjUk3 = .{ .slots = .{
11018 .{ .reg = .{ .location = 0, .class = .lasx } },
11019 .{ .reg = .{ .location = 5, .class = .lasx } },
11020 .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } },
11021 } },
11022 .XdXjUk4 = .{ .slots = .{
11023 .{ .reg = .{ .location = 0, .class = .lasx } },
11024 .{ .reg = .{ .location = 5, .class = .lasx } },
11025 .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } },
11026 } },
11027 .XdXjUk5 = .{ .slots = .{
11028 .{ .reg = .{ .location = 0, .class = .lasx } },
11029 .{ .reg = .{ .location = 5, .class = .lasx } },
11030 .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } },
11031 } },
11032 .XdXjUk6 = .{ .slots = .{
11033 .{ .reg = .{ .location = 0, .class = .lasx } },
11034 .{ .reg = .{ .location = 5, .class = .lasx } },
11035 .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } },
11036 } },
11037 .XdXjUk7 = .{ .slots = .{
11038 .{ .reg = .{ .location = 0, .class = .lasx } },
11039 .{ .reg = .{ .location = 5, .class = .lasx } },
11040 .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } },
11041 } },
11042 .XdXjUk8 = .{ .slots = .{
11043 .{ .reg = .{ .location = 0, .class = .lasx } },
11044 .{ .reg = .{ .location = 5, .class = .lasx } },
11045 .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } },
11046 } },
11047 .XdXjXk = .{ .slots = .{
11048 .{ .reg = .{ .location = 0, .class = .lasx } },
11049 .{ .reg = .{ .location = 5, .class = .lasx } },
11050 .{ .reg = .{ .location = 10, .class = .lasx } },
11051 } },
11052 .XdXjXkXa = .{ .slots = .{
11053 .{ .reg = .{ .location = 0, .class = .lasx } },
11054 .{ .reg = .{ .location = 5, .class = .lasx } },
11055 .{ .reg = .{ .location = 10, .class = .lasx } },
11056 .{ .reg = .{ .location = 15, .class = .lasx } },
11057 } },
11058 },
11059}