| author |  Veikka Tuominen <git@vexu.eu> 2020-03-12 22:42:01+02:00 |
| committer | Veikka Tuominen <git@vexu.eu> 2020-03-12 22:42:01+02:00 |
| log | 71d776c3be91f6b4e982b45fbfe03e3696a397f5 |
| tree | de9487bd41b3c646f19018e03285730b15c6142d |
| parent | 6dde769279aaa0cc09d13dd0670b74a8dd24f547 |
| signature |  Commit is signed but in an unrecognized format. |
add note to disabled tests, improve comptime cmpxchg
4 files changed, 23 insertions(+), 20 deletions(-)
lib- std
- atomic
- event
- src
- test
- stage1
- behavior
lib/std/atomic/stack.zig+5-5
| ... | @@ -38,8 +38,8 @@ pub fn Stack(comptime T: type) type { | ... | @@ -38,8 +38,8 @@ pub fn Stack(comptime T: type) type { |
| 38 | node.next = self.root; | 38 | node.next = self.root; |
| 39 | self.root = node; | 39 | self.root = node; |
| 40 | } else { | 40 | } else { |
| 41 | while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {} | 41 | while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {} |
| 42 | defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true); | 42 | defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst)); |
| 43 | 43 | ||
| 44 | node.next = self.root; | 44 | node.next = self.root; |
| 45 | self.root = node; | 45 | self.root = node; |
| ... | @@ -52,8 +52,8 @@ pub fn Stack(comptime T: type) type { | ... | @@ -52,8 +52,8 @@ pub fn Stack(comptime T: type) type { |
| 52 | self.root = root.next; | 52 | self.root = root.next; |
| 53 | return root; | 53 | return root; |
| 54 | } else { | 54 | } else { |
| 55 | while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {} | 55 | while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {} |
| 56 | defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true); | 56 | defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst)); |
| 57 | 57 | ||
| 58 | const root = self.root orelse return null; | 58 | const root = self.root orelse return null; |
| 59 | self.root = root.next; | 59 | self.root = root.next; |
| ... | @@ -164,7 +164,7 @@ fn startPuts(ctx: *Context) u8 { | ... | @@ -164,7 +164,7 @@ fn startPuts(ctx: *Context) u8 { |
| 164 | 164 | ||
| 165 | fn startGets(ctx: *Context) u8 { | 165 | fn startGets(ctx: *Context) u8 { |
| 166 | while (true) { | 166 | while (true) { |
| 167 | const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst) == true; | 167 | const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst); |
| 168 | 168 | ||
| 169 | while (ctx.stack.pop()) |node| { | 169 | while (ctx.stack.pop()) |node| { |
| 170 | std.time.sleep(1); // let the os scheduler be our fuzz | 170 | std.time.sleep(1); // let the os scheduler be our fuzz |
lib/std/event/channel.zig+3-6
| ... | @@ -169,8 +169,7 @@ pub fn Channel(comptime T: type) type { | ... | @@ -169,8 +169,7 @@ pub fn Channel(comptime T: type) type { |
| 169 | 169 | ||
| 170 | lock: while (true) { | 170 | lock: while (true) { |
| 171 | // set the lock flag | 171 | // set the lock flag |
| 172 | const prev_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst); | 172 | if (@atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst)) return; |
| 173 | if (prev_lock != 0) return; | ||
| 174 | 173 | ||
| 175 | // clear the need_dispatch flag since we're about to do it | 174 | // clear the need_dispatch flag since we're about to do it |
| 176 | @atomicStore(bool, &self.need_dispatch, false, .SeqCst); | 175 | @atomicStore(bool, &self.need_dispatch, false, .SeqCst); |
| ... | @@ -250,11 +249,9 @@ pub fn Channel(comptime T: type) type { | ... | @@ -250,11 +249,9 @@ pub fn Channel(comptime T: type) type { |
| 250 | } | 249 | } |
| 251 | 250 | ||
| 252 | // clear need-dispatch flag | 251 | // clear need-dispatch flag |
| 253 | const need_dispatch = @atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst); | 252 | if (@atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst)) continue; |
| 254 | if (need_dispatch) continue; | ||
| 255 | 253 | ||
| 256 | const my_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst); | 254 | assert(@atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst)); |
| 257 | assert(my_lock); | ||
| 258 | 255 | ||
| 259 | // we have to check again now that we unlocked | 256 | // we have to check again now that we unlocked |
| 260 | if (@atomicLoad(bool, &self.need_dispatch, .SeqCst)) continue :lock; | 257 | if (@atomicLoad(bool, &self.need_dispatch, .SeqCst)) continue :lock; |
src/ir.cpp+11-7
| ... | @@ -25215,21 +25215,25 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch | ... | @@ -25215,21 +25215,25 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch |
| 25215 | if (ptr_val == nullptr) | 25215 | if (ptr_val == nullptr) |
| 25216 | return ira->codegen->invalid_inst_gen; | 25216 | return ira->codegen->invalid_inst_gen; |
| 25217 | 25217 | ||
| 25218 | ZigValue *op1_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node); | 25218 | ZigValue *stored_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node); |
| 25219 | if (op1_val == nullptr) | 25219 | if (stored_val == nullptr) |
| 25220 | return ira->codegen->invalid_inst_gen; | 25220 | return ira->codegen->invalid_inst_gen; |
| 25221 | 25221 | ||
| 25222 | ZigValue *op2_val = ir_resolve_const(ira, casted_cmp_value, UndefBad); | 25222 | ZigValue *expected_val = ir_resolve_const(ira, casted_cmp_value, UndefBad); |
| 25223 | if (op2_val == nullptr) | 25223 | if (expected_val == nullptr) |
| 25224 | return ira->codegen->invalid_inst_gen; | ||
| 25225 | |||
| 25226 | ZigValue *new_val = ir_resolve_const(ira, casted_new_value, UndefBad); | ||
| 25227 | if (new_val == nullptr) | ||
| 25224 | return ira->codegen->invalid_inst_gen; | 25228 | return ira->codegen->invalid_inst_gen; |
| 25225 | 25229 | ||
| 25226 | bool eql = const_values_equal(ira->codegen, op1_val, op2_val); | 25230 | bool eql = const_values_equal(ira->codegen, stored_val, expected_val); |
| 25227 | IrInstGen *result = ir_const(ira, &instruction->base.base, result_type); | 25231 | IrInstGen *result = ir_const(ira, &instruction->base.base, result_type); |
| 25228 | if (eql) { | 25232 | if (eql) { |
| 25229 | ir_analyze_store_ptr(ira, &instruction->base.base, casted_ptr, casted_new_value, false); | 25233 | copy_const_val(ira->codegen, stored_val, new_val); |
| 25230 | set_optional_value_to_null(result->value); | 25234 | set_optional_value_to_null(result->value); |
| 25231 | } else { | 25235 | } else { |
| 25232 | set_optional_payload(result->value, op1_val); | 25236 | set_optional_payload(result->value, stored_val); |
| 25233 | } | 25237 | } |
| 25234 | return result; | 25238 | return result; |
| 25235 | } | 25239 | } |
test/stage1/behavior/atomics.zig+4-2
| ... | @@ -149,6 +149,7 @@ fn testAtomicStore() void { | ... | @@ -149,6 +149,7 @@ fn testAtomicStore() void { |
| 149 | } | 149 | } |
| 150 | 150 | ||
| 151 | test "atomicrmw with floats" { | 151 | test "atomicrmw with floats" { |
| 152 | // TODO https://github.com/ziglang/zig/issues/4457 | ||
| 152 | if (builtin.arch == .aarch64 or builtin.arch == .arm or builtin.arch == .riscv64) | 153 | if (builtin.arch == .aarch64 or builtin.arch == .arm or builtin.arch == .riscv64) |
| 153 | return error.SkipZigTest; | 154 | return error.SkipZigTest; |
| 154 | testAtomicRmwFloat(); | 155 | testAtomicRmwFloat(); |
| ... | @@ -167,8 +168,6 @@ fn testAtomicRmwFloat() void { | ... | @@ -167,8 +168,6 @@ fn testAtomicRmwFloat() void { |
| 167 | } | 168 | } |
| 168 | 169 | ||
| 169 | test "atomicrmw with ints" { | 170 | test "atomicrmw with ints" { |
| 170 | if (builtin.arch == .mipsel) | ||
| 171 | return error.SkipZigTest; | ||
| 172 | testAtomicRmwInt(); | 171 | testAtomicRmwInt(); |
| 173 | comptime testAtomicRmwInt(); | 172 | comptime testAtomicRmwInt(); |
| 174 | } | 173 | } |
| ... | @@ -189,6 +188,9 @@ fn testAtomicRmwInt() void { | ... | @@ -189,6 +188,9 @@ fn testAtomicRmwInt() void { |
| 189 | expect(x == 0xff); | 188 | expect(x == 0xff); |
| 190 | _ = @atomicRmw(u8, &x, .Xor, 2, .SeqCst); | 189 | _ = @atomicRmw(u8, &x, .Xor, 2, .SeqCst); |
| 191 | expect(x == 0xfd); | 190 | expect(x == 0xfd); |
| 191 | |||
| 192 | // TODO https://github.com/ziglang/zig/issues/4724 | ||
| 193 | if (builtin.arch == .mipsel) return; | ||
| 192 | _ = @atomicRmw(u8, &x, .Max, 1, .SeqCst); | 194 | _ = @atomicRmw(u8, &x, .Max, 1, .SeqCst); |
| 193 | expect(x == 0xfd); | 195 | expect(x == 0xfd); |
| 194 | _ = @atomicRmw(u8, &x, .Min, 1, .SeqCst); | 196 | _ = @atomicRmw(u8, &x, .Min, 1, .SeqCst); |