authorgravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-12 22:42:01+02:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-12 22:42:01+02:00
log71d776c3be91f6b4e982b45fbfe03e3696a397f5
treede9487bd41b3c646f19018e03285730b15c6142d
parent6dde769279aaa0cc09d13dd0670b74a8dd24f547
signaturelock-open Commit is signed but in an unrecognized format.

add note to disabled tests, improve comptime cmpxchg

4 files changed, 23 insertions(+), 20 deletions(-)

lib/std/atomic/stack.zig+5-5
......@@ -38,8 +38,8 @@ pub fn Stack(comptime T: type) type {
3838 node.next = self.root;
3939 self.root = node;
4040 } else {
41 while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
42 defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
41 while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {}
42 defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst));
4343
4444 node.next = self.root;
4545 self.root = node;
......@@ -52,8 +52,8 @@ pub fn Stack(comptime T: type) type {
5252 self.root = root.next;
5353 return root;
5454 } else {
55 while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
56 defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
55 while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst)) {}
56 defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst));
5757
5858 const root = self.root orelse return null;
5959 self.root = root.next;
......@@ -164,7 +164,7 @@ fn startPuts(ctx: *Context) u8 {
164164
165165fn startGets(ctx: *Context) u8 {
166166 while (true) {
167 const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst) == true;
167 const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst);
168168
169169 while (ctx.stack.pop()) |node| {
170170 std.time.sleep(1); // let the os scheduler be our fuzz
lib/std/event/channel.zig+3-6
......@@ -169,8 +169,7 @@ pub fn Channel(comptime T: type) type {
169169
170170 lock: while (true) {
171171 // set the lock flag
172 const prev_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst);
173 if (prev_lock != 0) return;
172 if (@atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst)) return;
174173
175174 // clear the need_dispatch flag since we're about to do it
176175 @atomicStore(bool, &self.need_dispatch, false, .SeqCst);
......@@ -250,11 +249,9 @@ pub fn Channel(comptime T: type) type {
250249 }
251250
252251 // clear need-dispatch flag
253 const need_dispatch = @atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst);
254 if (need_dispatch) continue;
252 if (@atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst)) continue;
255253
256 const my_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst);
257 assert(my_lock);
254 assert(@atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst));
258255
259256 // we have to check again now that we unlocked
260257 if (@atomicLoad(bool, &self.need_dispatch, .SeqCst)) continue :lock;
src/ir.cpp+11-7
......@@ -25215,21 +25215,25 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch
2521525215 if (ptr_val == nullptr)
2521625216 return ira->codegen->invalid_inst_gen;
2521725217
25218 ZigValue *op1_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node);
25219 if (op1_val == nullptr)
25218 ZigValue *stored_val = const_ptr_pointee(ira, ira->codegen, ptr_val, instruction->base.base.source_node);
25219 if (stored_val == nullptr)
2522025220 return ira->codegen->invalid_inst_gen;
2522125221
25222 ZigValue *op2_val = ir_resolve_const(ira, casted_cmp_value, UndefBad);
25223 if (op2_val == nullptr)
25222 ZigValue *expected_val = ir_resolve_const(ira, casted_cmp_value, UndefBad);
25223 if (expected_val == nullptr)
25224 return ira->codegen->invalid_inst_gen;
25225
25226 ZigValue *new_val = ir_resolve_const(ira, casted_new_value, UndefBad);
25227 if (new_val == nullptr)
2522425228 return ira->codegen->invalid_inst_gen;
2522525229
25226 bool eql = const_values_equal(ira->codegen, op1_val, op2_val);
25230 bool eql = const_values_equal(ira->codegen, stored_val, expected_val);
2522725231 IrInstGen *result = ir_const(ira, &instruction->base.base, result_type);
2522825232 if (eql) {
25229 ir_analyze_store_ptr(ira, &instruction->base.base, casted_ptr, casted_new_value, false);
25233 copy_const_val(ira->codegen, stored_val, new_val);
2523025234 set_optional_value_to_null(result->value);
2523125235 } else {
25232 set_optional_payload(result->value, op1_val);
25236 set_optional_payload(result->value, stored_val);
2523325237 }
2523425238 return result;
2523525239 }
test/stage1/behavior/atomics.zig+4-2
......@@ -149,6 +149,7 @@ fn testAtomicStore() void {
149149}
150150
151151test "atomicrmw with floats" {
152 // TODO https://github.com/ziglang/zig/issues/4457
152153 if (builtin.arch == .aarch64 or builtin.arch == .arm or builtin.arch == .riscv64)
153154 return error.SkipZigTest;
154155 testAtomicRmwFloat();
......@@ -167,8 +168,6 @@ fn testAtomicRmwFloat() void {
167168}
168169
169170test "atomicrmw with ints" {
170 if (builtin.arch == .mipsel)
171 return error.SkipZigTest;
172171 testAtomicRmwInt();
173172 comptime testAtomicRmwInt();
174173}
......@@ -189,6 +188,9 @@ fn testAtomicRmwInt() void {
189188 expect(x == 0xff);
190189 _ = @atomicRmw(u8, &x, .Xor, 2, .SeqCst);
191190 expect(x == 0xfd);
191
192 // TODO https://github.com/ziglang/zig/issues/4724
193 if (builtin.arch == .mipsel) return;
192194 _ = @atomicRmw(u8, &x, .Max, 1, .SeqCst);
193195 expect(x == 0xfd);
194196 _ = @atomicRmw(u8, &x, .Min, 1, .SeqCst);