authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-02-20 19:08:37+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-02-22 21:56:34+01:00
log71dda25f14f2eb8315cd42f3edabd9386b4fd012
treefc1e332d4e60872ea121ea93be94e203238682cf
parent25d313f9115a939dfa1ffd65d00a392b30f235e3

x64: add basic impl of minimum builtin for ints


3 files changed, 49 insertions(+), 4 deletions(-)

src/arch/x86_64/CodeGen.zig+39-4
......@@ -1072,10 +1072,44 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
10721072
10731073fn airMin(self: *Self, inst: Air.Inst.Index) !void {
10741074 const bin_op = self.air.instructions.items(.data)[inst].bin_op;
1075 const result: MCValue = if (self.liveness.isUnused(inst))
1076 .dead
1077 else
1078 return self.fail("TODO implement min for {}", .{self.target.cpu.arch});
1075 if (self.liveness.isUnused(inst)) {
1076 return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
1077 }
1078
1079 const ty = self.air.typeOfIndex(inst);
1080 if (ty.zigTypeTag() != .Int) {
1081 return self.fail("TODO implement min for type {}", .{ty});
1082 }
1083 const signedness = ty.intInfo(self.target.*).signedness;
1084 const result: MCValue = result: {
1085 // TODO improve by checking if any operand can be reused.
1086 // TODO audit register allocation
1087 const lhs = try self.resolveInst(bin_op.lhs);
1088 lhs.freezeIfRegister(&self.register_manager);
1089 defer lhs.unfreezeIfRegister(&self.register_manager);
1090
1091 const lhs_reg = try self.copyToTmpRegister(ty, lhs);
1092 self.register_manager.freezeRegs(&.{lhs_reg});
1093 defer self.register_manager.unfreezeRegs(&.{lhs_reg});
1094
1095 const rhs_mcv = try self.limitImmediateType(bin_op.rhs, i32);
1096 rhs_mcv.freezeIfRegister(&self.register_manager);
1097 defer rhs_mcv.unfreezeIfRegister(&self.register_manager);
1098
1099 try self.genBinMathOpMir(.cmp, ty, .{ .register = lhs_reg }, rhs_mcv);
1100
1101 const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ty, rhs_mcv);
1102 _ = try self.addInst(.{
1103 .tag = if (signedness == .signed) .cond_mov_lt else .cond_mov_below,
1104 .ops = (Mir.Ops{
1105 .reg1 = dst_mcv.register,
1106 .reg2 = lhs_reg,
1107 }).encode(),
1108 .data = undefined,
1109 });
1110
1111 break :result dst_mcv;
1112 };
10791113 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
10801114}
10811115
......@@ -3283,6 +3317,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
32833317 // There are 2 operands, destination and source.
32843318 // Either one, but not both, can be a memory operand.
32853319 // Source operand can be an immediate, 8 bits or 32 bits.
3320 // TODO this looks wrong. Why do simply reuse lhs without checking if it is dead or alive?
32863321 const dst_mcv = if (lhs.isImmediate() or (lhs.isMemory() and rhs.isMemory()))
32873322 MCValue{ .register = try self.copyToTmpRegister(ty, lhs) }
32883323 else
src/arch/x86_64/Emit.zig+8
......@@ -162,6 +162,8 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
162162 => try emit.mirCondSetByte(tag, inst),
163163
164164 .cond_mov_eq => try emit.mirCondMov(.cmove, inst),
165 .cond_mov_lt => try emit.mirCondMov(.cmovl, inst),
166 .cond_mov_below => try emit.mirCondMov(.cmovb, inst),
165167
166168 .ret => try emit.mirRet(inst),
167169
......@@ -1180,6 +1182,10 @@ const Tag = enum {
11801182 cqo,
11811183 cmove,
11821184 cmovz,
1185 cmovl,
1186 cmovng,
1187 cmovb,
1188 cmovnae,
11831189
11841190 fn isSetCC(tag: Tag) bool {
11851191 return switch (tag) {
......@@ -1406,6 +1412,8 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
14061412 .lea => OpCode.oneByte(if (is_one_byte) 0x8c else 0x8d),
14071413 .imul => OpCode.twoByte(0x0f, 0xaf),
14081414 .cmove, .cmovz => OpCode.twoByte(0x0f, 0x44),
1415 .cmovb, .cmovnae => OpCode.twoByte(0x0f, 0x42),
1416 .cmovl, .cmovng => OpCode.twoByte(0x0f, 0x4c),
14091417 else => null,
14101418 },
14111419 .oi => return switch (tag) {
src/arch/x86_64/Mir.zig+2
......@@ -292,6 +292,8 @@ pub const Inst = struct {
292292 /// 0b10 reg1, dword ptr [reg2 + imm]
293293 /// 0b11 reg1, qword ptr [reg2 + imm]
294294 cond_mov_eq,
295 cond_mov_lt,
296 cond_mov_below,
295297
296298 /// ops flags: form:
297299 /// 0b00 reg1