authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-08-05 22:45:39+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-08-05 22:45:39+02:00
log75b267b7fb412dedaea7e593e2d7f66a71399147
tree47cb566e2cf958ef1cb4cea58d382baf00067bc1
parent11e2bb391ee13d0b91f241f9720a9ae877e5cc2a
parent184234141d97f2b24f00626a3ed82cb44f4e4235

Merge pull request '`std.Target`: bump baseline CPU for `powerpc64-(freebsd,linux)` to `pwr8`' (#36394) from alexrp/zig:ppc64-baseline-cpu into master

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/36394

2 files changed, 4 insertions(+), 3 deletions(-)

lib/std/Target.zig+1
......@@ -2081,6 +2081,7 @@ pub const Cpu = struct {
20812081 else => generic(arch),
20822082 },
20832083 .powerpc64 => switch (os.tag) {
2084 .linux, .freebsd => &powerpc.cpu.pwr8,
20842085 .openbsd => &powerpc.cpu.pwr9,
20852086 else => generic(arch),
20862087 },
test/behavior/floatop.zig+3-3
......@@ -228,7 +228,7 @@ test "vector cmp f32" {
228228 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
229229 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
230230 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest;
231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
232232 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
233233
234234 try testCmpVector(f32);
......@@ -250,7 +250,7 @@ test "vector cmp f128" {
250250 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
251251 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
252252 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
253 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .powerpc64le) return error.SkipZigTest;
253 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
254254 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
255255
256256 try testCmpVector(f128);
......@@ -260,7 +260,7 @@ test "vector cmp f128" {
260260test "vector cmp f80/c_longdouble" {
261261 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
262262 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
263 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .powerpc64le) return error.SkipZigTest;
263 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
264264 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
265265 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
266266