| author | |
| committer | |
| log | 76558f8c6b8361ab520ea77e4b4cd2bfc8f688ad |
| tree | d8731c7449e024527fd44a442e35477cd7d68aee |
| parent | 68bd82d0cc9b0cd07cde509c1c89a438b6d297c9 |
It appears to just be a 1:1 copy of riscv64, including the super weird sign
extension quirk for u32.
Contributes to #21671.1 files changed, 1 insertions(+), 1 deletions(-)
src/codegen/llvm.zig+1-1| ... | ... | @@ -12578,7 +12578,7 @@ fn ccAbiPromoteInt( |
| 12578 | 12578 | else => null, |
| 12579 | 12579 | }, |
| 12580 | 12580 | else => switch (target.cpu.arch) { |
| 12581 | .riscv64 => switch (int_info.bits) { | |
| 12581 | .loongarch64, .riscv64 => switch (int_info.bits) { | |
| 12582 | 12582 | 0...16 => int_info.signedness, |
| 12583 | 12583 | 32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug. |
| 12584 | 12584 | 17...31, 33...63 => int_info.signedness, |