authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-07 22:52:52+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-09 14:16:29+01:00
log77ca77cf144e3f7e8be53b6e4220a4efc313628b
treef7c23b14aa8f503f9358e4e312b9727b8c512e18
parentd66c97d0ef0434ce0814d1921877b9ffa877a645
signaturelock-open Commit is signed but in an unrecognized format.

stage2 ARM: make Mir.Inst.cond = .al default

2 files changed, 1 insertions(+), 60 deletions(-)

src/arch/arm/CodeGen.zig-59
...@@ -338,7 +338,6 @@ fn addInst(self: *Self, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {...@@ -338,7 +338,6 @@ fn addInst(self: *Self, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {
338fn addNop(self: *Self) error{OutOfMemory}!Mir.Inst.Index {338fn addNop(self: *Self) error{OutOfMemory}!Mir.Inst.Index {
339 return try self.addInst(.{339 return try self.addInst(.{
340 .tag = .nop,340 .tag = .nop,
341 .cond = .al,
342 .data = .{ .nop = {} },341 .data = .{ .nop = {} },
343 });342 });
344}343}
...@@ -371,7 +370,6 @@ fn gen(self: *Self) !void {...@@ -371,7 +370,6 @@ fn gen(self: *Self) !void {
371 // mov fp, sp370 // mov fp, sp
372 _ = try self.addInst(.{371 _ = try self.addInst(.{
373 .tag = .mov,372 .tag = .mov,
374 .cond = .al,
375 .data = .{ .rr_op = .{373 .data = .{ .rr_op = .{
376 .rd = .fp,374 .rd = .fp,
377 .rn = .r0,375 .rn = .r0,
...@@ -405,7 +403,6 @@ fn gen(self: *Self) !void {...@@ -405,7 +403,6 @@ fn gen(self: *Self) !void {
405403
406 self.mir_instructions.set(push_reloc, .{404 self.mir_instructions.set(push_reloc, .{
407 .tag = .push,405 .tag = .push,
408 .cond = .al,
409 .data = .{ .register_list = saved_regs },406 .data = .{ .register_list = saved_regs },
410 });407 });
411408
...@@ -416,7 +413,6 @@ fn gen(self: *Self) !void {...@@ -416,7 +413,6 @@ fn gen(self: *Self) !void {
416 if (Instruction.Operand.fromU32(stack_size)) |op| {413 if (Instruction.Operand.fromU32(stack_size)) |op| {
417 self.mir_instructions.set(sub_reloc, .{414 self.mir_instructions.set(sub_reloc, .{
418 .tag = .sub,415 .tag = .sub,
419 .cond = .al,
420 .data = .{ .rr_op = .{ .rd = .sp, .rn = .sp, .op = op } },416 .data = .{ .rr_op = .{ .rd = .sp, .rn = .sp, .op = op } },
421 });417 });
422 } else {418 } else {
...@@ -440,7 +436,6 @@ fn gen(self: *Self) !void {...@@ -440,7 +436,6 @@ fn gen(self: *Self) !void {
440 } else for (self.exitlude_jump_relocs.items) |jmp_reloc| {436 } else for (self.exitlude_jump_relocs.items) |jmp_reloc| {
441 self.mir_instructions.set(jmp_reloc, .{437 self.mir_instructions.set(jmp_reloc, .{
442 .tag = .b,438 .tag = .b,
443 .cond = .al,
444 .data = .{ .inst = @intCast(u32, self.mir_instructions.len) },439 .data = .{ .inst = @intCast(u32, self.mir_instructions.len) },
445 });440 });
446 }441 }
...@@ -452,7 +447,6 @@ fn gen(self: *Self) !void {...@@ -452,7 +447,6 @@ fn gen(self: *Self) !void {
452 // mov sp, fp447 // mov sp, fp
453 _ = try self.addInst(.{448 _ = try self.addInst(.{
454 .tag = .mov,449 .tag = .mov,
455 .cond = .al,
456 .data = .{ .rr_op = .{450 .data = .{ .rr_op = .{
457 .rd = .sp,451 .rd = .sp,
458 .rn = .r0,452 .rn = .r0,
...@@ -463,7 +457,6 @@ fn gen(self: *Self) !void {...@@ -463,7 +457,6 @@ fn gen(self: *Self) !void {
463 // pop {fp, pc}457 // pop {fp, pc}
464 _ = try self.addInst(.{458 _ = try self.addInst(.{
465 .tag = .pop,459 .tag = .pop,
466 .cond = .al,
467 .data = .{ .register_list = saved_regs },460 .data = .{ .register_list = saved_regs },
468 });461 });
469 } else {462 } else {
...@@ -1251,7 +1244,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1251,7 +1244,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12511244
1252 _ = try self.addInst(.{1245 _ = try self.addInst(.{
1253 .tag = tag,1246 .tag = tag,
1254 .cond = .al,
1255 .data = .{ .rr_offset = .{1247 .data = .{ .rr_offset = .{
1256 .rt = dst_reg,1248 .rt = dst_reg,
1257 .rn = base_mcv.register,1249 .rn = base_mcv.register,
...@@ -1262,7 +1254,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1262,7 +1254,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1262 2 => {1254 2 => {
1263 _ = try self.addInst(.{1255 _ = try self.addInst(.{
1264 .tag = .ldrh,1256 .tag = .ldrh,
1265 .cond = .al,
1266 .data = .{ .rr_extra_offset = .{1257 .data = .{ .rr_extra_offset = .{
1267 .rt = dst_reg,1258 .rt = dst_reg,
1268 .rn = base_mcv.register,1259 .rn = base_mcv.register,
...@@ -1406,7 +1397,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1406,7 +1397,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1406 .register => |dst_reg| {1397 .register => |dst_reg| {
1407 _ = try self.addInst(.{1398 _ = try self.addInst(.{
1408 .tag = .ldr,1399 .tag = .ldr,
1409 .cond = .al,
1410 .data = .{ .rr_offset = .{1400 .data = .{ .rr_offset = .{
1411 .rt = dst_reg,1401 .rt = dst_reg,
1412 .rn = reg,1402 .rn = reg,
...@@ -1430,7 +1420,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1430,7 +1420,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1430 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});1420 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});
1431 _ = try self.addInst(.{1421 _ = try self.addInst(.{
1432 .tag = .ldr,1422 .tag = .ldr,
1433 .cond = .al,
1434 .data = .{ .rr_offset = .{1423 .data = .{ .rr_offset = .{
1435 .rt = tmp_regs[0],1424 .rt = tmp_regs[0],
1436 .rn = reg,1425 .rn = reg,
...@@ -1439,7 +1428,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1439,7 +1428,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1439 });1428 });
1440 _ = try self.addInst(.{1429 _ = try self.addInst(.{
1441 .tag = .ldr,1430 .tag = .ldr,
1442 .cond = .al,
1443 .data = .{ .rr_offset = .{1431 .data = .{ .rr_offset = .{
1444 .rt = tmp_regs[1],1432 .rt = tmp_regs[1],
1445 .rn = reg,1433 .rn = reg,
...@@ -1465,7 +1453,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1465,7 +1453,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1465 };1453 };
1466 _ = try self.addInst(.{1454 _ = try self.addInst(.{
1467 .tag = .sub,1455 .tag = .sub,
1468 .cond = .al,
1469 .data = .{ .rr_op = .{1456 .data = .{ .rr_op = .{
1470 .rd = dst_reg,1457 .rd = dst_reg,
1471 .rn = .fp,1458 .rn = .fp,
...@@ -1479,7 +1466,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1479,7 +1466,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1479 };1466 };
1480 _ = try self.addInst(.{1467 _ = try self.addInst(.{
1481 .tag = .mov,1468 .tag = .mov,
1482 .cond = .al,
1483 .data = .{ .rr_op = .{1469 .data = .{ .rr_op = .{
1484 .rd = len_reg,1470 .rd = len_reg,
1485 .rn = .r0,1471 .rn = .r0,
...@@ -1560,7 +1546,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type...@@ -1560,7 +1546,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
1560 .register => |value_reg| {1546 .register => |value_reg| {
1561 _ = try self.addInst(.{1547 _ = try self.addInst(.{
1562 .tag = .str,1548 .tag = .str,
1563 .cond = .al,
1564 .data = .{ .rr_offset = .{1549 .data = .{ .rr_offset = .{
1565 .rt = value_reg,1550 .rt = value_reg,
1566 .rn = addr_reg,1551 .rn = addr_reg,
...@@ -1866,7 +1851,6 @@ fn genArmBinOpCode(...@@ -1866,7 +1851,6 @@ fn genArmBinOpCode(
18661851
1867 _ = try self.addInst(.{1852 _ = try self.addInst(.{
1868 .tag = tag,1853 .tag = tag,
1869 .cond = .al,
1870 .data = .{ .rr_op = .{1854 .data = .{ .rr_op = .{
1871 .rd = dst_reg,1855 .rd = dst_reg,
1872 .rn = op1,1856 .rn = op1,
...@@ -1879,7 +1863,6 @@ fn genArmBinOpCode(...@@ -1879,7 +1863,6 @@ fn genArmBinOpCode(
18791863
1880 _ = try self.addInst(.{1864 _ = try self.addInst(.{
1881 .tag = tag,1865 .tag = tag,
1882 .cond = .al,
1883 .data = .{ .rr_op = .{1866 .data = .{ .rr_op = .{
1884 .rd = dst_reg,1867 .rd = dst_reg,
1885 .rn = op1,1868 .rn = op1,
...@@ -1890,7 +1873,6 @@ fn genArmBinOpCode(...@@ -1890,7 +1873,6 @@ fn genArmBinOpCode(
1890 .cmp_eq => {1873 .cmp_eq => {
1891 _ = try self.addInst(.{1874 _ = try self.addInst(.{
1892 .tag = .cmp,1875 .tag = .cmp,
1893 .cond = .al,
1894 .data = .{ .rr_op = .{1876 .data = .{ .rr_op = .{
1895 .rd = .r0,1877 .rd = .r0,
1896 .rn = op1,1878 .rn = op1,
...@@ -1916,7 +1898,6 @@ fn genArmBinOpCode(...@@ -1916,7 +1898,6 @@ fn genArmBinOpCode(
19161898
1917 _ = try self.addInst(.{1899 _ = try self.addInst(.{
1918 .tag = tag,1900 .tag = tag,
1919 .cond = .al,
1920 .data = .{ .rr_shift = .{1901 .data = .{ .rr_shift = .{
1921 .rd = dst_reg,1902 .rd = dst_reg,
1922 .rm = op1,1903 .rm = op1,
...@@ -1993,7 +1974,6 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai...@@ -1993,7 +1974,6 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19931974
1994 _ = try self.addInst(.{1975 _ = try self.addInst(.{
1995 .tag = .mul,1976 .tag = .mul,
1996 .cond = .al,
1997 .data = .{ .rrr = .{1977 .data = .{ .rrr = .{
1998 .rd = dst_mcv.register,1978 .rd = dst_mcv.register,
1999 .rn = lhs_mcv.register,1979 .rn = lhs_mcv.register,
...@@ -2045,7 +2025,6 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind...@@ -2045,7 +2025,6 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind
20452025
2046 _ = try self.addInst(.{2026 _ = try self.addInst(.{
2047 .tag = .mul,2027 .tag = .mul,
2048 .cond = .al,
2049 .data = .{ .rrr = .{2028 .data = .{ .rrr = .{
2050 .rd = dst_mcv.register,2029 .rd = dst_mcv.register,
2051 .rn = lhs_mcv.register,2030 .rn = lhs_mcv.register,
...@@ -2066,7 +2045,6 @@ fn genArmInlineMemcpy(...@@ -2066,7 +2045,6 @@ fn genArmInlineMemcpy(
2066 // mov count, #02045 // mov count, #0
2067 _ = try self.addInst(.{2046 _ = try self.addInst(.{
2068 .tag = .mov,2047 .tag = .mov,
2069 .cond = .al,
2070 .data = .{ .rr_op = .{2048 .data = .{ .rr_op = .{
2071 .rd = count,2049 .rd = count,
2072 .rn = .r0,2050 .rn = .r0,
...@@ -2078,7 +2056,6 @@ fn genArmInlineMemcpy(...@@ -2078,7 +2056,6 @@ fn genArmInlineMemcpy(
2078 // cmp count, len2056 // cmp count, len
2079 _ = try self.addInst(.{2057 _ = try self.addInst(.{
2080 .tag = .cmp,2058 .tag = .cmp,
2081 .cond = .al,
2082 .data = .{ .rr_op = .{2059 .data = .{ .rr_op = .{
2083 .rd = .r0,2060 .rd = .r0,
2084 .rn = count,2061 .rn = count,
...@@ -2096,7 +2073,6 @@ fn genArmInlineMemcpy(...@@ -2096,7 +2073,6 @@ fn genArmInlineMemcpy(
2096 // ldrb tmp, [src, count]2073 // ldrb tmp, [src, count]
2097 _ = try self.addInst(.{2074 _ = try self.addInst(.{
2098 .tag = .ldrb,2075 .tag = .ldrb,
2099 .cond = .al,
2100 .data = .{ .rr_offset = .{2076 .data = .{ .rr_offset = .{
2101 .rt = tmp,2077 .rt = tmp,
2102 .rn = src,2078 .rn = src,
...@@ -2107,7 +2083,6 @@ fn genArmInlineMemcpy(...@@ -2107,7 +2083,6 @@ fn genArmInlineMemcpy(
2107 // strb tmp, [src, count]2083 // strb tmp, [src, count]
2108 _ = try self.addInst(.{2084 _ = try self.addInst(.{
2109 .tag = .strb,2085 .tag = .strb,
2110 .cond = .al,
2111 .data = .{ .rr_offset = .{2086 .data = .{ .rr_offset = .{
2112 .rt = tmp,2087 .rt = tmp,
2113 .rn = dst,2088 .rn = dst,
...@@ -2118,7 +2093,6 @@ fn genArmInlineMemcpy(...@@ -2118,7 +2093,6 @@ fn genArmInlineMemcpy(
2118 // add count, count, #12093 // add count, count, #1
2119 _ = try self.addInst(.{2094 _ = try self.addInst(.{
2120 .tag = .add,2095 .tag = .add,
2121 .cond = .al,
2122 .data = .{ .rr_op = .{2096 .data = .{ .rr_op = .{
2123 .rd = count,2097 .rd = count,
2124 .rn = count,2098 .rn = count,
...@@ -2129,7 +2103,6 @@ fn genArmInlineMemcpy(...@@ -2129,7 +2103,6 @@ fn genArmInlineMemcpy(
2129 // b loop2103 // b loop
2130 _ = try self.addInst(.{2104 _ = try self.addInst(.{
2131 .tag = .b,2105 .tag = .b,
2132 .cond = .al,
2133 .data = .{ .inst = @intCast(u32, self.mir_instructions.len - 5) },2106 .data = .{ .inst = @intCast(u32, self.mir_instructions.len - 5) },
2134 });2107 });
21352108
...@@ -2236,7 +2209,6 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {...@@ -2236,7 +2209,6 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
2236fn airBreakpoint(self: *Self) !void {2209fn airBreakpoint(self: *Self) !void {
2237 _ = try self.addInst(.{2210 _ = try self.addInst(.{
2238 .tag = .bkpt,2211 .tag = .bkpt,
2239 .cond = .al,
2240 .data = .{ .imm16 = 0 },2212 .data = .{ .imm16 = 0 },
2241 });2213 });
2242 return self.finishAirBookkeeping();2214 return self.finishAirBookkeeping();
...@@ -2348,14 +2320,12 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {...@@ -2348,14 +2320,12 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
2348 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {2320 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
2349 _ = try self.addInst(.{2321 _ = try self.addInst(.{
2350 .tag = .blx,2322 .tag = .blx,
2351 .cond = .al,
2352 .data = .{ .reg = .lr },2323 .data = .{ .reg = .lr },
2353 });2324 });
2354 } else {2325 } else {
2355 return self.fail("TODO fix blx emulation for ARM <v5", .{});2326 return self.fail("TODO fix blx emulation for ARM <v5", .{});
2356 // _ = try self.addInst(.{2327 // _ = try self.addInst(.{
2357 // .tag = .mov,2328 // .tag = .mov,
2358 // .cond = .al,
2359 // .data = .{ .rr_op = .{2329 // .data = .{ .rr_op = .{
2360 // .rd = .lr,2330 // .rd = .lr,
2361 // .rn = .r0,2331 // .rn = .r0,
...@@ -2364,7 +2334,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {...@@ -2364,7 +2334,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
2364 // });2334 // });
2365 // _ = try self.addInst(.{2335 // _ = try self.addInst(.{
2366 // .tag = .bx,2336 // .tag = .bx,
2367 // .cond = .al,
2368 // .data = .{ .reg = .lr },2337 // .data = .{ .reg = .lr },
2369 // });2338 // });
2370 }2339 }
...@@ -2539,7 +2508,6 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {...@@ -2539,7 +2508,6 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
2539 // bne ...2508 // bne ...
2540 _ = try self.addInst(.{2509 _ = try self.addInst(.{
2541 .tag = .cmp,2510 .tag = .cmp,
2542 .cond = .al,
2543 .data = .{ .rr_op = .{2511 .data = .{ .rr_op = .{
2544 .rd = .r0,2512 .rd = .r0,
2545 .rn = reg,2513 .rn = reg,
...@@ -2889,7 +2857,6 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {...@@ -2889,7 +2857,6 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
2889fn jump(self: *Self, inst: Mir.Inst.Index) !void {2857fn jump(self: *Self, inst: Mir.Inst.Index) !void {
2890 _ = try self.addInst(.{2858 _ = try self.addInst(.{
2891 .tag = .b,2859 .tag = .b,
2892 .cond = .al,
2893 .data = .{ .inst = inst },2860 .data = .{ .inst = inst },
2894 });2861 });
2895}2862}
...@@ -2973,7 +2940,6 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {...@@ -2973,7 +2940,6 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {
2973 // Emit a jump with a relocation. It will be patched up after the block ends.2940 // Emit a jump with a relocation. It will be patched up after the block ends.
2974 try block_data.relocs.append(self.gpa, try self.addInst(.{2941 try block_data.relocs.append(self.gpa, try self.addInst(.{
2975 .tag = .b,2942 .tag = .b,
2976 .cond = .al,
2977 .data = .{ .inst = undefined }, // populated later through performReloc2943 .data = .{ .inst = undefined }, // populated later through performReloc
2978 }));2944 }));
2979}2945}
...@@ -3029,7 +2995,6 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -3029,7 +2995,6 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
3029 if (mem.eql(u8, asm_source, "svc #0")) {2995 if (mem.eql(u8, asm_source, "svc #0")) {
3030 _ = try self.addInst(.{2996 _ = try self.addInst(.{
3031 .tag = .svc,2997 .tag = .svc,
3032 .cond = .al,
3033 .data = .{ .imm24 = 0 },2998 .data = .{ .imm24 = 0 },
3034 });2999 });
3035 } else {3000 } else {
...@@ -3135,7 +3100,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3135,7 +3100,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31353100
3136 _ = try self.addInst(.{3101 _ = try self.addInst(.{
3137 .tag = tag,3102 .tag = tag,
3138 .cond = .al,
3139 .data = .{ .rr_offset = .{3103 .data = .{ .rr_offset = .{
3140 .rt = reg,3104 .rt = reg,
3141 .rn = .fp,3105 .rn = .fp,
...@@ -3153,7 +3117,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3153,7 +3117,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31533117
3154 _ = try self.addInst(.{3118 _ = try self.addInst(.{
3155 .tag = .strh,3119 .tag = .strh,
3156 .cond = .al,
3157 .data = .{ .rr_extra_offset = .{3120 .data = .{ .rr_extra_offset = .{
3158 .rt = reg,3121 .rt = reg,
3159 .rn = .fp,3122 .rn = .fp,
...@@ -3200,7 +3163,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3200,7 +3163,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3200 };3163 };
3201 _ = try self.addInst(.{3164 _ = try self.addInst(.{
3202 .tag = .sub,3165 .tag = .sub,
3203 .cond = .al,
3204 .data = .{ .rr_op = .{3166 .data = .{ .rr_op = .{
3205 .rd = src_reg,3167 .rd = src_reg,
3206 .rn = .fp,3168 .rn = .fp,
...@@ -3215,7 +3177,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3215,7 +3177,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3215 };3177 };
3216 _ = try self.addInst(.{3178 _ = try self.addInst(.{
3217 .tag = .sub,3179 .tag = .sub,
3218 .cond = .al,
3219 .data = .{ .rr_op = .{3180 .data = .{ .rr_op = .{
3220 .rd = dst_reg,3181 .rd = dst_reg,
3221 .rn = .fp,3182 .rn = .fp,
...@@ -3230,7 +3191,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3230,7 +3191,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3230 };3191 };
3231 _ = try self.addInst(.{3192 _ = try self.addInst(.{
3232 .tag = .mov,3193 .tag = .mov,
3233 .cond = .al,
3234 .data = .{ .rr_op = .{3194 .data = .{ .rr_op = .{
3235 .rd = len_reg,3195 .rd = len_reg,
3236 .rn = .r0,3196 .rn = .r0,
...@@ -3272,7 +3232,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3272,7 +3232,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3272 // mov reg, 03232 // mov reg, 0
3273 _ = try self.addInst(.{3233 _ = try self.addInst(.{
3274 .tag = .mov,3234 .tag = .mov,
3275 .cond = .al,
3276 .data = .{ .rr_op = .{3235 .data = .{ .rr_op = .{
3277 .rd = reg,3236 .rd = reg,
3278 .rn = .r0,3237 .rn = .r0,
...@@ -3297,7 +3256,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3297,7 +3256,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3297 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {3256 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {
3298 _ = try self.addInst(.{3257 _ = try self.addInst(.{
3299 .tag = .mov,3258 .tag = .mov,
3300 .cond = .al,
3301 .data = .{ .rr_op = .{3259 .data = .{ .rr_op = .{
3302 .rd = reg,3260 .rd = reg,
3303 .rn = .r0,3261 .rn = .r0,
...@@ -3307,7 +3265,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3307,7 +3265,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3307 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {3265 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
3308 _ = try self.addInst(.{3266 _ = try self.addInst(.{
3309 .tag = .mvn,3267 .tag = .mvn,
3310 .cond = .al,
3311 .data = .{ .rr_op = .{3268 .data = .{ .rr_op = .{
3312 .rd = reg,3269 .rd = reg,
3313 .rn = .r0,3270 .rn = .r0,
...@@ -3318,7 +3275,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3318,7 +3275,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3318 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {3275 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
3319 _ = try self.addInst(.{3276 _ = try self.addInst(.{
3320 .tag = .movw,3277 .tag = .movw,
3321 .cond = .al,
3322 .data = .{ .r_imm16 = .{3278 .data = .{ .r_imm16 = .{
3323 .rd = reg,3279 .rd = reg,
3324 .imm16 = @intCast(u16, x),3280 .imm16 = @intCast(u16, x),
...@@ -3327,7 +3283,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3327,7 +3283,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3327 } else {3283 } else {
3328 _ = try self.addInst(.{3284 _ = try self.addInst(.{
3329 .tag = .mov,3285 .tag = .mov,
3330 .cond = .al,
3331 .data = .{ .rr_op = .{3286 .data = .{ .rr_op = .{
3332 .rd = reg,3287 .rd = reg,
3333 .rn = .r0,3288 .rn = .r0,
...@@ -3336,7 +3291,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3336,7 +3291,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3336 });3291 });
3337 _ = try self.addInst(.{3292 _ = try self.addInst(.{
3338 .tag = .orr,3293 .tag = .orr,
3339 .cond = .al,
3340 .data = .{ .rr_op = .{3294 .data = .{ .rr_op = .{
3341 .rd = reg,3295 .rd = reg,
3342 .rn = reg,3296 .rn = reg,
...@@ -3353,7 +3307,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3353,7 +3307,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3353 // movt reg, #0xaaaa3307 // movt reg, #0xaaaa
3354 _ = try self.addInst(.{3308 _ = try self.addInst(.{
3355 .tag = .movw,3309 .tag = .movw,
3356 .cond = .al,
3357 .data = .{ .r_imm16 = .{3310 .data = .{ .r_imm16 = .{
3358 .rd = reg,3311 .rd = reg,
3359 .imm16 = @truncate(u16, x),3312 .imm16 = @truncate(u16, x),
...@@ -3361,7 +3314,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3361,7 +3314,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3361 });3314 });
3362 _ = try self.addInst(.{3315 _ = try self.addInst(.{
3363 .tag = .movt,3316 .tag = .movt,
3364 .cond = .al,
3365 .data = .{ .r_imm16 = .{3317 .data = .{ .r_imm16 = .{
3366 .rd = reg,3318 .rd = reg,
3367 .imm16 = @truncate(u16, x >> 16),3319 .imm16 = @truncate(u16, x >> 16),
...@@ -3375,7 +3327,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3375,7 +3327,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3375 // orr reg, reg, #0xdd, 83327 // orr reg, reg, #0xdd, 8
3376 _ = try self.addInst(.{3328 _ = try self.addInst(.{
3377 .tag = .mov,3329 .tag = .mov,
3378 .cond = .al,
3379 .data = .{ .rr_op = .{3330 .data = .{ .rr_op = .{
3380 .rd = reg,3331 .rd = reg,
3381 .rn = .r0,3332 .rn = .r0,
...@@ -3384,7 +3335,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3384,7 +3335,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3384 });3335 });
3385 _ = try self.addInst(.{3336 _ = try self.addInst(.{
3386 .tag = .orr,3337 .tag = .orr,
3387 .cond = .al,
3388 .data = .{ .rr_op = .{3338 .data = .{ .rr_op = .{
3389 .rd = reg,3339 .rd = reg,
3390 .rn = reg,3340 .rn = reg,
...@@ -3393,7 +3343,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3393,7 +3343,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3393 });3343 });
3394 _ = try self.addInst(.{3344 _ = try self.addInst(.{
3395 .tag = .orr,3345 .tag = .orr,
3396 .cond = .al,
3397 .data = .{ .rr_op = .{3346 .data = .{ .rr_op = .{
3398 .rd = reg,3347 .rd = reg,
3399 .rn = reg,3348 .rn = reg,
...@@ -3402,7 +3351,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3402,7 +3351,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3402 });3351 });
3403 _ = try self.addInst(.{3352 _ = try self.addInst(.{
3404 .tag = .orr,3353 .tag = .orr,
3405 .cond = .al,
3406 .data = .{ .rr_op = .{3354 .data = .{ .rr_op = .{
3407 .rd = reg,3355 .rd = reg,
3408 .rn = reg,3356 .rn = reg,
...@@ -3420,7 +3368,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3420,7 +3368,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3420 // mov reg, src_reg3368 // mov reg, src_reg
3421 _ = try self.addInst(.{3369 _ = try self.addInst(.{
3422 .tag = .mov,3370 .tag = .mov,
3423 .cond = .al,
3424 .data = .{ .rr_op = .{3371 .data = .{ .rr_op = .{
3425 .rd = reg,3372 .rd = reg,
3426 .rn = .r0,3373 .rn = .r0,
...@@ -3434,7 +3381,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3434,7 +3381,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3434 try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });3381 try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });
3435 _ = try self.addInst(.{3382 _ = try self.addInst(.{
3436 .tag = .ldr,3383 .tag = .ldr,
3437 .cond = .al,
3438 .data = .{ .rr_offset = .{3384 .data = .{ .rr_offset = .{
3439 .rt = reg,3385 .rt = reg,
3440 .rn = reg,3386 .rn = reg,
...@@ -3461,7 +3407,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3461,7 +3407,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34613407
3462 _ = try self.addInst(.{3408 _ = try self.addInst(.{
3463 .tag = tag,3409 .tag = tag,
3464 .cond = .al,
3465 .data = .{ .rr_offset = .{3410 .data = .{ .rr_offset = .{
3466 .rt = reg,3411 .rt = reg,
3467 .rn = .fp,3412 .rn = .fp,
...@@ -3479,7 +3424,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3479,7 +3424,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34793424
3480 _ = try self.addInst(.{3425 _ = try self.addInst(.{
3481 .tag = .ldrh,3426 .tag = .ldrh,
3482 .cond = .al,
3483 .data = .{ .rr_extra_offset = .{3427 .data = .{ .rr_extra_offset = .{
3484 .rt = reg,3428 .rt = reg,
3485 .rn = .fp,3429 .rn = .fp,
...@@ -3507,7 +3451,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3507,7 +3451,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
35073451
3508 _ = try self.addInst(.{3452 _ = try self.addInst(.{
3509 .tag = tag,3453 .tag = tag,
3510 .cond = .al,
3511 .data = .{ .r_stack_offset = .{3454 .data = .{ .r_stack_offset = .{
3512 .rt = reg,3455 .rt = reg,
3513 .stack_offset = @intCast(u32, adj_off),3456 .stack_offset = @intCast(u32, adj_off),
...@@ -3551,7 +3494,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I...@@ -3551,7 +3494,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35513494
3552 _ = try self.addInst(.{3495 _ = try self.addInst(.{
3553 .tag = tag,3496 .tag = tag,
3554 .cond = .al,
3555 .data = .{ .rr_offset = .{3497 .data = .{ .rr_offset = .{
3556 .rt = reg,3498 .rt = reg,
3557 .rn = .sp,3499 .rn = .sp,
...@@ -3566,7 +3508,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I...@@ -3566,7 +3508,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35663508
3567 _ = try self.addInst(.{3509 _ = try self.addInst(.{
3568 .tag = .strh,3510 .tag = .strh,
3569 .cond = .al,
3570 .data = .{ .rr_extra_offset = .{3511 .data = .{ .rr_extra_offset = .{
3571 .rt = reg,3512 .rt = reg,
3572 .rn = .sp,3513 .rn = .sp,
src/arch/arm/Mir.zig+1-1
...@@ -20,7 +20,7 @@ extra: []const u32,...@@ -20,7 +20,7 @@ extra: []const u32,
2020
21pub const Inst = struct {21pub const Inst = struct {
22 tag: Tag,22 tag: Tag,
23 cond: bits.Condition,23 cond: bits.Condition = .al,
24 /// The meaning of this depends on `tag`.24 /// The meaning of this depends on `tag`.
25 data: Data,25 data: Data,
2626