authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-07 22:52:52+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-09 14:16:29+01:00
log77ca77cf144e3f7e8be53b6e4220a4efc313628b
treef7c23b14aa8f503f9358e4e312b9727b8c512e18
parentd66c97d0ef0434ce0814d1921877b9ffa877a645
signaturelock-open Commit is signed but in an unrecognized format.

stage2 ARM: make Mir.Inst.cond = .al default

2 files changed, 1 insertions(+), 60 deletions(-)

src/arch/arm/CodeGen.zig-59
......@@ -338,7 +338,6 @@ fn addInst(self: *Self, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {
338338fn addNop(self: *Self) error{OutOfMemory}!Mir.Inst.Index {
339339 return try self.addInst(.{
340340 .tag = .nop,
341 .cond = .al,
342341 .data = .{ .nop = {} },
343342 });
344343}
......@@ -371,7 +370,6 @@ fn gen(self: *Self) !void {
371370 // mov fp, sp
372371 _ = try self.addInst(.{
373372 .tag = .mov,
374 .cond = .al,
375373 .data = .{ .rr_op = .{
376374 .rd = .fp,
377375 .rn = .r0,
......@@ -405,7 +403,6 @@ fn gen(self: *Self) !void {
405403
406404 self.mir_instructions.set(push_reloc, .{
407405 .tag = .push,
408 .cond = .al,
409406 .data = .{ .register_list = saved_regs },
410407 });
411408
......@@ -416,7 +413,6 @@ fn gen(self: *Self) !void {
416413 if (Instruction.Operand.fromU32(stack_size)) |op| {
417414 self.mir_instructions.set(sub_reloc, .{
418415 .tag = .sub,
419 .cond = .al,
420416 .data = .{ .rr_op = .{ .rd = .sp, .rn = .sp, .op = op } },
421417 });
422418 } else {
......@@ -440,7 +436,6 @@ fn gen(self: *Self) !void {
440436 } else for (self.exitlude_jump_relocs.items) |jmp_reloc| {
441437 self.mir_instructions.set(jmp_reloc, .{
442438 .tag = .b,
443 .cond = .al,
444439 .data = .{ .inst = @intCast(u32, self.mir_instructions.len) },
445440 });
446441 }
......@@ -452,7 +447,6 @@ fn gen(self: *Self) !void {
452447 // mov sp, fp
453448 _ = try self.addInst(.{
454449 .tag = .mov,
455 .cond = .al,
456450 .data = .{ .rr_op = .{
457451 .rd = .sp,
458452 .rn = .r0,
......@@ -463,7 +457,6 @@ fn gen(self: *Self) !void {
463457 // pop {fp, pc}
464458 _ = try self.addInst(.{
465459 .tag = .pop,
466 .cond = .al,
467460 .data = .{ .register_list = saved_regs },
468461 });
469462 } else {
......@@ -1251,7 +1244,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12511244
12521245 _ = try self.addInst(.{
12531246 .tag = tag,
1254 .cond = .al,
12551247 .data = .{ .rr_offset = .{
12561248 .rt = dst_reg,
12571249 .rn = base_mcv.register,
......@@ -1262,7 +1254,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12621254 2 => {
12631255 _ = try self.addInst(.{
12641256 .tag = .ldrh,
1265 .cond = .al,
12661257 .data = .{ .rr_extra_offset = .{
12671258 .rt = dst_reg,
12681259 .rn = base_mcv.register,
......@@ -1406,7 +1397,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14061397 .register => |dst_reg| {
14071398 _ = try self.addInst(.{
14081399 .tag = .ldr,
1409 .cond = .al,
14101400 .data = .{ .rr_offset = .{
14111401 .rt = dst_reg,
14121402 .rn = reg,
......@@ -1430,7 +1420,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14301420 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});
14311421 _ = try self.addInst(.{
14321422 .tag = .ldr,
1433 .cond = .al,
14341423 .data = .{ .rr_offset = .{
14351424 .rt = tmp_regs[0],
14361425 .rn = reg,
......@@ -1439,7 +1428,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14391428 });
14401429 _ = try self.addInst(.{
14411430 .tag = .ldr,
1442 .cond = .al,
14431431 .data = .{ .rr_offset = .{
14441432 .rt = tmp_regs[1],
14451433 .rn = reg,
......@@ -1465,7 +1453,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14651453 };
14661454 _ = try self.addInst(.{
14671455 .tag = .sub,
1468 .cond = .al,
14691456 .data = .{ .rr_op = .{
14701457 .rd = dst_reg,
14711458 .rn = .fp,
......@@ -1479,7 +1466,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14791466 };
14801467 _ = try self.addInst(.{
14811468 .tag = .mov,
1482 .cond = .al,
14831469 .data = .{ .rr_op = .{
14841470 .rd = len_reg,
14851471 .rn = .r0,
......@@ -1560,7 +1546,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
15601546 .register => |value_reg| {
15611547 _ = try self.addInst(.{
15621548 .tag = .str,
1563 .cond = .al,
15641549 .data = .{ .rr_offset = .{
15651550 .rt = value_reg,
15661551 .rn = addr_reg,
......@@ -1866,7 +1851,6 @@ fn genArmBinOpCode(
18661851
18671852 _ = try self.addInst(.{
18681853 .tag = tag,
1869 .cond = .al,
18701854 .data = .{ .rr_op = .{
18711855 .rd = dst_reg,
18721856 .rn = op1,
......@@ -1879,7 +1863,6 @@ fn genArmBinOpCode(
18791863
18801864 _ = try self.addInst(.{
18811865 .tag = tag,
1882 .cond = .al,
18831866 .data = .{ .rr_op = .{
18841867 .rd = dst_reg,
18851868 .rn = op1,
......@@ -1890,7 +1873,6 @@ fn genArmBinOpCode(
18901873 .cmp_eq => {
18911874 _ = try self.addInst(.{
18921875 .tag = .cmp,
1893 .cond = .al,
18941876 .data = .{ .rr_op = .{
18951877 .rd = .r0,
18961878 .rn = op1,
......@@ -1916,7 +1898,6 @@ fn genArmBinOpCode(
19161898
19171899 _ = try self.addInst(.{
19181900 .tag = tag,
1919 .cond = .al,
19201901 .data = .{ .rr_shift = .{
19211902 .rd = dst_reg,
19221903 .rm = op1,
......@@ -1993,7 +1974,6 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19931974
19941975 _ = try self.addInst(.{
19951976 .tag = .mul,
1996 .cond = .al,
19971977 .data = .{ .rrr = .{
19981978 .rd = dst_mcv.register,
19991979 .rn = lhs_mcv.register,
......@@ -2045,7 +2025,6 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind
20452025
20462026 _ = try self.addInst(.{
20472027 .tag = .mul,
2048 .cond = .al,
20492028 .data = .{ .rrr = .{
20502029 .rd = dst_mcv.register,
20512030 .rn = lhs_mcv.register,
......@@ -2066,7 +2045,6 @@ fn genArmInlineMemcpy(
20662045 // mov count, #0
20672046 _ = try self.addInst(.{
20682047 .tag = .mov,
2069 .cond = .al,
20702048 .data = .{ .rr_op = .{
20712049 .rd = count,
20722050 .rn = .r0,
......@@ -2078,7 +2056,6 @@ fn genArmInlineMemcpy(
20782056 // cmp count, len
20792057 _ = try self.addInst(.{
20802058 .tag = .cmp,
2081 .cond = .al,
20822059 .data = .{ .rr_op = .{
20832060 .rd = .r0,
20842061 .rn = count,
......@@ -2096,7 +2073,6 @@ fn genArmInlineMemcpy(
20962073 // ldrb tmp, [src, count]
20972074 _ = try self.addInst(.{
20982075 .tag = .ldrb,
2099 .cond = .al,
21002076 .data = .{ .rr_offset = .{
21012077 .rt = tmp,
21022078 .rn = src,
......@@ -2107,7 +2083,6 @@ fn genArmInlineMemcpy(
21072083 // strb tmp, [src, count]
21082084 _ = try self.addInst(.{
21092085 .tag = .strb,
2110 .cond = .al,
21112086 .data = .{ .rr_offset = .{
21122087 .rt = tmp,
21132088 .rn = dst,
......@@ -2118,7 +2093,6 @@ fn genArmInlineMemcpy(
21182093 // add count, count, #1
21192094 _ = try self.addInst(.{
21202095 .tag = .add,
2121 .cond = .al,
21222096 .data = .{ .rr_op = .{
21232097 .rd = count,
21242098 .rn = count,
......@@ -2129,7 +2103,6 @@ fn genArmInlineMemcpy(
21292103 // b loop
21302104 _ = try self.addInst(.{
21312105 .tag = .b,
2132 .cond = .al,
21332106 .data = .{ .inst = @intCast(u32, self.mir_instructions.len - 5) },
21342107 });
21352108
......@@ -2236,7 +2209,6 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
22362209fn airBreakpoint(self: *Self) !void {
22372210 _ = try self.addInst(.{
22382211 .tag = .bkpt,
2239 .cond = .al,
22402212 .data = .{ .imm16 = 0 },
22412213 });
22422214 return self.finishAirBookkeeping();
......@@ -2348,14 +2320,12 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
23482320 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
23492321 _ = try self.addInst(.{
23502322 .tag = .blx,
2351 .cond = .al,
23522323 .data = .{ .reg = .lr },
23532324 });
23542325 } else {
23552326 return self.fail("TODO fix blx emulation for ARM <v5", .{});
23562327 // _ = try self.addInst(.{
23572328 // .tag = .mov,
2358 // .cond = .al,
23592329 // .data = .{ .rr_op = .{
23602330 // .rd = .lr,
23612331 // .rn = .r0,
......@@ -2364,7 +2334,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
23642334 // });
23652335 // _ = try self.addInst(.{
23662336 // .tag = .bx,
2367 // .cond = .al,
23682337 // .data = .{ .reg = .lr },
23692338 // });
23702339 }
......@@ -2539,7 +2508,6 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
25392508 // bne ...
25402509 _ = try self.addInst(.{
25412510 .tag = .cmp,
2542 .cond = .al,
25432511 .data = .{ .rr_op = .{
25442512 .rd = .r0,
25452513 .rn = reg,
......@@ -2889,7 +2857,6 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
28892857fn jump(self: *Self, inst: Mir.Inst.Index) !void {
28902858 _ = try self.addInst(.{
28912859 .tag = .b,
2892 .cond = .al,
28932860 .data = .{ .inst = inst },
28942861 });
28952862}
......@@ -2973,7 +2940,6 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {
29732940 // Emit a jump with a relocation. It will be patched up after the block ends.
29742941 try block_data.relocs.append(self.gpa, try self.addInst(.{
29752942 .tag = .b,
2976 .cond = .al,
29772943 .data = .{ .inst = undefined }, // populated later through performReloc
29782944 }));
29792945}
......@@ -3029,7 +2995,6 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
30292995 if (mem.eql(u8, asm_source, "svc #0")) {
30302996 _ = try self.addInst(.{
30312997 .tag = .svc,
3032 .cond = .al,
30332998 .data = .{ .imm24 = 0 },
30342999 });
30353000 } else {
......@@ -3135,7 +3100,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31353100
31363101 _ = try self.addInst(.{
31373102 .tag = tag,
3138 .cond = .al,
31393103 .data = .{ .rr_offset = .{
31403104 .rt = reg,
31413105 .rn = .fp,
......@@ -3153,7 +3117,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31533117
31543118 _ = try self.addInst(.{
31553119 .tag = .strh,
3156 .cond = .al,
31573120 .data = .{ .rr_extra_offset = .{
31583121 .rt = reg,
31593122 .rn = .fp,
......@@ -3200,7 +3163,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
32003163 };
32013164 _ = try self.addInst(.{
32023165 .tag = .sub,
3203 .cond = .al,
32043166 .data = .{ .rr_op = .{
32053167 .rd = src_reg,
32063168 .rn = .fp,
......@@ -3215,7 +3177,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
32153177 };
32163178 _ = try self.addInst(.{
32173179 .tag = .sub,
3218 .cond = .al,
32193180 .data = .{ .rr_op = .{
32203181 .rd = dst_reg,
32213182 .rn = .fp,
......@@ -3230,7 +3191,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
32303191 };
32313192 _ = try self.addInst(.{
32323193 .tag = .mov,
3233 .cond = .al,
32343194 .data = .{ .rr_op = .{
32353195 .rd = len_reg,
32363196 .rn = .r0,
......@@ -3272,7 +3232,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
32723232 // mov reg, 0
32733233 _ = try self.addInst(.{
32743234 .tag = .mov,
3275 .cond = .al,
32763235 .data = .{ .rr_op = .{
32773236 .rd = reg,
32783237 .rn = .r0,
......@@ -3297,7 +3256,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
32973256 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {
32983257 _ = try self.addInst(.{
32993258 .tag = .mov,
3300 .cond = .al,
33013259 .data = .{ .rr_op = .{
33023260 .rd = reg,
33033261 .rn = .r0,
......@@ -3307,7 +3265,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33073265 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
33083266 _ = try self.addInst(.{
33093267 .tag = .mvn,
3310 .cond = .al,
33113268 .data = .{ .rr_op = .{
33123269 .rd = reg,
33133270 .rn = .r0,
......@@ -3318,7 +3275,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33183275 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
33193276 _ = try self.addInst(.{
33203277 .tag = .movw,
3321 .cond = .al,
33223278 .data = .{ .r_imm16 = .{
33233279 .rd = reg,
33243280 .imm16 = @intCast(u16, x),
......@@ -3327,7 +3283,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33273283 } else {
33283284 _ = try self.addInst(.{
33293285 .tag = .mov,
3330 .cond = .al,
33313286 .data = .{ .rr_op = .{
33323287 .rd = reg,
33333288 .rn = .r0,
......@@ -3336,7 +3291,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33363291 });
33373292 _ = try self.addInst(.{
33383293 .tag = .orr,
3339 .cond = .al,
33403294 .data = .{ .rr_op = .{
33413295 .rd = reg,
33423296 .rn = reg,
......@@ -3353,7 +3307,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33533307 // movt reg, #0xaaaa
33543308 _ = try self.addInst(.{
33553309 .tag = .movw,
3356 .cond = .al,
33573310 .data = .{ .r_imm16 = .{
33583311 .rd = reg,
33593312 .imm16 = @truncate(u16, x),
......@@ -3361,7 +3314,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33613314 });
33623315 _ = try self.addInst(.{
33633316 .tag = .movt,
3364 .cond = .al,
33653317 .data = .{ .r_imm16 = .{
33663318 .rd = reg,
33673319 .imm16 = @truncate(u16, x >> 16),
......@@ -3375,7 +3327,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33753327 // orr reg, reg, #0xdd, 8
33763328 _ = try self.addInst(.{
33773329 .tag = .mov,
3378 .cond = .al,
33793330 .data = .{ .rr_op = .{
33803331 .rd = reg,
33813332 .rn = .r0,
......@@ -3384,7 +3335,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33843335 });
33853336 _ = try self.addInst(.{
33863337 .tag = .orr,
3387 .cond = .al,
33883338 .data = .{ .rr_op = .{
33893339 .rd = reg,
33903340 .rn = reg,
......@@ -3393,7 +3343,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
33933343 });
33943344 _ = try self.addInst(.{
33953345 .tag = .orr,
3396 .cond = .al,
33973346 .data = .{ .rr_op = .{
33983347 .rd = reg,
33993348 .rn = reg,
......@@ -3402,7 +3351,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34023351 });
34033352 _ = try self.addInst(.{
34043353 .tag = .orr,
3405 .cond = .al,
34063354 .data = .{ .rr_op = .{
34073355 .rd = reg,
34083356 .rn = reg,
......@@ -3420,7 +3368,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34203368 // mov reg, src_reg
34213369 _ = try self.addInst(.{
34223370 .tag = .mov,
3423 .cond = .al,
34243371 .data = .{ .rr_op = .{
34253372 .rd = reg,
34263373 .rn = .r0,
......@@ -3434,7 +3381,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34343381 try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });
34353382 _ = try self.addInst(.{
34363383 .tag = .ldr,
3437 .cond = .al,
34383384 .data = .{ .rr_offset = .{
34393385 .rt = reg,
34403386 .rn = reg,
......@@ -3461,7 +3407,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34613407
34623408 _ = try self.addInst(.{
34633409 .tag = tag,
3464 .cond = .al,
34653410 .data = .{ .rr_offset = .{
34663411 .rt = reg,
34673412 .rn = .fp,
......@@ -3479,7 +3424,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34793424
34803425 _ = try self.addInst(.{
34813426 .tag = .ldrh,
3482 .cond = .al,
34833427 .data = .{ .rr_extra_offset = .{
34843428 .rt = reg,
34853429 .rn = .fp,
......@@ -3507,7 +3451,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
35073451
35083452 _ = try self.addInst(.{
35093453 .tag = tag,
3510 .cond = .al,
35113454 .data = .{ .r_stack_offset = .{
35123455 .rt = reg,
35133456 .stack_offset = @intCast(u32, adj_off),
......@@ -3551,7 +3494,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35513494
35523495 _ = try self.addInst(.{
35533496 .tag = tag,
3554 .cond = .al,
35553497 .data = .{ .rr_offset = .{
35563498 .rt = reg,
35573499 .rn = .sp,
......@@ -3566,7 +3508,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35663508
35673509 _ = try self.addInst(.{
35683510 .tag = .strh,
3569 .cond = .al,
35703511 .data = .{ .rr_extra_offset = .{
35713512 .rt = reg,
35723513 .rn = .sp,
src/arch/arm/Mir.zig+1-1
......@@ -20,7 +20,7 @@ extra: []const u32,
2020
2121pub const Inst = struct {
2222 tag: Tag,
23 cond: bits.Condition,
23 cond: bits.Condition = .al,
2424 /// The meaning of this depends on `tag`.
2525 data: Data,
2626