authorgravatar for xq@random-projects.netFelix "xq" Queißner <xq@random-projects.net> 2024-10-04 22:53:28+02:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-10-04 13:53:28-07:00
log7c74edec8d7d97677033d8a688e02ee32d82ab43
tree8704f54815734e78861274fe8734b263082d07c5
parent3e62cb5c90608580558fff1af24af68735778392
signaturebadge-check Signed by PGP key B5690EEEBB952194

Adds new cpu architectures propeller1 and propeller2. (#21563)

* Adds new cpu architectures propeller1 and propeller2. These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores. Resolves #21559 * Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2 * Fixes missing switch prongs in src/codegen/llvm.zig * Fixes order in std.Target.Arch --------- Co-authored-by: Felix "xq" Queißner <git@random-projects.net>

10 files changed, 87 insertions(+), 1 deletions(-)

lib/std/Target.zig+31
...@@ -648,6 +648,7 @@ pub const wasm = @import("Target/wasm.zig");...@@ -648,6 +648,7 @@ pub const wasm = @import("Target/wasm.zig");
648pub const x86 = @import("Target/x86.zig");648pub const x86 = @import("Target/x86.zig");
649pub const xcore = @import("Target/xcore.zig");649pub const xcore = @import("Target/xcore.zig");
650pub const xtensa = @import("Target/xtensa.zig");650pub const xtensa = @import("Target/xtensa.zig");
651pub const propeller = @import("Target/propeller.zig");
651652
652pub const Abi = enum {653pub const Abi = enum {
653 none,654 none,
...@@ -882,6 +883,9 @@ pub fn toElfMachine(target: Target) std.elf.EM {...@@ -882,6 +883,9 @@ pub fn toElfMachine(target: Target) std.elf.EM {
882 .xcore => .XCORE,883 .xcore => .XCORE,
883 .xtensa => .XTENSA,884 .xtensa => .XTENSA,
884885
886 .propeller1 => .PROPELLER,
887 .propeller2 => .PROPELLER2,
888
885 .nvptx,889 .nvptx,
886 .nvptx64,890 .nvptx64,
887 .spirv,891 .spirv,
...@@ -941,6 +945,8 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {...@@ -941,6 +945,8 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
941 .wasm64,945 .wasm64,
942 .xcore,946 .xcore,
943 .xtensa,947 .xtensa,
948 .propeller1,
949 .propeller2,
944 => .UNKNOWN,950 => .UNKNOWN,
945 };951 };
946}952}
...@@ -1156,6 +1162,8 @@ pub const Cpu = struct {...@@ -1156,6 +1162,8 @@ pub const Cpu = struct {
1156 powerpcle,1162 powerpcle,
1157 powerpc64,1163 powerpc64,
1158 powerpc64le,1164 powerpc64le,
1165 propeller1,
1166 propeller2,
1159 riscv32,1167 riscv32,
1160 riscv64,1168 riscv64,
1161 s390x,1169 s390x,
...@@ -1309,6 +1317,14 @@ pub const Cpu = struct {...@@ -1309,6 +1317,14 @@ pub const Cpu = struct {
1309 };1317 };
1310 }1318 }
13111319
1320 /// Returns if the architecture is a Parallax propeller architecture.
1321 pub inline fn isPropeller(arch: Arch) bool {
1322 return switch (arch) {
1323 .propeller1, .propeller2 => true,
1324 else => false,
1325 };
1326 }
1327
1312 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {1328 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
1313 for (arch.allCpuModels()) |cpu| {1329 for (arch.allCpuModels()) |cpu| {
1314 if (std.mem.eql(u8, cpu_name, cpu.name)) {1330 if (std.mem.eql(u8, cpu_name, cpu.name)) {
...@@ -1353,6 +1369,8 @@ pub const Cpu = struct {...@@ -1353,6 +1369,8 @@ pub const Cpu = struct {
1353 .loongarch32,1369 .loongarch32,
1354 .loongarch64,1370 .loongarch64,
1355 .arc,1371 .arc,
1372 .propeller1,
1373 .propeller2,
1356 => .little,1374 => .little,
13571375
1358 .armeb,1376 .armeb,
...@@ -1385,6 +1403,10 @@ pub const Cpu = struct {...@@ -1385,6 +1403,10 @@ pub const Cpu = struct {
1385 .input, .output, .uniform => is_spirv,1403 .input, .output, .uniform => is_spirv,
1386 // TODO this should also check how many flash banks the cpu has1404 // TODO this should also check how many flash banks the cpu has
1387 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,1405 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
1406
1407 // Propeller address spaces:
1408 .cog, .hub => arch.isPropeller(),
1409 .lut => (arch == .propeller2),
1388 };1410 };
1389 }1411 }
13901412
...@@ -1405,6 +1427,7 @@ pub const Cpu = struct {...@@ -1405,6 +1427,7 @@ pub const Cpu = struct {
1405 .nvptx, .nvptx64 => "nvptx",1427 .nvptx, .nvptx64 => "nvptx",
1406 .wasm32, .wasm64 => "wasm",1428 .wasm32, .wasm64 => "wasm",
1407 .spirv, .spirv32, .spirv64 => "spirv",1429 .spirv, .spirv32, .spirv64 => "spirv",
1430 .propeller1, .propeller2 => "propeller",
1408 else => @tagName(arch),1431 else => @tagName(arch),
1409 };1432 };
1410 }1433 }
...@@ -1819,6 +1842,8 @@ pub const DynamicLinker = struct {...@@ -1819,6 +1842,8 @@ pub const DynamicLinker = struct {
1819 .spirv,1842 .spirv,
1820 .spirv32,1843 .spirv32,
1821 .spirv64,1844 .spirv64,
1845 .propeller1,
1846 .propeller2,
1822 => none,1847 => none,
18231848
1824 // TODO go over each item in this list and either move it to the above list, or1849 // TODO go over each item in this list and either move it to the above list, or
...@@ -1928,6 +1953,8 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1928,6 +1953,8 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1928 .spirv32,1953 .spirv32,
1929 .loongarch32,1954 .loongarch32,
1930 .xtensa,1955 .xtensa,
1956 .propeller1,
1957 .propeller2,
1931 => 32,1958 => 32,
19321959
1933 .aarch64,1960 .aarch64,
...@@ -2432,6 +2459,8 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {...@@ -2432,6 +2459,8 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
2432 .kalimba,2459 .kalimba,
2433 .spu_2,2460 .spu_2,
2434 .xtensa,2461 .xtensa,
2462 .propeller1,
2463 .propeller2,
2435 => 4,2464 => 4,
24362465
2437 .amdgcn,2466 .amdgcn,
...@@ -2536,6 +2565,8 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {...@@ -2536,6 +2565,8 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
2536 .kalimba,2565 .kalimba,
2537 .spu_2,2566 .spu_2,
2538 .xtensa,2567 .xtensa,
2568 .propeller1,
2569 .propeller2,
2539 => 4,2570 => 4,
25402571
2541 .arc,2572 .arc,
lib/std/Target/propeller.zig created+20
...@@ -0,0 +1,20 @@
1const std = @import("../std.zig");
2const CpuFeature = std.Target.Cpu.Feature;
3const CpuModel = std.Target.Cpu.Model;
4
5pub const Feature = enum {};
6
7pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
8pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
9pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
10pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
11
12pub const all_features: [0]CpuFeature = .{};
13
14pub const cpu = struct {
15 pub const generic = CpuModel{
16 .name = "generic",
17 .llvm_name = null,
18 .features = featureSet(&[_]Feature{}),
19 };
20};
lib/std/builtin.zig+11
...@@ -236,6 +236,17 @@ pub const AddressSpace = enum(u5) {...@@ -236,6 +236,17 @@ pub const AddressSpace = enum(u5) {
236 flash3,236 flash3,
237 flash4,237 flash4,
238 flash5,238 flash5,
239
240 // Propeller address spaces.
241
242 /// This address space only addresses the cog-local ram.
243 cog,
244
245 /// This address space only addresses shared hub ram.
246 hub,
247
248 /// This address space only addresses the "lookup" ram
249 lut,
239};250};
240251
241/// This data structure is used by the Zig language code generation and252/// This data structure is used by the Zig language code generation and
lib/std/elf.zig+8
...@@ -1628,6 +1628,14 @@ pub const EM = enum(u16) {...@@ -1628,6 +1628,14 @@ pub const EM = enum(u16) {
1628 /// Adapteva's Epiphany architecture1628 /// Adapteva's Epiphany architecture
1629 ADAPTEVA_EPIPHANY = 0x1223,1629 ADAPTEVA_EPIPHANY = 0x1223,
16301630
1631 /// Parallax Propeller (P1)
1632 /// This value is an unofficial ELF value used in: https://github.com/parallaxinc/propgcc
1633 PROPELLER = 0x5072,
1634
1635 /// Parallax Propeller 2 (P2)
1636 /// This value is an unofficial ELF value used in: https://github.com/ne75/llvm-project
1637 PROPELLER2 = 300,
1638
1631 _,1639 _,
1632};1640};
16331641
src/Sema.zig+3
...@@ -37672,6 +37672,9 @@ pub fn analyzeAsAddressSpace(...@@ -37672,6 +37672,9 @@ pub fn analyzeAsAddressSpace(
37672 .constant => is_gpu and (ctx == .constant),37672 .constant => is_gpu and (ctx == .constant),
37673 // TODO this should also check how many flash banks the cpu has37673 // TODO this should also check how many flash banks the cpu has
37674 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,37674 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
37675
37676 .cog, .hub => arch.isPropeller(),
37677 .lut => (arch == .propeller2),
37675 };37678 };
3767637679
37677 if (!supported) {37680 if (!supported) {
src/Type.zig+1
...@@ -1641,6 +1641,7 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {...@@ -1641,6 +1641,7 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1641 .avr => 1,1641 .avr => 1,
1642 .msp430 => 2,1642 .msp430 => 2,
1643 .xcore => 4,1643 .xcore => 4,
1644 .propeller1, .propeller2 => 4,
16441645
1645 .arm,1646 .arm,
1646 .armeb,1647 .armeb,
src/Zcu.zig+2
...@@ -3000,6 +3000,8 @@ pub fn atomicPtrAlignment(...@@ -3000,6 +3000,8 @@ pub fn atomicPtrAlignment(
3000 .spirv32,3000 .spirv32,
3001 .loongarch32,3001 .loongarch32,
3002 .xtensa,3002 .xtensa,
3003 .propeller1,
3004 .propeller2,
3003 => 32,3005 => 32,
30043006
3005 .amdgcn,3007 .amdgcn,
src/codegen/llvm.zig+6-1
...@@ -88,7 +88,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -88,7 +88,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
8888
89 .kalimba,89 .kalimba,
90 .spu_2,90 .spu_2,
91 .propeller1,
92 .propeller2,
91 => unreachable, // Gated by hasLlvmSupport().93 => unreachable, // Gated by hasLlvmSupport().
94
92 };95 };
93 try llvm_triple.appendSlice(llvm_arch);96 try llvm_triple.appendSlice(llvm_arch);
9497
...@@ -281,7 +284,7 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -281,7 +284,7 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
281 .wasm32 => .wasm32,284 .wasm32 => .wasm32,
282 .wasm64 => .wasm64,285 .wasm64 => .wasm64,
283 .ve => .ve,286 .ve => .ve,
284 .spu_2 => .UnknownArch,287 .propeller1, .propeller2, .spu_2 => .UnknownArch,
285 };288 };
286}289}
287290
...@@ -12714,6 +12717,8 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -12714,6 +12717,8 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12714 // LLVM does does not have a backend for these.12717 // LLVM does does not have a backend for these.
12715 .kalimba,12718 .kalimba,
12716 .spu_2,12719 .spu_2,
12720 .propeller1,
12721 .propeller2,
12717 => unreachable,12722 => unreachable,
12718 }12723 }
12719}12724}
src/codegen/spirv.zig+3
...@@ -1856,6 +1856,9 @@ const NavGen = struct {...@@ -1856,6 +1856,9 @@ const NavGen = struct {
1856 .flash3,1856 .flash3,
1857 .flash4,1857 .flash4,
1858 .flash5,1858 .flash5,
1859 .cog,
1860 .lut,
1861 .hub,
1859 => unreachable,1862 => unreachable,
1860 };1863 };
1861 }1864 }
src/target.zig+2
...@@ -168,6 +168,8 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -168,6 +168,8 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
168 // No LLVM backend exists.168 // No LLVM backend exists.
169 .kalimba,169 .kalimba,
170 .spu_2,170 .spu_2,
171 .propeller1,
172 .propeller2,
171 => false,173 => false,
172 };174 };
173}175}