authorgravatar for xq@random-projects.netFelix "xq" Queißner <xq@random-projects.net> 2024-10-04 22:53:28+02:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-10-04 13:53:28-07:00
log7c74edec8d7d97677033d8a688e02ee32d82ab43
tree8704f54815734e78861274fe8734b263082d07c5
parent3e62cb5c90608580558fff1af24af68735778392
signaturebadge-check Signed by PGP key B5690EEEBB952194

Adds new cpu architectures propeller1 and propeller2. (#21563)

* Adds new cpu architectures propeller1 and propeller2. These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores. Resolves #21559 * Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2 * Fixes missing switch prongs in src/codegen/llvm.zig * Fixes order in std.Target.Arch --------- Co-authored-by: Felix "xq" Queißner <git@random-projects.net>

10 files changed, 87 insertions(+), 1 deletions(-)

lib/std/Target.zig+31
......@@ -648,6 +648,7 @@ pub const wasm = @import("Target/wasm.zig");
648648pub const x86 = @import("Target/x86.zig");
649649pub const xcore = @import("Target/xcore.zig");
650650pub const xtensa = @import("Target/xtensa.zig");
651pub const propeller = @import("Target/propeller.zig");
651652
652653pub const Abi = enum {
653654 none,
......@@ -882,6 +883,9 @@ pub fn toElfMachine(target: Target) std.elf.EM {
882883 .xcore => .XCORE,
883884 .xtensa => .XTENSA,
884885
886 .propeller1 => .PROPELLER,
887 .propeller2 => .PROPELLER2,
888
885889 .nvptx,
886890 .nvptx64,
887891 .spirv,
......@@ -941,6 +945,8 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
941945 .wasm64,
942946 .xcore,
943947 .xtensa,
948 .propeller1,
949 .propeller2,
944950 => .UNKNOWN,
945951 };
946952}
......@@ -1156,6 +1162,8 @@ pub const Cpu = struct {
11561162 powerpcle,
11571163 powerpc64,
11581164 powerpc64le,
1165 propeller1,
1166 propeller2,
11591167 riscv32,
11601168 riscv64,
11611169 s390x,
......@@ -1309,6 +1317,14 @@ pub const Cpu = struct {
13091317 };
13101318 }
13111319
1320 /// Returns if the architecture is a Parallax propeller architecture.
1321 pub inline fn isPropeller(arch: Arch) bool {
1322 return switch (arch) {
1323 .propeller1, .propeller2 => true,
1324 else => false,
1325 };
1326 }
1327
13121328 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
13131329 for (arch.allCpuModels()) |cpu| {
13141330 if (std.mem.eql(u8, cpu_name, cpu.name)) {
......@@ -1353,6 +1369,8 @@ pub const Cpu = struct {
13531369 .loongarch32,
13541370 .loongarch64,
13551371 .arc,
1372 .propeller1,
1373 .propeller2,
13561374 => .little,
13571375
13581376 .armeb,
......@@ -1385,6 +1403,10 @@ pub const Cpu = struct {
13851403 .input, .output, .uniform => is_spirv,
13861404 // TODO this should also check how many flash banks the cpu has
13871405 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
1406
1407 // Propeller address spaces:
1408 .cog, .hub => arch.isPropeller(),
1409 .lut => (arch == .propeller2),
13881410 };
13891411 }
13901412
......@@ -1405,6 +1427,7 @@ pub const Cpu = struct {
14051427 .nvptx, .nvptx64 => "nvptx",
14061428 .wasm32, .wasm64 => "wasm",
14071429 .spirv, .spirv32, .spirv64 => "spirv",
1430 .propeller1, .propeller2 => "propeller",
14081431 else => @tagName(arch),
14091432 };
14101433 }
......@@ -1819,6 +1842,8 @@ pub const DynamicLinker = struct {
18191842 .spirv,
18201843 .spirv32,
18211844 .spirv64,
1845 .propeller1,
1846 .propeller2,
18221847 => none,
18231848
18241849 // TODO go over each item in this list and either move it to the above list, or
......@@ -1928,6 +1953,8 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
19281953 .spirv32,
19291954 .loongarch32,
19301955 .xtensa,
1956 .propeller1,
1957 .propeller2,
19311958 => 32,
19321959
19331960 .aarch64,
......@@ -2432,6 +2459,8 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
24322459 .kalimba,
24332460 .spu_2,
24342461 .xtensa,
2462 .propeller1,
2463 .propeller2,
24352464 => 4,
24362465
24372466 .amdgcn,
......@@ -2536,6 +2565,8 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
25362565 .kalimba,
25372566 .spu_2,
25382567 .xtensa,
2568 .propeller1,
2569 .propeller2,
25392570 => 4,
25402571
25412572 .arc,
lib/std/Target/propeller.zig created+20
......@@ -0,0 +1,20 @@
1const std = @import("../std.zig");
2const CpuFeature = std.Target.Cpu.Feature;
3const CpuModel = std.Target.Cpu.Model;
4
5pub const Feature = enum {};
6
7pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
8pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
9pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
10pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
11
12pub const all_features: [0]CpuFeature = .{};
13
14pub const cpu = struct {
15 pub const generic = CpuModel{
16 .name = "generic",
17 .llvm_name = null,
18 .features = featureSet(&[_]Feature{}),
19 };
20};
lib/std/builtin.zig+11
......@@ -236,6 +236,17 @@ pub const AddressSpace = enum(u5) {
236236 flash3,
237237 flash4,
238238 flash5,
239
240 // Propeller address spaces.
241
242 /// This address space only addresses the cog-local ram.
243 cog,
244
245 /// This address space only addresses shared hub ram.
246 hub,
247
248 /// This address space only addresses the "lookup" ram
249 lut,
239250};
240251
241252/// This data structure is used by the Zig language code generation and
lib/std/elf.zig+8
......@@ -1628,6 +1628,14 @@ pub const EM = enum(u16) {
16281628 /// Adapteva's Epiphany architecture
16291629 ADAPTEVA_EPIPHANY = 0x1223,
16301630
1631 /// Parallax Propeller (P1)
1632 /// This value is an unofficial ELF value used in: https://github.com/parallaxinc/propgcc
1633 PROPELLER = 0x5072,
1634
1635 /// Parallax Propeller 2 (P2)
1636 /// This value is an unofficial ELF value used in: https://github.com/ne75/llvm-project
1637 PROPELLER2 = 300,
1638
16311639 _,
16321640};
16331641
src/Sema.zig+3
......@@ -37672,6 +37672,9 @@ pub fn analyzeAsAddressSpace(
3767237672 .constant => is_gpu and (ctx == .constant),
3767337673 // TODO this should also check how many flash banks the cpu has
3767437674 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
37675
37676 .cog, .hub => arch.isPropeller(),
37677 .lut => (arch == .propeller2),
3767537678 };
3767637679
3767737680 if (!supported) {
src/Type.zig+1
......@@ -1641,6 +1641,7 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16411641 .avr => 1,
16421642 .msp430 => 2,
16431643 .xcore => 4,
1644 .propeller1, .propeller2 => 4,
16441645
16451646 .arm,
16461647 .armeb,
src/Zcu.zig+2
......@@ -3000,6 +3000,8 @@ pub fn atomicPtrAlignment(
30003000 .spirv32,
30013001 .loongarch32,
30023002 .xtensa,
3003 .propeller1,
3004 .propeller2,
30033005 => 32,
30043006
30053007 .amdgcn,
src/codegen/llvm.zig+6-1
......@@ -88,7 +88,10 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
8888
8989 .kalimba,
9090 .spu_2,
91 .propeller1,
92 .propeller2,
9193 => unreachable, // Gated by hasLlvmSupport().
94
9295 };
9396 try llvm_triple.appendSlice(llvm_arch);
9497
......@@ -281,7 +284,7 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
281284 .wasm32 => .wasm32,
282285 .wasm64 => .wasm64,
283286 .ve => .ve,
284 .spu_2 => .UnknownArch,
287 .propeller1, .propeller2, .spu_2 => .UnknownArch,
285288 };
286289}
287290
......@@ -12714,6 +12717,8 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1271412717 // LLVM does does not have a backend for these.
1271512718 .kalimba,
1271612719 .spu_2,
12720 .propeller1,
12721 .propeller2,
1271712722 => unreachable,
1271812723 }
1271912724}
src/codegen/spirv.zig+3
......@@ -1856,6 +1856,9 @@ const NavGen = struct {
18561856 .flash3,
18571857 .flash4,
18581858 .flash5,
1859 .cog,
1860 .lut,
1861 .hub,
18591862 => unreachable,
18601863 };
18611864 }
src/target.zig+2
......@@ -168,6 +168,8 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
168168 // No LLVM backend exists.
169169 .kalimba,
170170 .spu_2,
171 .propeller1,
172 .propeller2,
171173 => false,
172174 };
173175}