authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-03-19 19:48:27+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-03-19 19:48:27+01:00
log7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2
tree6444e2961ca1509b573de24e8c34ffacaa4a529a
parent956d9f4ce019243ed0bd7f587acdeb1af4b5f61c
signaturelock-open Commit is signed but in an unrecognized format.

stage2 RISCV64: implement move register to register

3 files changed, 33 insertions(+), 0 deletions(-)

src/arch/riscv64/CodeGen.zig+14
...@@ -2074,6 +2074,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -2074,6 +2074,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
2074 return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf2074 return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf
2075 }2075 }
2076 },2076 },
2077 .register => |src_reg| {
2078 // If the registers are the same, nothing to do.
2079 if (src_reg.id() == reg.id())
2080 return;
2081
2082 // mov reg, src_reg
2083 _ = try self.addInst(.{
2084 .tag = .mv,
2085 .data = .{ .rr = .{
2086 .rd = reg,
2087 .rs = src_reg,
2088 } },
2089 });
2090 },
2077 .memory => |addr| {2091 .memory => |addr| {
2078 // The value is in memory at a hard-coded address.2092 // The value is in memory at a hard-coded address.
2079 // If the type is a pointer, it means the pointer address is at this memory location.2093 // If the type is a pointer, it means the pointer address is at this memory location.
src/arch/riscv64/Emit.zig+11
...@@ -56,6 +56,8 @@ pub fn emitMir(...@@ -56,6 +56,8 @@ pub fn emitMir(
56 .dbg_prologue_end => try emit.mirDebugPrologueEnd(),56 .dbg_prologue_end => try emit.mirDebugPrologueEnd(),
57 .dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),57 .dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
5858
59 .mv => try emit.mirRR(inst),
60
59 .nop => try emit.mirNop(inst),61 .nop => try emit.mirNop(inst),
60 .ret => try emit.mirNop(inst),62 .ret => try emit.mirNop(inst),
6163
...@@ -186,6 +188,15 @@ fn mirDebugEpilogueBegin(self: *Emit) !void {...@@ -186,6 +188,15 @@ fn mirDebugEpilogueBegin(self: *Emit) !void {
186 }188 }
187}189}
188190
191fn mirRR(emit: *Emit, inst: Mir.Inst.Index) !void {
192 const tag = emit.mir.instructions.items(.tag)[inst];
193 const rr = emit.mir.instructions.items(.data)[inst].rr;
194
195 switch (tag) {
196 .mv => try emit.writeInstruction(Instruction.addi(rr.rd, rr.rs, 0)),
197 else => unreachable,
198 }
199}
189fn mirUType(emit: *Emit, inst: Mir.Inst.Index) !void {200fn mirUType(emit: *Emit, inst: Mir.Inst.Index) !void {
190 const tag = emit.mir.instructions.items(.tag)[inst];201 const tag = emit.mir.instructions.items(.tag)[inst];
191 const u_type = emit.mir.instructions.items(.data)[inst].u_type;202 const u_type = emit.mir.instructions.items(.data)[inst].u_type;
src/arch/riscv64/Mir.zig+8
...@@ -36,6 +36,7 @@ pub const Inst = struct {...@@ -36,6 +36,7 @@ pub const Inst = struct {
36 jalr,36 jalr,
37 ld,37 ld,
38 lui,38 lui,
39 mv,
39 nop,40 nop,
40 ret,41 ret,
41 sd,42 sd,
...@@ -68,6 +69,13 @@ pub const Inst = struct {...@@ -68,6 +69,13 @@ pub const Inst = struct {
68 ///69 ///
69 /// Used by e.g. blr70 /// Used by e.g. blr
70 reg: Register,71 reg: Register,
72 /// Two registers
73 ///
74 /// Used by e.g. mv
75 rr: struct {
76 rd: Register,
77 rs: Register,
78 },
71 /// I-Type79 /// I-Type
72 ///80 ///
73 /// Used by e.g. jalr81 /// Used by e.g. jalr